LXR linux/arch/arm/mach-bcmring/core.c

   1/*
   2 *  derived from linux/arch/arm/mach-versatile/core.c
   3 *  linux/arch/arm/mach-bcmring/core.c
   4 *
   5 *  Copyright (C) 1999 - 2003 ARM Limited
   6 *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22/* Portions copyright Broadcom 2008 */
  23
  24#include <linux/init.h>
  25#include <linux/device.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/platform_device.h>
  28#include <linux/sysdev.h>
  29#include <linux/interrupt.h>
  30#include <linux/amba/bus.h>
  31#include <linux/clocksource.h>
  32#include <linux/clockchips.h>
  33
  34#include <mach/csp/mm_addr.h>
  35#include <mach/hardware.h>
  36#include <asm/clkdev.h>
  37#include <linux/io.h>
  38#include <asm/irq.h>
  39#include <asm/hardware/arm_timer.h>
  40#include <asm/mach-types.h>
  41
  42#include <asm/mach/arch.h>
  43#include <asm/mach/flash.h>
  44#include <asm/mach/irq.h>
  45#include <asm/mach/time.h>
  46#include <asm/mach/map.h>
  47
  48#include <cfg_global.h>
  49
  50#include "clock.h"
  51
  52#include <csp/secHw.h>
  53#include <mach/csp/secHw_def.h>
  54#include <mach/csp/chipcHw_inline.h>
  55#include <mach/csp/tmrHw_reg.h>
  56
  57#define AMBA_DEVICE(name, initname, base, plat, size)       \
  58static struct amba_device name##_device = {     \
  59   .dev = {                                     \
  60      .coherent_dma_mask = ~0,                  \
  61      .init_name = initname,                    \
  62      .platform_data = plat                     \
  63   },                                           \
  64   .res = {                                     \
  65      .start = MM_ADDR_IO_##base,               \
  66                .end = MM_ADDR_IO_##base + (size) - 1,    \
  67      .flags = IORESOURCE_MEM                   \
  68   },                                           \
  69   .dma_mask = ~0,                              \
  70   .irq = {                                     \
  71      IRQ_##base                                \
  72   }                                            \
  73}
  74
  75
  76AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
  77AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
  78
  79static struct clk pll1_clk = {
  80        .name = "PLL1",
  81        .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
  82        .rate_hz = 2000000000,
  83        .use_cnt = 7,
  84};
  85
  86static struct clk uart_clk = {
  87        .name = "UART",
  88        .type = CLK_TYPE_PROGRAMMABLE,
  89        .csp_id = chipcHw_CLOCK_UART,
  90        .rate_hz = HW_CFG_UART_CLK_HZ,
  91        .parent = &pll1_clk,
  92};
  93
  94static struct clk_lookup lookups[] = {
  95        {                       /* UART0 */
  96         .dev_id = "uarta",
  97         .clk = &uart_clk,
  98         }, {                   /* UART1 */
  99             .dev_id = "uartb",
 100             .clk = &uart_clk,
 101             }
 102};
 103
 104static struct amba_device *amba_devs[] __initdata = {
 105        &uartA_device,
 106        &uartB_device,
 107};
 108
 109void __init bcmring_amba_init(void)
 110{
 111        int i;
 112        u32 bus_clock;
 113
 114/* Linux is run initially in non-secure mode. Secure peripherals */
 115/* generate FIQ, and must be handled in secure mode. Until we have */
 116/* a linux security monitor implementation, keep everything in */
 117/* non-secure mode. */
 118        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
 119        secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
 120                          secHw_BLK_MASK_KEY_SCAN |
 121                          secHw_BLK_MASK_TOUCH_SCREEN |
 122                          secHw_BLK_MASK_UART0 |
 123                          secHw_BLK_MASK_UART1 |
 124                          secHw_BLK_MASK_WATCHDOG |
 125                          secHw_BLK_MASK_SPUM |
 126                          secHw_BLK_MASK_DDR2 |
 127                          secHw_BLK_MASK_SPU |
 128                          secHw_BLK_MASK_PKA |
 129                          secHw_BLK_MASK_RNG |
 130                          secHw_BLK_MASK_RTC |
 131                          secHw_BLK_MASK_OTP |
 132                          secHw_BLK_MASK_BOOT |
 133                          secHw_BLK_MASK_MPU |
 134                          secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
 135
 136        /* Only the devices attached to the AMBA bus are enabled just before the bus is */
 137        /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
 138        /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
 139        /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
 140        bus_clock = chipcHw_REG_BUS_CLOCK_GE
 141            | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
 142
 143        chipcHw_busInterfaceClockEnable(bus_clock);
 144
 145        for (i = 0; i < ARRAY_SIZE(lookups); i++)
 146                clkdev_add(&lookups[i]);
 147
 148        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 149                struct amba_device *d = amba_devs[i];
 150                amba_device_register(d, &iomem_resource);
 151        }
 152}
 153
 154/*
 155 * Where is the timer (VA)?
 156 */
 157#define TIMER0_VA_BASE           MM_IO_BASE_TMR
 158#define TIMER1_VA_BASE          (MM_IO_BASE_TMR + 0x20)
 159#define TIMER2_VA_BASE          (MM_IO_BASE_TMR + 0x40)
 160#define TIMER3_VA_BASE          (MM_IO_BASE_TMR + 0x60)
 161
 162/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
 163#if defined(CONFIG_ARCH_FPGA11107)
 164/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
 165/* slow down Linux's sense of time */
 166#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 167#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 168#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
 169#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
 170#else
 171#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 172#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 173#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
 174#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
 175#endif
 176
 177#define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ
 178
 179/*
 180 *  These are useconds NOT ticks.
 181 *
 182 */
 183#define mSEC_1                          1000
 184#define mSEC_5                          (mSEC_1 * 5)
 185#define mSEC_10                         (mSEC_1 * 10)
 186#define mSEC_25                         (mSEC_1 * 25)
 187#define SEC_1                           (mSEC_1 * 1000)
 188
 189/*
 190 * How long is the timer interval?
 191 */
 192#define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 193#if TIMER_INTERVAL >= 0x100000
 194#define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 195#define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 196#define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 197#elif TIMER_INTERVAL >= 0x10000
 198#define TIMER_RELOAD    (TIMER_INTERVAL >> 4)   /* Divide by 16 */
 199#define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 200#define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 201#else
 202#define TIMER_RELOAD    (TIMER_INTERVAL)
 203#define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 204#define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 205#endif
 206
 207static void timer_set_mode(enum clock_event_mode mode,
 208                           struct clock_event_device *clk)
 209{
 210        unsigned long ctrl;
 211
 212        switch (mode) {
 213        case CLOCK_EVT_MODE_PERIODIC:
 214                writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 215
 216                ctrl = TIMER_CTRL_PERIODIC;
 217                ctrl |=
 218                    TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 219                    TIMER_CTRL_ENABLE;
 220                break;
 221        case CLOCK_EVT_MODE_ONESHOT:
 222                /* period set, and timer enabled in 'next_event' hook */
 223                ctrl = TIMER_CTRL_ONESHOT;
 224                ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 225                break;
 226        case CLOCK_EVT_MODE_UNUSED:
 227        case CLOCK_EVT_MODE_SHUTDOWN:
 228        default:
 229                ctrl = 0;
 230        }
 231
 232        writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 233}
 234
 235static int timer_set_next_event(unsigned long evt,
 236                                struct clock_event_device *unused)
 237{
 238        unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 239
 240        writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 241        writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 242
 243        return 0;
 244}
 245
 246static struct clock_event_device timer0_clockevent = {
 247        .name = "timer0",
 248        .shift = 32,
 249        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 250        .set_mode = timer_set_mode,
 251        .set_next_event = timer_set_next_event,
 252};
 253
 254/*
 255 * IRQ handler for the timer
 256 */
 257static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
 258{
 259        struct clock_event_device *evt = &timer0_clockevent;
 260
 261        writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 262
 263        evt->event_handler(evt);
 264
 265        return IRQ_HANDLED;
 266}
 267
 268static struct irqaction bcmring_timer_irq = {
 269        .name = "bcmring Timer Tick",
 270        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 271        .handler = bcmring_timer_interrupt,
 272};
 273
 274static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
 275{
 276        return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
 277}
 278
 279static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
 280{
 281        return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 282}
 283
 284static struct clocksource clocksource_bcmring_timer1 = {
 285        .name = "timer1",
 286        .rating = 200,
 287        .read = bcmring_get_cycles_timer1,
 288        .mask = CLOCKSOURCE_MASK(32),
 289        .shift = 20,
 290        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 291};
 292
 293static struct clocksource clocksource_bcmring_timer3 = {
 294        .name = "timer3",
 295        .rating = 100,
 296        .read = bcmring_get_cycles_timer3,
 297        .mask = CLOCKSOURCE_MASK(32),
 298        .shift = 20,
 299        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 300};
 301
 302static int __init bcmring_clocksource_init(void)
 303{
 304        /* setup timer1 as free-running clocksource */
 305        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 306        writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
 307        writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
 308        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 309               TIMER1_VA_BASE + TIMER_CTRL);
 310
 311        clocksource_bcmring_timer1.mult =
 312            clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
 313                                 clocksource_bcmring_timer1.shift);
 314        clocksource_register(&clocksource_bcmring_timer1);
 315
 316        /* setup timer3 as free-running clocksource */
 317        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 318        writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 319        writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 320        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 321               TIMER3_VA_BASE + TIMER_CTRL);
 322
 323        clocksource_bcmring_timer3.mult =
 324            clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
 325                                 clocksource_bcmring_timer3.shift);
 326        clocksource_register(&clocksource_bcmring_timer3);
 327
 328        return 0;
 329}
 330
 331/*
 332 * Set up timer interrupt, and return the current time in seconds.
 333 */
 334void __init bcmring_init_timer(void)
 335{
 336        printk(KERN_INFO "bcmring_init_timer\n");
 337        /*
 338         * Initialise to a known state (all timers off)
 339         */
 340        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 341        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 342        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 343        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 344
 345        /*
 346         * Make irqs happen for the system timer
 347         */
 348        setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
 349
 350        bcmring_clocksource_init();
 351
 352        timer0_clockevent.mult =
 353            div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 354        timer0_clockevent.max_delta_ns =
 355            clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 356        timer0_clockevent.min_delta_ns =
 357            clockevent_delta2ns(0xf, &timer0_clockevent);
 358
 359        timer0_clockevent.cpumask = cpumask_of(0);
 360        clockevents_register_device(&timer0_clockevent);
 361}
 362
 363struct sys_timer bcmring_timer = {
 364        .init = bcmring_init_timer,
 365};
 366