1/***************************************************************************** 2* Copyright 2009 Broadcom Corporation. All rights reserved. 3* 4* Unless you and Broadcom execute a separate written software license 5* agreement governing use of this software, this software is licensed to you 6* under the terms of the GNU General Public License version 2, available at 7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). 8* 9* Notwithstanding the above, under no circumstances may you combine this 10* software in any way with any other Broadcom software provided under a 11* license other than the GPL, without Broadcom's express prior written 12* consent. 13*****************************************************************************/ 14 15#ifndef CAP_INLINE_H 16#define CAP_INLINE_H 17 18/* ---- Include Files ---------------------------------------------------- */ 19#include <mach/csp/cap.h> 20#include <cfg_global.h> 21 22/* ---- Public Constants and Types --------------------------------------- */ 23#define CAP_CONFIG0_VPM_DIS 0x00000001 24#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002 25#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004 26#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008 27#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010 28#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020 29#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040 30#define CAP_CONFIG0_USB0_DIS 0x00000080 31#define CAP_CONFIG0_USB1_DIS 0x00000100 32#define CAP_CONFIG0_TSC_DIS 0x00000200 33#define CAP_CONFIG0_EHSS0_DIS 0x00000400 34#define CAP_CONFIG0_EHSS1_DIS 0x00000800 35#define CAP_CONFIG0_SDIO0_DIS 0x00001000 36#define CAP_CONFIG0_SDIO1_DIS 0x00002000 37#define CAP_CONFIG0_UARTB_DIS 0x00004000 38#define CAP_CONFIG0_KEYPAD_DIS 0x00008000 39#define CAP_CONFIG0_CLCD_DIS 0x00010000 40#define CAP_CONFIG0_GE_DIS 0x00020000 41#define CAP_CONFIG0_LEDM_DIS 0x00040000 42#define CAP_CONFIG0_BBL_DIS 0x00080000 43#define CAP_CONFIG0_VDEC_DIS 0x00100000 44#define CAP_CONFIG0_PIF_DIS 0x00200000 45#define CAP_CONFIG0_RESERVED1_DIS 0x00400000 46#define CAP_CONFIG0_RESERVED2_DIS 0x00800000 47 48#define CAP_CONFIG1_APMA_DIS 0x00000001 49#define CAP_CONFIG1_APMB_DIS 0x00000002 50#define CAP_CONFIG1_APMC_DIS 0x00000004 51#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600 52#define CAP_CONFIG1_CLCD_RES_SHIFT 9 53#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT) 54#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT) 55#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT) 56#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT) 57 58#define CAP_CONFIG2_SPU_DIS 0x00000010 59#define CAP_CONFIG2_PKA_DIS 0x00000020 60#define CAP_CONFIG2_RNG_DIS 0x00000080 61 62#if (CFG_GLOBAL_CHIP == BCM11107) 63#define capConfig0 0 64#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA 65#define capConfig2 0 66#define CAP_APM_MAX_NUM_CHANS 3 67#elif (CFG_GLOBAL_CHIP == FPGA11107) 68#define capConfig0 0 69#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA 70#define capConfig2 0 71#define CAP_APM_MAX_NUM_CHANS 3 72#elif (CFG_GLOBAL_CHIP == BCM11109) 73#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) 74#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) 75#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) 76#define CAP_APM_MAX_NUM_CHANS 2 77#elif (CFG_GLOBAL_CHIP == BCM11170) 78#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) 79#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) 80#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) 81#define CAP_APM_MAX_NUM_CHANS 2 82#elif (CFG_GLOBAL_CHIP == BCM11110) 83#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) 84#define capConfig1 CAP_CONFIG1_APMC_DIS 85#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) 86#define CAP_APM_MAX_NUM_CHANS 2 87#elif (CFG_GLOBAL_CHIP == BCM11211) 88#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS) 89#define capConfig1 CAP_CONFIG1_APMC_DIS 90#define capConfig2 0 91#define CAP_APM_MAX_NUM_CHANS 2 92#else 93#error CFG_GLOBAL_CHIP type capabilities not defined 94#endif 95 96#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) 97#define CAP_HW_CFG_ARM_CLK_HZ 500000000 98#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) 99#define CAP_HW_CFG_ARM_CLK_HZ 300000000 100#elif (CFG_GLOBAL_CHIP == BCM11211) 101#define CAP_HW_CFG_ARM_CLK_HZ 666666666 102#else 103#error CFG_GLOBAL_CHIP type capabilities not defined 104#endif 105 106#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107)) 107#define CAP_HW_CFG_VPM_CLK_HZ 333333333 108#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) 109#define CAP_HW_CFG_VPM_CLK_HZ 200000000 110#else 111#error CFG_GLOBAL_CHIP type capabilities not defined 112#endif 113 114/* ---- Public Variable Externs ------------------------------------------ */ 115/* ---- Public Function Prototypes --------------------------------------- */ 116 117/**************************************************************************** 118* cap_isPresent - 119* 120* PURPOSE: 121* Determines if the chip has a certain capability present 122* 123* PARAMETERS: 124* capability - type of capability to determine if present 125* 126* RETURNS: 127* CAP_PRESENT or CAP_NOT_PRESENT 128****************************************************************************/ 129static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index) 130{ 131 CAP_RC_T returnVal = CAP_NOT_PRESENT; 132 133 switch (capability) { 134 case CAP_VPM: 135 { 136 if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) { 137 returnVal = CAP_PRESENT; 138 } 139 } 140 break; 141 142 case CAP_ETH_PHY: 143 { 144 if ((index == 0) 145 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) { 146 returnVal = CAP_PRESENT; 147 } 148 if ((index == 1) 149 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) { 150 returnVal = CAP_PRESENT; 151 } 152 } 153 break; 154 155 case CAP_ETH_GMII: 156 { 157 if ((index == 0) 158 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) { 159 returnVal = CAP_PRESENT; 160 } 161 if ((index == 1) 162 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) { 163 returnVal = CAP_PRESENT; 164 } 165 } 166 break; 167 168 case CAP_ETH_SGMII: 169 { 170 if ((index == 0) 171 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) { 172 returnVal = CAP_PRESENT; 173 } 174 if ((index == 1) 175 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) { 176 returnVal = CAP_PRESENT; 177 } 178 } 179 break; 180 181 case CAP_USB: 182 { 183 if ((index == 0) 184 && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) { 185 returnVal = CAP_PRESENT; 186 } 187 if ((index == 1) 188 && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) { 189 returnVal = CAP_PRESENT; 190 } 191 } 192 break; 193 194 case CAP_TSC: 195 { 196 if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) { 197 returnVal = CAP_PRESENT; 198 } 199 } 200 break; 201 202 case CAP_EHSS: 203 { 204 if ((index == 0) 205 && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) { 206 returnVal = CAP_PRESENT; 207 } 208 if ((index == 1) 209 && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) { 210 returnVal = CAP_PRESENT; 211 } 212 } 213 break; 214 215 case CAP_SDIO: 216 { 217 if ((index == 0) 218 && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) { 219 returnVal = CAP_PRESENT; 220 } 221 if ((index == 1) 222 && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) { 223 returnVal = CAP_PRESENT; 224 } 225 } 226 break; 227 228 case CAP_UARTB: 229 { 230 if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) { 231 returnVal = CAP_PRESENT; 232 } 233 } 234 break; 235 236 case CAP_KEYPAD: 237 { 238 if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) { 239 returnVal = CAP_PRESENT; 240 } 241 } 242 break; 243 244 case CAP_CLCD: 245 { 246 if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) { 247 returnVal = CAP_PRESENT; 248 } 249 } 250 break; 251 252 case CAP_GE: 253 { 254 if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) { 255 returnVal = CAP_PRESENT; 256 } 257 } 258 break; 259 260 case CAP_LEDM: 261 { 262 if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) { 263 returnVal = CAP_PRESENT; 264 } 265 } 266 break; 267 268 case CAP_BBL: 269 { 270 if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) { 271 returnVal = CAP_PRESENT; 272 } 273 } 274 break; 275 276 case CAP_VDEC: 277 { 278 if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) { 279 returnVal = CAP_PRESENT; 280 } 281 } 282 break; 283 284 case CAP_PIF: 285 { 286 if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) { 287 returnVal = CAP_PRESENT; 288 } 289 } 290 break; 291 292 case CAP_APM: 293 { 294 if ((index == 0) 295 && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) { 296 returnVal = CAP_PRESENT; 297 } 298 if ((index == 1) 299 && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) { 300 returnVal = CAP_PRESENT; 301 } 302 if ((index == 2) 303 && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) { 304 returnVal = CAP_PRESENT; 305 } 306 } 307 break; 308 309 case CAP_SPU: 310 { 311 if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) { 312 returnVal = CAP_PRESENT; 313 } 314 } 315 break; 316 317 case CAP_PKA: 318 { 319 if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) { 320 returnVal = CAP_PRESENT; 321 } 322 } 323 break; 324 325 case CAP_RNG: 326 { 327 if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) { 328 returnVal = CAP_PRESENT; 329 } 330 } 331 break; 332 333 default: 334 { 335 } 336 break; 337 } 338 return returnVal; 339} 340 341/**************************************************************************** 342* cap_getMaxArmSpeedHz - 343* 344* PURPOSE: 345* Determines the maximum speed of the ARM CPU 346* 347* PARAMETERS: 348* none 349* 350* RETURNS: 351* clock speed in Hz that the ARM processor is able to run at 352****************************************************************************/ 353static inline uint32_t cap_getMaxArmSpeedHz(void) 354{ 355#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) 356 return 500000000; 357#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) 358 return 300000000; 359#elif (CFG_GLOBAL_CHIP == BCM11211) 360 return 666666666; 361#else 362#error CFG_GLOBAL_CHIP type capabilities not defined 363#endif 364} 365 366/**************************************************************************** 367* cap_getMaxVpmSpeedHz - 368* 369* PURPOSE: 370* Determines the maximum speed of the VPM 371* 372* PARAMETERS: 373* none 374* 375* RETURNS: 376* clock speed in Hz that the VPM is able to run at 377****************************************************************************/ 378static inline uint32_t cap_getMaxVpmSpeedHz(void) 379{ 380#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107)) 381 return 333333333; 382#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) 383 return 200000000; 384#else 385#error CFG_GLOBAL_CHIP type capabilities not defined 386#endif 387} 388 389/**************************************************************************** 390* cap_getMaxLcdRes - 391* 392* PURPOSE: 393* Determines the maximum LCD resolution capabilities 394* 395* PARAMETERS: 396* none 397* 398* RETURNS: 399* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA 400* 401****************************************************************************/ 402static inline CAP_LCD_RES_T cap_getMaxLcdRes(void) 403{ 404 return (CAP_LCD_RES_T) 405 ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >> 406 CAP_CONFIG1_CLCD_RES_SHIFT); 407} 408 409#endif 410