linux/arch/arm/mach-ixp2000/ixdp2x01.c
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   1/*
   2 * arch/arm/mach-ixp2000/ixdp2x01.c
   3 *
   4 * Code common to Intel IXDP2401 and IXDP2801 platforms
   5 *
   6 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
   7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   8 *
   9 * Copyright (C) 2002-2003 Intel Corp.
  10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11 *
  12 *  This program is free software; you can redistribute  it and/or modify it
  13 *  under  the terms of  the GNU General  Public License as published by the
  14 *  Free Software Foundation;  either version 2 of the  License, or (at your
  15 *  option) any later version.
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/init.h>
  20#include <linux/mm.h>
  21#include <linux/sched.h>
  22#include <linux/interrupt.h>
  23#include <linux/bitops.h>
  24#include <linux/pci.h>
  25#include <linux/ioport.h>
  26#include <linux/slab.h>
  27#include <linux/delay.h>
  28#include <linux/serial.h>
  29#include <linux/tty.h>
  30#include <linux/serial_core.h>
  31#include <linux/platform_device.h>
  32#include <linux/serial_8250.h>
  33#include <linux/io.h>
  34
  35#include <asm/irq.h>
  36#include <asm/pgtable.h>
  37#include <asm/page.h>
  38#include <asm/system.h>
  39#include <mach/hardware.h>
  40#include <asm/mach-types.h>
  41
  42#include <asm/mach/pci.h>
  43#include <asm/mach/map.h>
  44#include <asm/mach/irq.h>
  45#include <asm/mach/time.h>
  46#include <asm/mach/arch.h>
  47#include <asm/mach/flash.h>
  48
  49/*************************************************************************
  50 * IXDP2x01 IRQ Handling
  51 *************************************************************************/
  52static void ixdp2x01_irq_mask(unsigned int irq)
  53{
  54        ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
  55                                IXP2000_BOARD_IRQ_MASK(irq));
  56}
  57
  58static void ixdp2x01_irq_unmask(unsigned int irq)
  59{
  60        ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
  61                                IXP2000_BOARD_IRQ_MASK(irq));
  62}
  63
  64static u32 valid_irq_mask;
  65
  66static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
  67{
  68        u32 ex_interrupt;
  69        int i;
  70
  71        desc->chip->mask(irq);
  72
  73        ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
  74
  75        if (!ex_interrupt) {
  76                printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
  77                return;
  78        }
  79
  80        for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
  81                if (ex_interrupt & (1 << i)) {
  82                        int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
  83                        generic_handle_irq(cpld_irq);
  84                }
  85        }
  86
  87        desc->chip->unmask(irq);
  88}
  89
  90static struct irq_chip ixdp2x01_irq_chip = {
  91        .mask   = ixdp2x01_irq_mask,
  92        .ack    = ixdp2x01_irq_mask,
  93        .unmask = ixdp2x01_irq_unmask
  94};
  95
  96/*
  97 * We only do anything if we are the master NPU on the board.
  98 * The slave NPU only has the ethernet chip going directly to
  99 * the PCIB interrupt input.
 100 */
 101void __init ixdp2x01_init_irq(void)
 102{
 103        int irq = 0;
 104
 105        /* initialize chip specific interrupts */
 106        ixp2000_init_irq();
 107
 108        if (machine_is_ixdp2401())
 109                valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
 110        else
 111                valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
 112
 113        /* Mask all interrupts from CPLD, disable simulation */
 114        ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
 115        ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
 116
 117        for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
 118                if (irq & valid_irq_mask) {
 119                        set_irq_chip(irq, &ixdp2x01_irq_chip);
 120                        set_irq_handler(irq, handle_level_irq);
 121                        set_irq_flags(irq, IRQF_VALID);
 122                } else {
 123                        set_irq_flags(irq, 0);
 124                }
 125        }
 126
 127        /* Hook into PCI interrupts */
 128        set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
 129}
 130
 131
 132/*************************************************************************
 133 * IXDP2x01 memory map
 134 *************************************************************************/
 135static struct map_desc ixdp2x01_io_desc __initdata = {
 136        .virtual        = IXDP2X01_VIRT_CPLD_BASE, 
 137        .pfn            = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
 138        .length         = IXDP2X01_CPLD_REGION_SIZE,
 139        .type           = MT_DEVICE
 140};
 141
 142static void __init ixdp2x01_map_io(void)
 143{
 144        ixp2000_map_io();
 145        iotable_init(&ixdp2x01_io_desc, 1);
 146}
 147
 148
 149/*************************************************************************
 150 * IXDP2x01 serial ports
 151 *************************************************************************/
 152static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
 153        {
 154                .mapbase        = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
 155                .membase        = (char *)IXDP2X01_UART1_VIRT_BASE,
 156                .irq            = IRQ_IXDP2X01_UART1,
 157                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 158                .iotype         = UPIO_MEM32,
 159                .regshift       = 2,
 160                .uartclk        = IXDP2X01_UART_CLK,
 161        },
 162        { }
 163};
 164
 165static struct resource ixdp2x01_uart_resource1 = {
 166        .start          = IXDP2X01_UART1_PHYS_BASE,
 167        .end            = IXDP2X01_UART1_PHYS_BASE + 0xffff,
 168        .flags          = IORESOURCE_MEM,
 169};
 170
 171static struct platform_device ixdp2x01_serial_device1 = {
 172        .name           = "serial8250",
 173        .id             = PLAT8250_DEV_PLATFORM1,
 174        .dev            = {
 175                .platform_data          = ixdp2x01_serial_port1,
 176        },
 177        .num_resources  = 1,
 178        .resource       = &ixdp2x01_uart_resource1,
 179};
 180
 181static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
 182        {
 183                .mapbase        = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
 184                .membase        = (char *)IXDP2X01_UART2_VIRT_BASE,
 185                .irq            = IRQ_IXDP2X01_UART2,
 186                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 187                .iotype         = UPIO_MEM32,
 188                .regshift       = 2,
 189                .uartclk        = IXDP2X01_UART_CLK,
 190        }, 
 191        { }
 192};
 193
 194static struct resource ixdp2x01_uart_resource2 = {
 195        .start          = IXDP2X01_UART2_PHYS_BASE,
 196        .end            = IXDP2X01_UART2_PHYS_BASE + 0xffff,
 197        .flags          = IORESOURCE_MEM,
 198};
 199
 200static struct platform_device ixdp2x01_serial_device2 = {
 201        .name           = "serial8250",
 202        .id             = PLAT8250_DEV_PLATFORM2,
 203        .dev            = {
 204                .platform_data          = ixdp2x01_serial_port2,
 205        },
 206        .num_resources  = 1,
 207        .resource       = &ixdp2x01_uart_resource2,
 208};
 209
 210static void ixdp2x01_uart_init(void)
 211{
 212        platform_device_register(&ixdp2x01_serial_device1);
 213        platform_device_register(&ixdp2x01_serial_device2);
 214}
 215
 216
 217/*************************************************************************
 218 * IXDP2x01 timer tick configuration
 219 *************************************************************************/
 220static unsigned int ixdp2x01_clock;
 221
 222static int __init ixdp2x01_clock_setup(char *str)
 223{
 224        ixdp2x01_clock = simple_strtoul(str, NULL, 10);
 225
 226        return 1;
 227}
 228
 229__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
 230
 231static void __init ixdp2x01_timer_init(void)
 232{
 233        if (!ixdp2x01_clock)
 234                ixdp2x01_clock = 50000000;
 235
 236        ixp2000_init_time(ixdp2x01_clock);
 237}
 238
 239static struct sys_timer ixdp2x01_timer = {
 240        .init           = ixdp2x01_timer_init,
 241        .offset         = ixp2000_gettimeoffset,
 242};
 243
 244/*************************************************************************
 245 * IXDP2x01 PCI
 246 *************************************************************************/
 247void __init ixdp2x01_pci_preinit(void)
 248{
 249        ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
 250        ixp2000_pci_preinit();
 251        pcibios_setup("firmware");
 252}
 253
 254#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
 255
 256static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 257{
 258        u8 bus = dev->bus->number;
 259        u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
 260        struct pci_bus *tmp_bus = dev->bus;
 261
 262        /* Primary bus, no interrupts here */
 263        if (bus == 0) {
 264                return -1;
 265        }
 266
 267        /* Lookup first leaf in bus tree */
 268        while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
 269                tmp_bus = tmp_bus->parent;
 270        }
 271
 272        /* Select between known bridges */
 273        switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
 274        /* Device is located after first MB bridge */
 275        case 0x0008:
 276                if (tmp_bus == dev->bus) {
 277                        /* Device is located directly after first MB bridge */
 278                        switch (devpin) {
 279                        case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
 280                                if (machine_is_ixdp2401())
 281                                        return IRQ_IXDP2401_INTA_82546;
 282                                return -1;
 283                        case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
 284                                if (machine_is_ixdp2401())
 285                                        return IRQ_IXDP2401_INTB_82546;
 286                                return -1;
 287                        case DEVPIN(0, 1):      /* PMC INTA# */
 288                                return IRQ_IXDP2X01_SPCI_PMC_INTA;
 289                        case DEVPIN(0, 2):      /* PMC INTB# */
 290                                return IRQ_IXDP2X01_SPCI_PMC_INTB;
 291                        case DEVPIN(0, 3):      /* PMC INTC# */
 292                                return IRQ_IXDP2X01_SPCI_PMC_INTC;
 293                        case DEVPIN(0, 4):      /* PMC INTD# */
 294                                return IRQ_IXDP2X01_SPCI_PMC_INTD;
 295                        }
 296                }
 297                break;
 298        case 0x0010:
 299                if (tmp_bus == dev->bus) {
 300                        /* Device is located directly after second MB bridge */
 301                        /* Secondary bus of second bridge */
 302                        switch (devpin) {
 303                        case DEVPIN(0, 1):      /* DB#0 */
 304                                return IRQ_IXDP2X01_SPCI_DB_0;
 305                        case DEVPIN(1, 1):      /* DB#1 */
 306                                return IRQ_IXDP2X01_SPCI_DB_1;
 307                        }
 308                } else {
 309                        /* Device is located indirectly after second MB bridge */
 310                        /* Not supported now */
 311                }
 312                break;
 313        }
 314
 315        return -1;
 316}
 317
 318
 319static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
 320{
 321        sys->mem_offset = 0xe0000000;
 322
 323        if (machine_is_ixdp2801() || machine_is_ixdp28x5())
 324                sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
 325
 326        return ixp2000_pci_setup(nr, sys);
 327}
 328
 329struct hw_pci ixdp2x01_pci __initdata = {
 330        .nr_controllers = 1,
 331        .setup          = ixdp2x01_pci_setup,
 332        .preinit        = ixdp2x01_pci_preinit,
 333        .scan           = ixp2000_pci_scan_bus,
 334        .map_irq        = ixdp2x01_pci_map_irq,
 335};
 336
 337int __init ixdp2x01_pci_init(void)
 338{
 339        if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
 340                machine_is_ixdp28x5())
 341                pci_common_init(&ixdp2x01_pci);
 342
 343        return 0;
 344}
 345
 346subsys_initcall(ixdp2x01_pci_init);
 347
 348/*************************************************************************
 349 * IXDP2x01 Machine Initialization
 350 *************************************************************************/
 351static struct flash_platform_data ixdp2x01_flash_platform_data = {
 352        .map_name       = "cfi_probe",
 353        .width          = 1,
 354};
 355
 356static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
 357{
 358        ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
 359                ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
 360        return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
 361}
 362
 363static struct ixp2000_flash_data ixdp2x01_flash_data = {
 364        .platform_data  = &ixdp2x01_flash_platform_data,
 365        .bank_setup     = ixdp2x01_flash_bank_setup
 366};
 367
 368static struct resource ixdp2x01_flash_resource = {
 369        .start          = 0xc4000000,
 370        .end            = 0xc4000000 + 0x01ffffff,
 371        .flags          = IORESOURCE_MEM,
 372};
 373
 374static struct platform_device ixdp2x01_flash = {
 375        .name           = "IXP2000-Flash",
 376        .id             = 0,
 377        .dev            = {
 378                .platform_data = &ixdp2x01_flash_data,
 379        },
 380        .num_resources  = 1,
 381        .resource       = &ixdp2x01_flash_resource,
 382};
 383
 384static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
 385        .sda_pin        = IXDP2X01_GPIO_SDA,
 386        .scl_pin        = IXDP2X01_GPIO_SCL,
 387};
 388
 389static struct platform_device ixdp2x01_i2c_controller = {
 390        .name           = "IXP2000-I2C",
 391        .id             = 0,
 392        .dev            = {
 393                .platform_data = &ixdp2x01_i2c_gpio_pins,
 394        },
 395        .num_resources  = 0
 396};
 397
 398static struct platform_device *ixdp2x01_devices[] __initdata = {
 399        &ixdp2x01_flash,
 400        &ixdp2x01_i2c_controller
 401};
 402
 403static void __init ixdp2x01_init_machine(void)
 404{
 405        ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
 406                (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
 407        
 408        ixdp2x01_flash_data.nr_banks =
 409                ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
 410
 411        platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
 412        ixp2000_uart_init();
 413        ixdp2x01_uart_init();
 414}
 415
 416
 417#ifdef CONFIG_ARCH_IXDP2401
 418MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
 419        /* Maintainer: MontaVista Software, Inc. */
 420        .phys_io        = IXP2000_UART_PHYS_BASE,
 421        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
 422        .boot_params    = 0x00000100,
 423        .map_io         = ixdp2x01_map_io,
 424        .init_irq       = ixdp2x01_init_irq,
 425        .timer          = &ixdp2x01_timer,
 426        .init_machine   = ixdp2x01_init_machine,
 427MACHINE_END
 428#endif
 429
 430#ifdef CONFIG_ARCH_IXDP2801
 431MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
 432        /* Maintainer: MontaVista Software, Inc. */
 433        .phys_io        = IXP2000_UART_PHYS_BASE,
 434        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
 435        .boot_params    = 0x00000100,
 436        .map_io         = ixdp2x01_map_io,
 437        .init_irq       = ixdp2x01_init_irq,
 438        .timer          = &ixdp2x01_timer,
 439        .init_machine   = ixdp2x01_init_machine,
 440MACHINE_END
 441
 442/*
 443 * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
 444 * changed the machine ID in the bootloader
 445 */
 446MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
 447        /* Maintainer: MontaVista Software, Inc. */
 448        .phys_io        = IXP2000_UART_PHYS_BASE,
 449        .io_pg_offst    = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
 450        .boot_params    = 0x00000100,
 451        .map_io         = ixdp2x01_map_io,
 452        .init_irq       = ixdp2x01_init_irq,
 453        .timer          = &ixdp2x01_timer,
 454        .init_machine   = ixdp2x01_init_machine,
 455MACHINE_END
 456#endif
 457
 458
 459