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18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/interrupt.h>
22#include <linux/mm.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/device.h>
28#include <linux/io.h>
29#include <asm/dma-mapping.h>
30
31#include <asm/cputype.h>
32#include <asm/irq.h>
33#include <asm/sizes.h>
34#include <asm/system.h>
35#include <asm/mach/pci.h>
36#include <mach/hardware.h>
37
38
39
40
41
42
43int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
44
45
46
47
48unsigned long ixp4xx_pci_reg_base = 0;
49
50
51
52
53
54
55
56
57static DEFINE_SPINLOCK(ixp4xx_pci_lock);
58
59
60
61
62static void crp_read(u32 ad_cbe, u32 *data)
63{
64 unsigned long flags;
65 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
66 *PCI_CRP_AD_CBE = ad_cbe;
67 *data = *PCI_CRP_RDATA;
68 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
69}
70
71
72
73
74static void crp_write(u32 ad_cbe, u32 data)
75{
76 unsigned long flags;
77 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
78 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
79 *PCI_CRP_WDATA = data;
80 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
81}
82
83static inline int check_master_abort(void)
84{
85
86 unsigned long isr = *PCI_ISR;
87
88 if (isr & PCI_ISR_PFE) {
89
90 *PCI_ISR = PCI_ISR_PFE;
91 pr_debug("%s failed\n", __func__);
92 return 1;
93 }
94
95 return 0;
96}
97
98int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
99{
100 unsigned long flags;
101 int retval = 0;
102 int i;
103
104 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
105
106 *PCI_NP_AD = addr;
107
108
109
110
111
112 for (i = 0; i < 8; i++) {
113 *PCI_NP_CBE = cmd;
114 *data = *PCI_NP_RDATA;
115 *data = *PCI_NP_RDATA;
116 }
117
118 if(check_master_abort())
119 retval = 1;
120
121 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
122 return retval;
123}
124
125int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
126{
127 unsigned long flags;
128 int retval = 0;
129
130 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
131
132 *PCI_NP_AD = addr;
133
134
135 *PCI_NP_CBE = cmd;
136
137
138 *data = *PCI_NP_RDATA;
139
140 if(check_master_abort())
141 retval = 1;
142
143 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
144 return retval;
145}
146
147int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
148{
149 unsigned long flags;
150 int retval = 0;
151
152 spin_lock_irqsave(&ixp4xx_pci_lock, flags);
153
154 *PCI_NP_AD = addr;
155
156
157 *PCI_NP_CBE = cmd;
158
159
160 *PCI_NP_WDATA = data;
161
162 if(check_master_abort())
163 retval = 1;
164
165 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
166 return retval;
167}
168
169static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
170{
171 u32 addr;
172 if (!bus_num) {
173
174 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
175 (where & ~3);
176 } else {
177
178 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
179 ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
180 }
181 return addr;
182}
183
184
185
186
187
188static u32 bytemask[] = {
189 0,
190 0xff,
191 0xffff,
192 0,
193 0xffffffff,
194};
195
196static u32 local_byte_lane_enable_bits(u32 n, int size)
197{
198 if (size == 1)
199 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
200 if (size == 2)
201 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
202 if (size == 4)
203 return 0;
204 return 0xffffffff;
205}
206
207static int local_read_config(int where, int size, u32 *value)
208{
209 u32 n, data;
210 pr_debug("local_read_config from %d size %d\n", where, size);
211 n = where % 4;
212 crp_read(where & ~3, &data);
213 *value = (data >> (8*n)) & bytemask[size];
214 pr_debug("local_read_config read %#x\n", *value);
215 return PCIBIOS_SUCCESSFUL;
216}
217
218static int local_write_config(int where, int size, u32 value)
219{
220 u32 n, byte_enables, data;
221 pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
222 n = where % 4;
223 byte_enables = local_byte_lane_enable_bits(n, size);
224 if (byte_enables == 0xffffffff)
225 return PCIBIOS_BAD_REGISTER_NUMBER;
226 data = value << (8*n);
227 crp_write((where & ~3) | byte_enables, data);
228 return PCIBIOS_SUCCESSFUL;
229}
230
231static u32 byte_lane_enable_bits(u32 n, int size)
232{
233 if (size == 1)
234 return (0xf & ~BIT(n)) << 4;
235 if (size == 2)
236 return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
237 if (size == 4)
238 return 0;
239 return 0xffffffff;
240}
241
242static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
243{
244 u32 n, byte_enables, addr, data;
245 u8 bus_num = bus->number;
246
247 pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
248 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
249
250 *value = 0xffffffff;
251 n = where % 4;
252 byte_enables = byte_lane_enable_bits(n, size);
253 if (byte_enables == 0xffffffff)
254 return PCIBIOS_BAD_REGISTER_NUMBER;
255
256 addr = ixp4xx_config_addr(bus_num, devfn, where);
257 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
258 return PCIBIOS_DEVICE_NOT_FOUND;
259
260 *value = (data >> (8*n)) & bytemask[size];
261 pr_debug("read_config_byte read %#x\n", *value);
262 return PCIBIOS_SUCCESSFUL;
263}
264
265static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
266{
267 u32 n, byte_enables, addr, data;
268 u8 bus_num = bus->number;
269
270 pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
271 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
272
273 n = where % 4;
274 byte_enables = byte_lane_enable_bits(n, size);
275 if (byte_enables == 0xffffffff)
276 return PCIBIOS_BAD_REGISTER_NUMBER;
277
278 addr = ixp4xx_config_addr(bus_num, devfn, where);
279 data = value << (8*n);
280 if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
281 return PCIBIOS_DEVICE_NOT_FOUND;
282
283 return PCIBIOS_SUCCESSFUL;
284}
285
286struct pci_ops ixp4xx_ops = {
287 .read = ixp4xx_pci_read_config,
288 .write = ixp4xx_pci_write_config,
289};
290
291
292
293
294static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
295{
296 u32 isr, status;
297
298 isr = *PCI_ISR;
299 local_read_config(PCI_STATUS, 2, &status);
300 pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
301 "status = %#x\n", addr, isr, status);
302
303
304 *PCI_ISR = PCI_ISR_PFE;
305 status |= PCI_STATUS_REC_MASTER_ABORT;
306 local_write_config(PCI_STATUS, 2, status);
307
308
309
310
311
312 if (fsr & (1 << 10))
313 regs->ARM_pc += 4;
314
315 return 0;
316}
317
318
319
320
321
322static int ixp4xx_pci_platform_notify(struct device *dev)
323{
324 if(dev->bus == &pci_bus_type) {
325 *dev->dma_mask = SZ_64M - 1;
326 dev->coherent_dma_mask = SZ_64M - 1;
327 dmabounce_register_dev(dev, 2048, 4096);
328 }
329 return 0;
330}
331
332static int ixp4xx_pci_platform_notify_remove(struct device *dev)
333{
334 if(dev->bus == &pci_bus_type) {
335 dmabounce_unregister_dev(dev);
336 }
337 return 0;
338}
339
340int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
341{
342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
343}
344
345
346
347
348
349
350
351void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
352 unsigned long *zhole_size)
353{
354 unsigned int sz = SZ_64M >> PAGE_SHIFT;
355
356
357
358
359 if (node || (zone_size[0] <= sz))
360 return;
361
362 zone_size[1] = zone_size[0] - sz;
363 zone_size[0] = sz;
364 zhole_size[1] = zhole_size[0];
365 zhole_size[0] = 0;
366}
367
368void __init ixp4xx_pci_preinit(void)
369{
370 unsigned long cpuid = read_cpuid_id();
371
372
373
374
375
376 if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
377 printk("PCI: IXP42x A0 silicon detected - "
378 "PCI Non-Prefetch Workaround Enabled\n");
379 ixp4xx_pci_read = ixp4xx_pci_read_errata;
380 } else
381 ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
382
383
384
385 hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
386
387 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
388
389
390
391
392
393 *PCI_PCIMEMBASE = 0x48494A4B;
394
395
396
397
398
399 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
400 ((PHYS_OFFSET & 0xFF000000) >> 8) +
401 ((PHYS_OFFSET & 0xFF000000) >> 16) +
402 ((PHYS_OFFSET & 0xFF000000) >> 24) +
403 0x00010203;
404
405 if (*PCI_CSR & PCI_CSR_HOST) {
406 printk("PCI: IXP4xx is host\n");
407
408 pr_debug("setup BARs in controller\n");
409
410
411
412
413
414 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
415 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
416 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
417 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
418
419
420
421
422
423 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
424
425
426
427
428 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
429 } else {
430 printk("PCI: IXP4xx is target - No bus scan performed\n");
431 }
432
433 printk("PCI: IXP4xx Using %s access for memory space\n",
434#ifndef CONFIG_IXP4XX_INDIRECT_PCI
435 "direct"
436#else
437 "indirect"
438#endif
439 );
440
441 pr_debug("clear error bits in ISR\n");
442 *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
443
444
445
446
447
448
449
450#ifdef __ARMEB__
451 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
452#else
453 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
454#endif
455
456 pr_debug("DONE\n");
457}
458
459int ixp4xx_setup(int nr, struct pci_sys_data *sys)
460{
461 struct resource *res;
462
463 if (nr >= 1)
464 return 0;
465
466 res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
467 if (res == NULL) {
468
469
470
471
472 panic("PCI: unable to allocate resources?\n");
473 }
474
475 local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
476
477 res[0].name = "PCI I/O Space";
478 res[0].start = 0x00000000;
479 res[0].end = 0x0000ffff;
480 res[0].flags = IORESOURCE_IO;
481
482 res[1].name = "PCI Memory Space";
483 res[1].start = PCIBIOS_MIN_MEM;
484#ifndef CONFIG_IXP4XX_INDIRECT_PCI
485 res[1].end = 0x4bffffff;
486#else
487 res[1].end = 0x4fffffff;
488#endif
489 res[1].flags = IORESOURCE_MEM;
490
491 request_resource(&ioport_resource, &res[0]);
492 request_resource(&iomem_resource, &res[1]);
493
494 sys->resource[0] = &res[0];
495 sys->resource[1] = &res[1];
496 sys->resource[2] = NULL;
497
498 platform_notify = ixp4xx_pci_platform_notify;
499 platform_notify_remove = ixp4xx_pci_platform_notify_remove;
500
501 return 1;
502}
503
504struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
505{
506 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
507}
508
509
510
511
512
513
514
515
516
517int
518pci_set_dma_mask(struct pci_dev *dev, u64 mask)
519{
520 if (mask >= SZ_64M - 1 )
521 return 0;
522
523 return -EIO;
524}
525
526int
527pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
528{
529 if (mask >= SZ_64M - 1 )
530 return 0;
531
532 return -EIO;
533}
534
535EXPORT_SYMBOL(ixp4xx_pci_read);
536EXPORT_SYMBOL(ixp4xx_pci_write);
537
538