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11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/serial.h>
15#include <linux/tty.h>
16#include <linux/serial_8250.h>
17#include <linux/slab.h>
18#include <linux/i2c-gpio.h>
19#include <linux/io.h>
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/nand.h>
22#include <linux/mtd/partitions.h>
23#include <linux/delay.h>
24
25#include <asm/types.h>
26#include <asm/setup.h>
27#include <asm/memory.h>
28#include <mach/hardware.h>
29#include <asm/mach-types.h>
30#include <asm/irq.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/flash.h>
33
34static struct flash_platform_data ixdp425_flash_data = {
35 .map_name = "cfi_probe",
36 .width = 2,
37};
38
39static struct resource ixdp425_flash_resource = {
40 .flags = IORESOURCE_MEM,
41};
42
43static struct platform_device ixdp425_flash = {
44 .name = "IXP4XX-Flash",
45 .id = 0,
46 .dev = {
47 .platform_data = &ixdp425_flash_data,
48 },
49 .num_resources = 1,
50 .resource = &ixdp425_flash_resource,
51};
52
53#if defined(CONFIG_MTD_NAND_PLATFORM) || \
54 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
55
56#ifdef CONFIG_MTD_PARTITIONS
57const char *part_probes[] = { "cmdlinepart", NULL };
58
59static struct mtd_partition ixdp425_partitions[] = {
60 {
61 .name = "ixp400 NAND FS 0",
62 .offset = 0,
63 .size = SZ_8M
64 }, {
65 .name = "ixp400 NAND FS 1",
66 .offset = MTDPART_OFS_APPEND,
67 .size = MTDPART_SIZ_FULL
68 },
69};
70#endif
71
72static void
73ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
74{
75 struct nand_chip *this = mtd->priv;
76 int offset = (int)this->priv;
77
78 if (ctrl & NAND_CTRL_CHANGE) {
79 if (ctrl & NAND_NCE) {
80 gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
81 udelay(5);
82 } else
83 gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);
84
85 offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
86 offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
87 this->priv = (void *)offset;
88 }
89
90 if (cmd != NAND_CMD_NONE)
91 writeb(cmd, this->IO_ADDR_W + offset);
92}
93
94static struct platform_nand_data ixdp425_flash_nand_data = {
95 .chip = {
96 .chip_delay = 30,
97 .options = NAND_NO_AUTOINCR,
98#ifdef CONFIG_MTD_PARTITIONS
99 .part_probe_types = part_probes,
100 .partitions = ixdp425_partitions,
101 .nr_partitions = ARRAY_SIZE(ixdp425_partitions),
102#endif
103 },
104 .ctrl = {
105 .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
106 }
107};
108
109static struct resource ixdp425_flash_nand_resource = {
110 .flags = IORESOURCE_MEM,
111};
112
113static struct platform_device ixdp425_flash_nand = {
114 .name = "gen_nand",
115 .id = -1,
116 .dev = {
117 .platform_data = &ixdp425_flash_nand_data,
118 },
119 .num_resources = 1,
120 .resource = &ixdp425_flash_nand_resource,
121};
122#endif
123
124static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
125 .sda_pin = IXDP425_SDA_PIN,
126 .scl_pin = IXDP425_SCL_PIN,
127};
128
129static struct platform_device ixdp425_i2c_gpio = {
130 .name = "i2c-gpio",
131 .id = 0,
132 .dev = {
133 .platform_data = &ixdp425_i2c_gpio_data,
134 },
135};
136
137static struct resource ixdp425_uart_resources[] = {
138 {
139 .start = IXP4XX_UART1_BASE_PHYS,
140 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
141 .flags = IORESOURCE_MEM
142 },
143 {
144 .start = IXP4XX_UART2_BASE_PHYS,
145 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
146 .flags = IORESOURCE_MEM
147 }
148};
149
150static struct plat_serial8250_port ixdp425_uart_data[] = {
151 {
152 .mapbase = IXP4XX_UART1_BASE_PHYS,
153 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
154 .irq = IRQ_IXP4XX_UART1,
155 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
156 .iotype = UPIO_MEM,
157 .regshift = 2,
158 .uartclk = IXP4XX_UART_XTAL,
159 },
160 {
161 .mapbase = IXP4XX_UART2_BASE_PHYS,
162 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
163 .irq = IRQ_IXP4XX_UART2,
164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
165 .iotype = UPIO_MEM,
166 .regshift = 2,
167 .uartclk = IXP4XX_UART_XTAL,
168 },
169 { },
170};
171
172static struct platform_device ixdp425_uart = {
173 .name = "serial8250",
174 .id = PLAT8250_DEV_PLATFORM,
175 .dev.platform_data = ixdp425_uart_data,
176 .num_resources = 2,
177 .resource = ixdp425_uart_resources
178};
179
180
181static struct eth_plat_info ixdp425_plat_eth[] = {
182 {
183 .phy = 0,
184 .rxq = 3,
185 .txreadyq = 20,
186 }, {
187 .phy = 1,
188 .rxq = 4,
189 .txreadyq = 21,
190 }
191};
192
193static struct platform_device ixdp425_eth[] = {
194 {
195 .name = "ixp4xx_eth",
196 .id = IXP4XX_ETH_NPEB,
197 .dev.platform_data = ixdp425_plat_eth,
198 }, {
199 .name = "ixp4xx_eth",
200 .id = IXP4XX_ETH_NPEC,
201 .dev.platform_data = ixdp425_plat_eth + 1,
202 }
203};
204
205static struct platform_device *ixdp425_devices[] __initdata = {
206 &ixdp425_i2c_gpio,
207 &ixdp425_flash,
208#if defined(CONFIG_MTD_NAND_PLATFORM) || \
209 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
210 &ixdp425_flash_nand,
211#endif
212 &ixdp425_uart,
213 &ixdp425_eth[0],
214 &ixdp425_eth[1],
215};
216
217static void __init ixdp425_init(void)
218{
219 ixp4xx_sys_init();
220
221 ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
222 ixdp425_flash_resource.end =
223 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
224
225#if defined(CONFIG_MTD_NAND_PLATFORM) || \
226 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
227 ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
228 ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
229
230 gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
231
232
233 *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
234 IXP4XX_EXP_BUS_STROBE_T(1) |
235 IXP4XX_EXP_BUS_CYCLES(0) |
236 IXP4XX_EXP_BUS_SIZE(0) |
237 IXP4XX_EXP_BUS_WR_EN |
238 IXP4XX_EXP_BUS_BYTE_EN;
239#endif
240
241 if (cpu_is_ixp43x()) {
242 ixdp425_uart.num_resources = 1;
243 ixdp425_uart_data[1].flags = 0;
244 }
245
246 platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
247}
248
249#ifdef CONFIG_ARCH_IXDP425
250MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
251
252 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
253 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
254 .map_io = ixp4xx_map_io,
255 .init_irq = ixp4xx_init_irq,
256 .timer = &ixp4xx_timer,
257 .boot_params = 0x0100,
258 .init_machine = ixdp425_init,
259MACHINE_END
260#endif
261
262#ifdef CONFIG_MACH_IXDP465
263MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
264
265 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
266 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
267 .map_io = ixp4xx_map_io,
268 .init_irq = ixp4xx_init_irq,
269 .timer = &ixp4xx_timer,
270 .boot_params = 0x0100,
271 .init_machine = ixdp425_init,
272MACHINE_END
273#endif
274
275#ifdef CONFIG_ARCH_PRPMC1100
276MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
277
278 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
279 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
280 .map_io = ixp4xx_map_io,
281 .init_irq = ixp4xx_init_irq,
282 .timer = &ixp4xx_timer,
283 .boot_params = 0x0100,
284 .init_machine = ixdp425_init,
285MACHINE_END
286#endif
287
288#ifdef CONFIG_MACH_KIXRP435
289MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
290
291 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
292 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
293 .map_io = ixp4xx_map_io,
294 .init_irq = ixp4xx_init_irq,
295 .timer = &ixp4xx_timer,
296 .boot_params = 0x0100,
297 .init_machine = ixdp425_init,
298MACHINE_END
299#endif
300
