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17#include <linux/delay.h>
18#include <linux/dma-mapping.h>
19#include <linux/firmware.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <mach/npe.h>
25
26#define DEBUG_MSG 0
27#define DEBUG_FW 0
28
29#define NPE_COUNT 3
30#define MAX_RETRIES 1000
31#define NPE_42X_DATA_SIZE 0x800
32#define NPE_46X_DATA_SIZE 0x1000
33#define NPE_A_42X_INSTR_SIZE 0x1000
34#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
35#define NPE_46X_INSTR_SIZE 0x1000
36#define REGS_SIZE 0x1000
37
38#define NPE_PHYS_REG 32
39
40#define FW_MAGIC 0xFEEDF00D
41#define FW_BLOCK_TYPE_INSTR 0x0
42#define FW_BLOCK_TYPE_DATA 0x1
43#define FW_BLOCK_TYPE_EOF 0xF
44
45
46#define CMD_NPE_STEP 0x01
47#define CMD_NPE_START 0x02
48#define CMD_NPE_STOP 0x03
49#define CMD_NPE_CLR_PIPE 0x04
50#define CMD_CLR_PROFILE_CNT 0x0C
51#define CMD_RD_INS_MEM 0x10
52#define CMD_WR_INS_MEM 0x11
53#define CMD_RD_DATA_MEM 0x12
54#define CMD_WR_DATA_MEM 0x13
55#define CMD_RD_ECS_REG 0x14
56#define CMD_WR_ECS_REG 0x15
57
58#define STAT_RUN 0x80000000
59#define STAT_STOP 0x40000000
60#define STAT_CLEAR 0x20000000
61#define STAT_ECS_K 0x00800000
62
63#define NPE_STEVT 0x1B
64#define NPE_STARTPC 0x1C
65#define NPE_REGMAP 0x1E
66#define NPE_CINDEX 0x1F
67
68#define INSTR_WR_REG_SHORT 0x0000C000
69#define INSTR_WR_REG_BYTE 0x00004000
70#define INSTR_RD_FIFO 0x0F888220
71#define INSTR_RESET_MBOX 0x0FAC8210
72
73#define ECS_BG_CTXT_REG_0 0x00
74#define ECS_BG_CTXT_REG_1 0x01
75#define ECS_BG_CTXT_REG_2 0x02
76#define ECS_PRI_1_CTXT_REG_0 0x04
77#define ECS_PRI_1_CTXT_REG_1 0x05
78#define ECS_PRI_1_CTXT_REG_2 0x06
79#define ECS_PRI_2_CTXT_REG_0 0x08
80#define ECS_PRI_2_CTXT_REG_1 0x09
81#define ECS_PRI_2_CTXT_REG_2 0x0A
82#define ECS_DBG_CTXT_REG_0 0x0C
83#define ECS_DBG_CTXT_REG_1 0x0D
84#define ECS_DBG_CTXT_REG_2 0x0E
85#define ECS_INSTRUCT_REG 0x11
86
87#define ECS_REG_0_ACTIVE 0x80000000
88#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000
89#define ECS_REG_0_LDUR_BITS 8
90#define ECS_REG_0_LDUR_MASK 0x00000700
91#define ECS_REG_1_CCTXT_BITS 16
92#define ECS_REG_1_CCTXT_MASK 0x000F0000
93#define ECS_REG_1_SELCTXT_BITS 0
94#define ECS_REG_1_SELCTXT_MASK 0x0000000F
95#define ECS_DBG_REG_2_IF 0x00100000
96#define ECS_DBG_REG_2_IE 0x00080000
97
98
99#define WFIFO_VALID 0x80000000
100
101
102#define MSGSTAT_OFNE 0x00010000
103#define MSGSTAT_IFNF 0x00020000
104#define MSGSTAT_OFNF 0x00040000
105#define MSGSTAT_IFNE 0x00080000
106#define MSGSTAT_MBINT 0x00100000
107#define MSGSTAT_IFINT 0x00200000
108#define MSGSTAT_OFINT 0x00400000
109#define MSGSTAT_WFINT 0x00800000
110
111
112#define MSGCTL_OUT_FIFO 0x00010000
113#define MSGCTL_IN_FIFO 0x00020000
114#define MSGCTL_OUT_FIFO_WRITE 0x01000000
115#define MSGCTL_IN_FIFO_WRITE 0x02000000
116
117
118#define RESET_MBOX_STAT 0x0000F0F0
119
120const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
121
122#define print_npe(pri, npe, fmt, ...) \
123 printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
124
125#if DEBUG_MSG
126#define debug_msg(npe, fmt, ...) \
127 print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
128#else
129#define debug_msg(npe, fmt, ...)
130#endif
131
132static struct {
133 u32 reg, val;
134} ecs_reset[] = {
135 { ECS_BG_CTXT_REG_0, 0xA0000000 },
136 { ECS_BG_CTXT_REG_1, 0x01000000 },
137 { ECS_BG_CTXT_REG_2, 0x00008000 },
138 { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
139 { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
140 { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
141 { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
142 { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
143 { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
144 { ECS_DBG_CTXT_REG_0, 0x20000000 },
145 { ECS_DBG_CTXT_REG_1, 0x00000000 },
146 { ECS_DBG_CTXT_REG_2, 0x001E0000 },
147 { ECS_INSTRUCT_REG, 0x1003C00F },
148};
149
150static struct npe npe_tab[NPE_COUNT] = {
151 {
152 .id = 0,
153 .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
154 .regs_phys = IXP4XX_NPEA_BASE_PHYS,
155 }, {
156 .id = 1,
157 .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
158 .regs_phys = IXP4XX_NPEB_BASE_PHYS,
159 }, {
160 .id = 2,
161 .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
162 .regs_phys = IXP4XX_NPEC_BASE_PHYS,
163 }
164};
165
166int npe_running(struct npe *npe)
167{
168 return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
169}
170
171static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
172{
173 __raw_writel(data, &npe->regs->exec_data);
174 __raw_writel(addr, &npe->regs->exec_addr);
175 __raw_writel(cmd, &npe->regs->exec_status_cmd);
176}
177
178static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
179{
180 __raw_writel(addr, &npe->regs->exec_addr);
181 __raw_writel(cmd, &npe->regs->exec_status_cmd);
182
183
184
185 __raw_readl(&npe->regs->exec_data);
186 __raw_readl(&npe->regs->exec_data);
187 return __raw_readl(&npe->regs->exec_data);
188}
189
190static void npe_clear_active(struct npe *npe, u32 reg)
191{
192 u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
193 npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
194}
195
196static void npe_start(struct npe *npe)
197{
198
199 npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
200 npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
201 npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
202
203 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
204 __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
205}
206
207static void npe_stop(struct npe *npe)
208{
209 __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
210 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
211}
212
213static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
214 u32 ldur)
215{
216 u32 wc;
217 int i;
218
219
220 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
221 ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
222
223
224
225
226
227
228 npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
229 (ctx << ECS_REG_1_CCTXT_BITS) |
230 (ctx << ECS_REG_1_SELCTXT_BITS));
231
232
233 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
234
235
236 npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
237
238
239
240 wc = __raw_readl(&npe->regs->watch_count);
241
242
243 __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
244
245
246 for (i = 0; i < MAX_RETRIES; i++) {
247 if (wc != __raw_readl(&npe->regs->watch_count))
248 return 0;
249 udelay(1);
250 }
251
252 print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
253 return -ETIMEDOUT;
254}
255
256static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
257 u8 val, u32 ctx)
258{
259
260 u32 instr = INSTR_WR_REG_BYTE |
261 addr << 9 |
262 (val & 0x1F) << 4 |
263 (val & ~0x1F) << (18 - 5);
264 return npe_debug_instr(npe, instr, ctx, 1);
265}
266
267static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
268 u16 val, u32 ctx)
269{
270
271 u32 instr = INSTR_WR_REG_SHORT |
272 addr << 9 |
273 (val & 0x1F) << 4 |
274 (val & ~0x1F) << (18 - 5);
275 return npe_debug_instr(npe, instr, ctx, 1);
276}
277
278static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
279 u32 val, u32 ctx)
280{
281
282 if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
283 return -ETIMEDOUT;
284 return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
285}
286
287static int npe_reset(struct npe *npe)
288{
289 u32 val, ctl, exec_count, ctx_reg2;
290 int i;
291
292 ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
293 0x3F3FFFFF;
294
295
296 __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
297
298
299
300 exec_count = __raw_readl(&npe->regs->exec_count);
301 __raw_writel(0, &npe->regs->exec_count);
302
303
304 ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
305 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
306 ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
307
308
309 while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
310 ;
311 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
312
313 print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
314 __raw_readl(&npe->regs->in_out_fifo));
315
316 while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
317
318
319 if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
320 return -ETIMEDOUT;
321
322
323 __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
324
325 if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
326 return -ETIMEDOUT;
327
328
329 for (val = 0; val < NPE_PHYS_REG; val++) {
330 if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
331 return -ETIMEDOUT;
332
333 if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
334 return -ETIMEDOUT;
335 }
336
337
338
339
340
341 val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
342 val &= ~ECS_REG_0_NEXTPC_MASK;
343 val |= (0 << 16) & ECS_REG_0_NEXTPC_MASK;
344 npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
345
346 for (i = 0; i < 16; i++) {
347 if (i) {
348
349 if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
350 return -ETIMEDOUT;
351 if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
352 return -ETIMEDOUT;
353 }
354
355 if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
356 return -ETIMEDOUT;
357 if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
358 return -ETIMEDOUT;
359 }
360
361
362
363 npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
364
365 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
366
367 __raw_writel(exec_count, &npe->regs->exec_count);
368 npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
369
370
371 for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
372 npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
373 ecs_reset[val].val);
374
375
376 __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
377
378 __raw_writel(0, &npe->regs->exec_count);
379 __raw_writel(0, &npe->regs->action_points[0]);
380 __raw_writel(0, &npe->regs->action_points[1]);
381 __raw_writel(0, &npe->regs->action_points[2]);
382 __raw_writel(0, &npe->regs->action_points[3]);
383 __raw_writel(0, &npe->regs->watch_count);
384
385 val = ixp4xx_read_feature_bits();
386
387 ixp4xx_write_feature_bits(val &
388 ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
389
390 ixp4xx_write_feature_bits(val |
391 (IXP4XX_FEATURE_RESET_NPEA << npe->id));
392 for (i = 0; i < MAX_RETRIES; i++) {
393 if (ixp4xx_read_feature_bits() &
394 (IXP4XX_FEATURE_RESET_NPEA << npe->id))
395 break;
396 udelay(1);
397 }
398 if (i == MAX_RETRIES)
399 return -ETIMEDOUT;
400
401 npe_stop(npe);
402
403
404 __raw_writel(ctl, &npe->regs->messaging_control);
405 return 0;
406}
407
408
409int npe_send_message(struct npe *npe, const void *msg, const char *what)
410{
411 const u32 *send = msg;
412 int cycles = 0;
413
414 debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
415 what, send[0], send[1]);
416
417 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
418 debug_msg(npe, "NPE input FIFO not empty\n");
419 return -EIO;
420 }
421
422 __raw_writel(send[0], &npe->regs->in_out_fifo);
423
424 if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
425 debug_msg(npe, "NPE input FIFO full\n");
426 return -EIO;
427 }
428
429 __raw_writel(send[1], &npe->regs->in_out_fifo);
430
431 while ((cycles < MAX_RETRIES) &&
432 (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
433 udelay(1);
434 cycles++;
435 }
436
437 if (cycles == MAX_RETRIES) {
438 debug_msg(npe, "Timeout sending message\n");
439 return -ETIMEDOUT;
440 }
441
442#if DEBUG_MSG > 1
443 debug_msg(npe, "Sending a message took %i cycles\n", cycles);
444#endif
445 return 0;
446}
447
448int npe_recv_message(struct npe *npe, void *msg, const char *what)
449{
450 u32 *recv = msg;
451 int cycles = 0, cnt = 0;
452
453 debug_msg(npe, "Trying to receive message %s\n", what);
454
455 while (cycles < MAX_RETRIES) {
456 if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
457 recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
458 if (cnt == 2)
459 break;
460 } else {
461 udelay(1);
462 cycles++;
463 }
464 }
465
466 switch(cnt) {
467 case 1:
468 debug_msg(npe, "Received [%08X]\n", recv[0]);
469 break;
470 case 2:
471 debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
472 break;
473 }
474
475 if (cycles == MAX_RETRIES) {
476 debug_msg(npe, "Timeout waiting for message\n");
477 return -ETIMEDOUT;
478 }
479
480#if DEBUG_MSG > 1
481 debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
482#endif
483 return 0;
484}
485
486int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
487{
488 int result;
489 u32 *send = msg, recv[2];
490
491 if ((result = npe_send_message(npe, msg, what)) != 0)
492 return result;
493 if ((result = npe_recv_message(npe, recv, what)) != 0)
494 return result;
495
496 if ((recv[0] != send[0]) || (recv[1] != send[1])) {
497 debug_msg(npe, "Message %s: unexpected message received\n",
498 what);
499 return -EIO;
500 }
501 return 0;
502}
503
504
505int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
506{
507 const struct firmware *fw_entry;
508
509 struct dl_block {
510 u32 type;
511 u32 offset;
512 } *blk;
513
514 struct dl_image {
515 u32 magic;
516 u32 id;
517 u32 size;
518 union {
519 u32 data[0];
520 struct dl_block blocks[0];
521 };
522 } *image;
523
524 struct dl_codeblock {
525 u32 npe_addr;
526 u32 size;
527 u32 data[0];
528 } *cb;
529
530 int i, j, err, data_size, instr_size, blocks, table_end;
531 u32 cmd;
532
533 if ((err = request_firmware(&fw_entry, name, dev)) != 0)
534 return err;
535
536 err = -EINVAL;
537 if (fw_entry->size < sizeof(struct dl_image)) {
538 print_npe(KERN_ERR, npe, "incomplete firmware file\n");
539 goto err;
540 }
541 image = (struct dl_image*)fw_entry->data;
542
543#if DEBUG_FW
544 print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
545 image->magic, image->id, image->size, image->size * 4);
546#endif
547
548 if (image->magic == swab32(FW_MAGIC)) {
549 image->id = swab32(image->id);
550 image->size = swab32(image->size);
551 } else if (image->magic != FW_MAGIC) {
552 print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
553 image->magic);
554 goto err;
555 }
556 if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
557 print_npe(KERN_ERR, npe,
558 "inconsistent size of firmware file\n");
559 goto err;
560 }
561 if (((image->id >> 24) & 0xF ) != npe->id) {
562 print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
563 goto err;
564 }
565 if (image->magic == swab32(FW_MAGIC))
566 for (i = 0; i < image->size; i++)
567 image->data[i] = swab32(image->data[i]);
568
569 if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF )) {
570 print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on "
571 "IXP42x\n");
572 goto err;
573 }
574
575 if (npe_running(npe)) {
576 print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
577 "already running\n");
578 err = -EBUSY;
579 goto err;
580 }
581#if 0
582 npe_stop(npe);
583 npe_reset(npe);
584#endif
585
586 print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
587 "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
588 (image->id >> 8) & 0xFF, image->id & 0xFF);
589
590 if (cpu_is_ixp42x()) {
591 if (!npe->id)
592 instr_size = NPE_A_42X_INSTR_SIZE;
593 else
594 instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
595 data_size = NPE_42X_DATA_SIZE;
596 } else {
597 instr_size = NPE_46X_INSTR_SIZE;
598 data_size = NPE_46X_DATA_SIZE;
599 }
600
601 for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
602 blocks++)
603 if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
604 break;
605 if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
606 print_npe(KERN_INFO, npe, "firmware EOF block marker not "
607 "found\n");
608 goto err;
609 }
610
611#if DEBUG_FW
612 print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
613#endif
614
615 table_end = blocks * sizeof(struct dl_block) / 4 + 1 ;
616 for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
617 if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
618 || blk->offset < table_end) {
619 print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
620 "firmware block #%i\n", blk->offset, i);
621 goto err;
622 }
623
624 cb = (struct dl_codeblock*)&image->data[blk->offset];
625 if (blk->type == FW_BLOCK_TYPE_INSTR) {
626 if (cb->npe_addr + cb->size > instr_size)
627 goto too_big;
628 cmd = CMD_WR_INS_MEM;
629 } else if (blk->type == FW_BLOCK_TYPE_DATA) {
630 if (cb->npe_addr + cb->size > data_size)
631 goto too_big;
632 cmd = CMD_WR_DATA_MEM;
633 } else {
634 print_npe(KERN_INFO, npe, "invalid firmware block #%i "
635 "type 0x%X\n", i, blk->type);
636 goto err;
637 }
638 if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
639 print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
640 "fit in firmware image: type %c, start 0x%X,"
641 " length 0x%X\n", i,
642 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
643 cb->npe_addr, cb->size);
644 goto err;
645 }
646
647 for (j = 0; j < cb->size; j++)
648 npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
649 }
650
651 npe_start(npe);
652 if (!npe_running(npe))
653 print_npe(KERN_ERR, npe, "unable to start\n");
654 release_firmware(fw_entry);
655 return 0;
656
657too_big:
658 print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
659 "memory: type %c, start 0x%X, length 0x%X\n", i,
660 blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
661 cb->npe_addr, cb->size);
662err:
663 release_firmware(fw_entry);
664 return err;
665}
666
667
668struct npe *npe_request(int id)
669{
670 if (id < NPE_COUNT)
671 if (npe_tab[id].valid)
672 if (try_module_get(THIS_MODULE))
673 return &npe_tab[id];
674 return NULL;
675}
676
677void npe_release(struct npe *npe)
678{
679 module_put(THIS_MODULE);
680}
681
682
683static int __init npe_init_module(void)
684{
685
686 int i, found = 0;
687
688 for (i = 0; i < NPE_COUNT; i++) {
689 struct npe *npe = &npe_tab[i];
690 if (!(ixp4xx_read_feature_bits() &
691 (IXP4XX_FEATURE_RESET_NPEA << i)))
692 continue;
693 if (!(npe->mem_res = request_mem_region(npe->regs_phys,
694 REGS_SIZE,
695 npe_name(npe)))) {
696 print_npe(KERN_ERR, npe,
697 "failed to request memory region\n");
698 continue;
699 }
700
701 if (npe_reset(npe))
702 continue;
703 npe->valid = 1;
704 found++;
705 }
706
707 if (!found)
708 return -ENODEV;
709 return 0;
710}
711
712static void __exit npe_cleanup_module(void)
713{
714 int i;
715
716 for (i = 0; i < NPE_COUNT; i++)
717 if (npe_tab[i].mem_res) {
718 npe_reset(&npe_tab[i]);
719 release_resource(npe_tab[i].mem_res);
720 }
721}
722
723module_init(npe_init_module);
724module_exit(npe_cleanup_module);
725
726MODULE_AUTHOR("Krzysztof Halasa");
727MODULE_LICENSE("GPL v2");
728
729EXPORT_SYMBOL(npe_names);
730EXPORT_SYMBOL(npe_running);
731EXPORT_SYMBOL(npe_request);
732EXPORT_SYMBOL(npe_release);
733EXPORT_SYMBOL(npe_load_firmware);
734EXPORT_SYMBOL(npe_send_message);
735EXPORT_SYMBOL(npe_recv_message);
736EXPORT_SYMBOL(npe_send_recv_message);
737