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19#include <linux/types.h>
20#include <linux/init.h>
21
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/mtd/plat-ram.h>
25#include <linux/memory.h>
26#include <linux/gpio.h>
27#include <linux/smc911x.h>
28#include <linux/interrupt.h>
29#include <linux/i2c.h>
30#include <linux/i2c/at24.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/mach/map.h>
36
37#include <mach/hardware.h>
38#include <mach/common.h>
39#include <mach/imx-uart.h>
40#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
41#include <mach/i2c.h>
42#endif
43#include <mach/iomux-mx35.h>
44#include <mach/ipu.h>
45#include <mach/mx3fb.h>
46
47#include "devices.h"
48
49static const struct fb_videomode fb_modedb[] = {
50 {
51
52 .name = "Sharp-LQ035Q7",
53 .refresh = 60,
54 .xres = 240,
55 .yres = 320,
56 .pixclock = 185925,
57 .left_margin = 9,
58 .right_margin = 16,
59 .upper_margin = 7,
60 .lower_margin = 9,
61 .hsync_len = 1,
62 .vsync_len = 1,
63 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
64 .vmode = FB_VMODE_NONINTERLACED,
65 .flag = 0,
66 }, {
67
68 .name = "TX090",
69 .refresh = 60,
70 .xres = 240,
71 .yres = 320,
72 .pixclock = 38255,
73 .left_margin = 144,
74 .right_margin = 0,
75 .upper_margin = 7,
76 .lower_margin = 40,
77 .hsync_len = 96,
78 .vsync_len = 1,
79 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
80 .vmode = FB_VMODE_NONINTERLACED,
81 .flag = 0,
82 },
83};
84
85static struct ipu_platform_data mx3_ipu_data = {
86 .irq_base = MXC_IPU_IRQ_START,
87};
88
89static struct mx3fb_platform_data mx3fb_pdata = {
90 .dma_dev = &mx3_ipu.dev,
91 .name = "Sharp-LQ035Q7",
92 .mode = fb_modedb,
93 .num_modes = ARRAY_SIZE(fb_modedb),
94};
95
96static struct physmap_flash_data pcm043_flash_data = {
97 .width = 2,
98};
99
100static struct resource pcm043_flash_resource = {
101 .start = 0xa0000000,
102 .end = 0xa1ffffff,
103 .flags = IORESOURCE_MEM,
104};
105
106static struct platform_device pcm043_flash = {
107 .name = "physmap-flash",
108 .id = 0,
109 .dev = {
110 .platform_data = &pcm043_flash_data,
111 },
112 .resource = &pcm043_flash_resource,
113 .num_resources = 1,
114};
115
116static struct imxuart_platform_data uart_pdata = {
117 .flags = IMXUART_HAVE_RTSCTS,
118};
119
120#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
121static struct imxi2c_platform_data pcm043_i2c_1_data = {
122 .bitrate = 50000,
123};
124
125static struct at24_platform_data board_eeprom = {
126 .byte_len = 4096,
127 .page_size = 32,
128 .flags = AT24_FLAG_ADDR16,
129};
130
131static struct i2c_board_info pcm043_i2c_devices[] = {
132 {
133 I2C_BOARD_INFO("at24", 0x52),
134 .platform_data = &board_eeprom,
135 }, {
136 I2C_BOARD_INFO("pcf8563", 0x51),
137 }
138};
139#endif
140
141static struct platform_device *devices[] __initdata = {
142 &pcm043_flash,
143 &mxc_fec_device,
144};
145
146static struct pad_desc pcm043_pads[] = {
147
148 MX35_PAD_CTS1__UART1_CTS,
149 MX35_PAD_RTS1__UART1_RTS,
150 MX35_PAD_TXD1__UART1_TXD_MUX,
151 MX35_PAD_RXD1__UART1_RXD_MUX,
152
153 MX35_PAD_CTS2__UART2_CTS,
154 MX35_PAD_RTS2__UART2_RTS,
155 MX35_PAD_TXD2__UART2_TXD_MUX,
156 MX35_PAD_RXD2__UART2_RXD_MUX,
157
158 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
159 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
160 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
161 MX35_PAD_FEC_COL__FEC_COL,
162 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
163 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
164 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
165 MX35_PAD_FEC_MDC__FEC_MDC,
166 MX35_PAD_FEC_MDIO__FEC_MDIO,
167 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
168 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
169 MX35_PAD_FEC_CRS__FEC_CRS,
170 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
171 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
172 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
173 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
174 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
175 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
176
177 MX35_PAD_I2C1_CLK__I2C1_SCL,
178 MX35_PAD_I2C1_DAT__I2C1_SDA,
179
180 MX35_PAD_LD0__IPU_DISPB_DAT_0,
181 MX35_PAD_LD1__IPU_DISPB_DAT_1,
182 MX35_PAD_LD2__IPU_DISPB_DAT_2,
183 MX35_PAD_LD3__IPU_DISPB_DAT_3,
184 MX35_PAD_LD4__IPU_DISPB_DAT_4,
185 MX35_PAD_LD5__IPU_DISPB_DAT_5,
186 MX35_PAD_LD6__IPU_DISPB_DAT_6,
187 MX35_PAD_LD7__IPU_DISPB_DAT_7,
188 MX35_PAD_LD8__IPU_DISPB_DAT_8,
189 MX35_PAD_LD9__IPU_DISPB_DAT_9,
190 MX35_PAD_LD10__IPU_DISPB_DAT_10,
191 MX35_PAD_LD11__IPU_DISPB_DAT_11,
192 MX35_PAD_LD12__IPU_DISPB_DAT_12,
193 MX35_PAD_LD13__IPU_DISPB_DAT_13,
194 MX35_PAD_LD14__IPU_DISPB_DAT_14,
195 MX35_PAD_LD15__IPU_DISPB_DAT_15,
196 MX35_PAD_LD16__IPU_DISPB_DAT_16,
197 MX35_PAD_LD17__IPU_DISPB_DAT_17,
198 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
199 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
200 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
201 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
202 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
203 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
204 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
205
206 MX35_PAD_ATA_CS0__GPIO2_6,
207};
208
209
210
211
212static void __init mxc_board_init(void)
213{
214 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
215
216 platform_add_devices(devices, ARRAY_SIZE(devices));
217
218 mxc_register_device(&mxc_uart_device0, &uart_pdata);
219
220 mxc_register_device(&mxc_uart_device1, &uart_pdata);
221
222#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
223 i2c_register_board_info(0, pcm043_i2c_devices,
224 ARRAY_SIZE(pcm043_i2c_devices));
225
226 mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
227#endif
228
229 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
230 mxc_register_device(&mx3_fb, &mx3fb_pdata);
231}
232
233static void __init pcm043_timer_init(void)
234{
235 mx35_clocks_init();
236}
237
238struct sys_timer pcm043_timer = {
239 .init = pcm043_timer_init,
240};
241
242MACHINE_START(PCM043, "Phytec Phycore pcm043")
243
244 .phys_io = AIPS1_BASE_ADDR,
245 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
246 .boot_params = PHYS_OFFSET + 0x100,
247 .map_io = mx35_map_io,
248 .init_irq = mx35_init_irq,
249 .init_machine = mxc_board_init,
250 .timer = &pcm043_timer,
251MACHINE_END
252
253
