1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/memory.h>
23#include <linux/platform_device.h>
24#include <linux/mtd/physmap.h>
25#include <linux/mtd/nand.h>
26#include <linux/gpio.h>
27
28#include <mach/hardware.h>
29#include <mach/irqs.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/mach/map.h>
34#include <mach/common.h>
35#include <asm/page.h>
36#include <asm/setup.h>
37#include <mach/board-qong.h>
38#include <mach/imx-uart.h>
39#include <mach/iomux-mx3.h>
40#include "devices.h"
41
42
43#define QONG_FPGA_VERSION(major, minor, rev) \
44 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
45
46#define QONG_FPGA_BASEADDR CS1_BASE_ADDR
47#define QONG_FPGA_PERIPH_SIZE (1 << 24)
48
49#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
50#define QONG_FPGA_CTRL_SIZE 0x10
51
52#define QONG_FPGA_CTRL_VERSION 0x00
53
54#define QONG_DNET_ID 1
55#define QONG_DNET_BASEADDR \
56 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
57#define QONG_DNET_SIZE 0x00001000
58
59#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
60
61
62
63
64
65static struct imxuart_platform_data uart_pdata = {
66 .flags = IMXUART_HAVE_RTSCTS,
67};
68
69static int uart_pins[] = {
70 MX31_PIN_CTS1__CTS1,
71 MX31_PIN_RTS1__RTS1,
72 MX31_PIN_TXD1__TXD1,
73 MX31_PIN_RXD1__RXD1
74};
75
76static inline void mxc_init_imx_uart(void)
77{
78 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
79 "uart-0");
80 mxc_register_device(&mxc_uart_device0, &uart_pdata);
81}
82
83static struct resource dnet_resources[] = {
84 {
85 .name = "dnet-memory",
86 .start = QONG_DNET_BASEADDR,
87 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
88 .flags = IORESOURCE_MEM,
89 }, {
90 .start = QONG_FPGA_IRQ,
91 .end = QONG_FPGA_IRQ,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device dnet_device = {
97 .name = "dnet",
98 .id = -1,
99 .num_resources = ARRAY_SIZE(dnet_resources),
100 .resource = dnet_resources,
101};
102
103static int __init qong_init_dnet(void)
104{
105 int ret;
106
107 ret = platform_device_register(&dnet_device);
108 return ret;
109}
110
111
112
113static struct physmap_flash_data qong_flash_data = {
114 .width = 2,
115};
116
117static struct resource qong_flash_resource = {
118 .start = CS0_BASE_ADDR,
119 .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
120 .flags = IORESOURCE_MEM,
121};
122
123static struct platform_device qong_nor_mtd_device = {
124 .name = "physmap-flash",
125 .id = 0,
126 .dev = {
127 .platform_data = &qong_flash_data,
128 },
129 .resource = &qong_flash_resource,
130 .num_resources = 1,
131};
132
133static void qong_init_nor_mtd(void)
134{
135 (void)platform_device_register(&qong_nor_mtd_device);
136}
137
138
139
140
141static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
142{
143 struct nand_chip *nand_chip = mtd->priv;
144
145 if (cmd == NAND_CMD_NONE)
146 return;
147
148 if (ctrl & NAND_CLE)
149 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
150 else
151 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
152}
153
154
155
156
157static int qong_nand_device_ready(struct mtd_info *mtd)
158{
159 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
160}
161
162static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
163{
164 if (chip >= 0)
165 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
166 else
167 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
168}
169
170static struct platform_nand_data qong_nand_data = {
171 .chip = {
172 .chip_delay = 20,
173 .options = 0,
174 },
175 .ctrl = {
176 .cmd_ctrl = qong_nand_cmd_ctrl,
177 .dev_ready = qong_nand_device_ready,
178 .select_chip = qong_nand_select_chip,
179 }
180};
181
182static struct resource qong_nand_resource = {
183 .start = CS3_BASE_ADDR,
184 .end = CS3_BASE_ADDR + SZ_32M - 1,
185 .flags = IORESOURCE_MEM,
186};
187
188static struct platform_device qong_nand_device = {
189 .name = "gen_nand",
190 .id = -1,
191 .dev = {
192 .platform_data = &qong_nand_data,
193 },
194 .num_resources = 1,
195 .resource = &qong_nand_resource,
196};
197
198static void __init qong_init_nand_mtd(void)
199{
200
201 __raw_writel(0x00004f00, CSCR_U(3));
202 __raw_writel(0x20013b31, CSCR_L(3));
203 __raw_writel(0x00020800, CSCR_A(3));
204 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
205
206
207 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
208 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
209 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
210
211
212 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
213 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
214 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
215
216
217 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
218 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
219 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
220
221 platform_device_register(&qong_nand_device);
222}
223
224static void __init qong_init_fpga(void)
225{
226 void __iomem *regs;
227 u32 fpga_ver;
228
229 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
230 if (!regs) {
231 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
232 __func__);
233 return;
234 }
235
236 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
237 iounmap(regs);
238 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
239 (fpga_ver & 0xF000) >> 12,
240 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
241 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
242 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
243 "devices won't be registered!\n");
244 return;
245 }
246
247
248 qong_init_nand_mtd();
249 qong_init_dnet();
250}
251
252
253
254
255static void __init mxc_board_init(void)
256{
257 mxc_init_imx_uart();
258 qong_init_nor_mtd();
259 qong_init_fpga();
260}
261
262static void __init qong_timer_init(void)
263{
264 mx31_clocks_init(26000000);
265}
266
267static struct sys_timer qong_timer = {
268 .init = qong_timer_init,
269};
270
271
272
273
274
275
276MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
277
278 .phys_io = AIPS1_BASE_ADDR,
279 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
280 .boot_params = PHYS_OFFSET + 0x100,
281 .map_io = mx31_map_io,
282 .init_irq = mx31_init_irq,
283 .init_machine = mxc_board_init,
284 .timer = &qong_timer,
285MACHINE_END
286
