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14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/input.h>
22
23#include <mach/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/flash.h>
27#include <asm/mach/map.h>
28
29#include <mach/tc.h>
30#include <mach/gpio.h>
31#include <mach/mux.h>
32#include <mach/fpga.h>
33#include <mach/nand.h>
34#include <mach/keypad.h>
35#include <mach/common.h>
36#include <mach/board.h>
37
38
39
40#define fsample_cpld_read(reg) __raw_readb(reg)
41#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
42
43#define FSAMPLE_CPLD_BASE 0xE8100000
44#define FSAMPLE_CPLD_SIZE SZ_4K
45#define FSAMPLE_CPLD_START 0x05080000
46
47#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
48#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
49#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
50#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
51#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
52#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
53
54#define FSAMPLE_CPLD_BIT_BT_RESET 0
55#define FSAMPLE_CPLD_BIT_LCD_RESET 1
56#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
57#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
58#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
59#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
60#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
61#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
62#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
63#define FSAMPLE_CPLD_BIT_OTG_RESET 9
64
65#define fsample_cpld_set(bit) \
66 fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
67
68#define fsample_cpld_clear(bit) \
69 fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
70
71static int fsample_keymap[] = {
72 KEY(0,0,KEY_UP),
73 KEY(0,1,KEY_RIGHT),
74 KEY(0,2,KEY_LEFT),
75 KEY(0,3,KEY_DOWN),
76 KEY(0,4,KEY_ENTER),
77 KEY(1,0,KEY_F10),
78 KEY(1,1,KEY_SEND),
79 KEY(1,2,KEY_END),
80 KEY(1,3,KEY_VOLUMEDOWN),
81 KEY(1,4,KEY_VOLUMEUP),
82 KEY(1,5,KEY_RECORD),
83 KEY(2,0,KEY_F9),
84 KEY(2,1,KEY_3),
85 KEY(2,2,KEY_6),
86 KEY(2,3,KEY_9),
87 KEY(2,4,KEY_KPDOT),
88 KEY(3,0,KEY_BACK),
89 KEY(3,1,KEY_2),
90 KEY(3,2,KEY_5),
91 KEY(3,3,KEY_8),
92 KEY(3,4,KEY_0),
93 KEY(3,5,KEY_KPSLASH),
94 KEY(4,0,KEY_HOME),
95 KEY(4,1,KEY_1),
96 KEY(4,2,KEY_4),
97 KEY(4,3,KEY_7),
98 KEY(4,4,KEY_KPASTERISK),
99 KEY(4,5,KEY_POWER),
100 0
101};
102
103static struct resource smc91x_resources[] = {
104 [0] = {
105 .start = H2P2_DBG_FPGA_ETHR_START,
106 .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = INT_730_MPU_EXT_NIRQ,
111 .end = 0,
112 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
113 },
114};
115
116static struct mtd_partition nor_partitions[] = {
117
118 {
119 .name = "bootloader",
120 .offset = 0,
121 .size = SZ_128K,
122 .mask_flags = MTD_WRITEABLE,
123 },
124
125 {
126 .name = "params",
127 .offset = MTDPART_OFS_APPEND,
128 .size = SZ_128K,
129 .mask_flags = 0,
130 },
131
132 {
133 .name = "kernel",
134 .offset = MTDPART_OFS_APPEND,
135 .size = SZ_2M,
136 .mask_flags = 0
137 },
138
139 {
140 .name = "rootfs",
141 .offset = MTDPART_OFS_APPEND,
142 .size = MTDPART_SIZ_FULL,
143 .mask_flags = 0
144 },
145};
146
147static struct flash_platform_data nor_data = {
148 .map_name = "cfi_probe",
149 .width = 2,
150 .parts = nor_partitions,
151 .nr_parts = ARRAY_SIZE(nor_partitions),
152};
153
154static struct resource nor_resource = {
155 .start = OMAP_CS0_PHYS,
156 .end = OMAP_CS0_PHYS + SZ_32M - 1,
157 .flags = IORESOURCE_MEM,
158};
159
160static struct platform_device nor_device = {
161 .name = "omapflash",
162 .id = 0,
163 .dev = {
164 .platform_data = &nor_data,
165 },
166 .num_resources = 1,
167 .resource = &nor_resource,
168};
169
170static struct omap_nand_platform_data nand_data = {
171 .options = NAND_SAMSUNG_LP_OPTIONS,
172};
173
174static struct resource nand_resource = {
175 .start = OMAP_CS3_PHYS,
176 .end = OMAP_CS3_PHYS + SZ_4K - 1,
177 .flags = IORESOURCE_MEM,
178};
179
180static struct platform_device nand_device = {
181 .name = "omapnand",
182 .id = 0,
183 .dev = {
184 .platform_data = &nand_data,
185 },
186 .num_resources = 1,
187 .resource = &nand_resource,
188};
189
190static struct platform_device smc91x_device = {
191 .name = "smc91x",
192 .id = 0,
193 .num_resources = ARRAY_SIZE(smc91x_resources),
194 .resource = smc91x_resources,
195};
196
197static struct resource kp_resources[] = {
198 [0] = {
199 .start = INT_730_MPUIO_KEYPAD,
200 .end = INT_730_MPUIO_KEYPAD,
201 .flags = IORESOURCE_IRQ,
202 },
203};
204
205static struct omap_kp_platform_data kp_data = {
206 .rows = 8,
207 .cols = 8,
208 .keymap = fsample_keymap,
209 .keymapsize = ARRAY_SIZE(fsample_keymap),
210 .delay = 4,
211};
212
213static struct platform_device kp_device = {
214 .name = "omap-keypad",
215 .id = -1,
216 .dev = {
217 .platform_data = &kp_data,
218 },
219 .num_resources = ARRAY_SIZE(kp_resources),
220 .resource = kp_resources,
221};
222
223static struct platform_device lcd_device = {
224 .name = "lcd_p2",
225 .id = -1,
226};
227
228static struct platform_device *devices[] __initdata = {
229 &nor_device,
230 &nand_device,
231 &smc91x_device,
232 &kp_device,
233 &lcd_device,
234};
235
236#define P2_NAND_RB_GPIO_PIN 62
237
238static int nand_dev_ready(struct omap_nand_platform_data *data)
239{
240 return gpio_get_value(P2_NAND_RB_GPIO_PIN);
241}
242
243static struct omap_lcd_config fsample_lcd_config __initdata = {
244 .ctrl_name = "internal",
245};
246
247static struct omap_board_config_kernel fsample_config[] = {
248 { OMAP_TAG_LCD, &fsample_lcd_config },
249};
250
251static void __init omap_fsample_init(void)
252{
253 if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
254 BUG();
255 nand_data.dev_ready = nand_dev_ready;
256
257 omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
258 omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
259
260 platform_add_devices(devices, ARRAY_SIZE(devices));
261
262 omap_board_config = fsample_config;
263 omap_board_config_size = ARRAY_SIZE(fsample_config);
264 omap_serial_init();
265 omap_register_i2c_bus(1, 100, NULL, 0);
266}
267
268static void __init fsample_init_smc91x(void)
269{
270 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
271 mdelay(50);
272 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
273 H2P2_DBG_FPGA_LAN_RESET);
274 mdelay(50);
275}
276
277static void __init omap_fsample_init_irq(void)
278{
279 omap1_init_common_hw();
280 omap_init_irq();
281 omap_gpio_init();
282 fsample_init_smc91x();
283}
284
285
286static struct map_desc omap_fsample_io_desc[] __initdata = {
287 {
288 .virtual = H2P2_DBG_FPGA_BASE,
289 .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
290 .length = H2P2_DBG_FPGA_SIZE,
291 .type = MT_DEVICE
292 },
293 {
294 .virtual = FSAMPLE_CPLD_BASE,
295 .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
296 .length = FSAMPLE_CPLD_SIZE,
297 .type = MT_DEVICE
298 }
299};
300
301static void __init omap_fsample_map_io(void)
302{
303 omap1_map_common_io();
304 iotable_init(omap_fsample_io_desc,
305 ARRAY_SIZE(omap_fsample_io_desc));
306
307
308
309
310
311
312 omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
313
314
315
316
317
318
319
320
321
322
323 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
324 omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
325
326
327
328
329
330 omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
331 omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
332
333
334
335
336
337 omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
338}
339
340MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
341
342 .phys_io = 0xfff00000,
343 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
344 .boot_params = 0x10000100,
345 .map_io = omap_fsample_map_io,
346 .init_irq = omap_fsample_init_irq,
347 .init_machine = omap_fsample_init,
348 .timer = &omap_timer,
349MACHINE_END
350
