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20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/serial_8250.h>
23#include <linux/serial_reg.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#include <mach/common.h>
28#include <mach/board.h>
29#include <mach/clock.h>
30#include <mach/control.h>
31
32#include "prm.h"
33#include "pm.h"
34#include "prm-regbits-34xx.h"
35
36#define UART_OMAP_WER 0x17
37
38#define DEFAULT_TIMEOUT (5 * HZ)
39
40struct omap_uart_state {
41 int num;
42 int can_sleep;
43 struct timer_list timer;
44 u32 timeout;
45
46 void __iomem *wk_st;
47 void __iomem *wk_en;
48 u32 wk_mask;
49 u32 padconf;
50
51 struct clk *ick;
52 struct clk *fck;
53 int clocked;
54
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
58
59#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
60 int context_valid;
61
62
63 u16 dll;
64 u16 dlh;
65 u16 ier;
66 u16 sysc;
67 u16 scr;
68 u16 wer;
69#endif
70};
71
72static LIST_HEAD(uart_list);
73
74static struct plat_serial8250_port serial_platform_data0[] = {
75 {
76 .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE,
78 .irq = 72,
79 .flags = UPF_BOOT_AUTOCONF,
80 .iotype = UPIO_MEM,
81 .regshift = 2,
82 .uartclk = OMAP24XX_BASE_BAUD * 16,
83 }, {
84 .flags = 0
85 }
86};
87
88static struct plat_serial8250_port serial_platform_data1[] = {
89 {
90 .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
91 .mapbase = OMAP_UART2_BASE,
92 .irq = 73,
93 .flags = UPF_BOOT_AUTOCONF,
94 .iotype = UPIO_MEM,
95 .regshift = 2,
96 .uartclk = OMAP24XX_BASE_BAUD * 16,
97 }, {
98 .flags = 0
99 }
100};
101
102static struct plat_serial8250_port serial_platform_data2[] = {
103 {
104 .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
105 .mapbase = OMAP_UART3_BASE,
106 .irq = 74,
107 .flags = UPF_BOOT_AUTOCONF,
108 .iotype = UPIO_MEM,
109 .regshift = 2,
110 .uartclk = OMAP24XX_BASE_BAUD * 16,
111 }, {
112 .flags = 0
113 }
114};
115
116#ifdef CONFIG_ARCH_OMAP4
117static struct plat_serial8250_port serial_platform_data3[] = {
118 {
119 .membase = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
120 .mapbase = OMAP_UART4_BASE,
121 .irq = 70,
122 .flags = UPF_BOOT_AUTOCONF,
123 .iotype = UPIO_MEM,
124 .regshift = 2,
125 .uartclk = OMAP24XX_BASE_BAUD * 16,
126 }, {
127 .flags = 0
128 }
129};
130#endif
131static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
132 int offset)
133{
134 offset <<= up->regshift;
135 return (unsigned int)__raw_readb(up->membase + offset);
136}
137
138static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
139 int value)
140{
141 offset <<= p->regshift;
142 __raw_writeb(value, p->membase + offset);
143}
144
145
146
147
148
149
150static inline void __init omap_uart_reset(struct omap_uart_state *uart)
151{
152 struct plat_serial8250_port *p = uart->p;
153
154 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
155 serial_write_reg(p, UART_OMAP_SCR, 0x08);
156 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
157 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
158}
159
160#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
161
162static int enable_off_mode;
163
164static void omap_uart_save_context(struct omap_uart_state *uart)
165{
166 u16 lcr = 0;
167 struct plat_serial8250_port *p = uart->p;
168
169 if (!enable_off_mode)
170 return;
171
172 lcr = serial_read_reg(p, UART_LCR);
173 serial_write_reg(p, UART_LCR, 0xBF);
174 uart->dll = serial_read_reg(p, UART_DLL);
175 uart->dlh = serial_read_reg(p, UART_DLM);
176 serial_write_reg(p, UART_LCR, lcr);
177 uart->ier = serial_read_reg(p, UART_IER);
178 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
179 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
180 uart->wer = serial_read_reg(p, UART_OMAP_WER);
181
182 uart->context_valid = 1;
183}
184
185static void omap_uart_restore_context(struct omap_uart_state *uart)
186{
187 u16 efr = 0;
188 struct plat_serial8250_port *p = uart->p;
189
190 if (!enable_off_mode)
191 return;
192
193 if (!uart->context_valid)
194 return;
195
196 uart->context_valid = 0;
197
198 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
199 serial_write_reg(p, UART_LCR, 0xBF);
200 efr = serial_read_reg(p, UART_EFR);
201 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
202 serial_write_reg(p, UART_LCR, 0x0);
203 serial_write_reg(p, UART_IER, 0x0);
204 serial_write_reg(p, UART_LCR, 0xBF);
205 serial_write_reg(p, UART_DLL, uart->dll);
206 serial_write_reg(p, UART_DLM, uart->dlh);
207 serial_write_reg(p, UART_LCR, 0x0);
208 serial_write_reg(p, UART_IER, uart->ier);
209 serial_write_reg(p, UART_FCR, 0xA1);
210 serial_write_reg(p, UART_LCR, 0xBF);
211 serial_write_reg(p, UART_EFR, efr);
212 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
213 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
214 serial_write_reg(p, UART_OMAP_WER, uart->wer);
215 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
216 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
217}
218#else
219static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
220static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
221#endif
222
223static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
224{
225 if (uart->clocked)
226 return;
227
228 clk_enable(uart->ick);
229 clk_enable(uart->fck);
230 uart->clocked = 1;
231 omap_uart_restore_context(uart);
232}
233
234#ifdef CONFIG_PM
235
236static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
237{
238 if (!uart->clocked)
239 return;
240
241 omap_uart_save_context(uart);
242 uart->clocked = 0;
243 clk_disable(uart->ick);
244 clk_disable(uart->fck);
245}
246
247static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
248{
249
250 if (uart->wk_en && uart->wk_mask) {
251 u32 v = __raw_readl(uart->wk_en);
252 v |= uart->wk_mask;
253 __raw_writel(v, uart->wk_en);
254 }
255
256
257 if (cpu_is_omap34xx() && uart->padconf) {
258 u16 v = omap_ctrl_readw(uart->padconf);
259 v |= OMAP3_PADCONF_WAKEUPENABLE0;
260 omap_ctrl_writew(v, uart->padconf);
261 }
262}
263
264static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
265{
266
267 if (uart->wk_en && uart->wk_mask) {
268 u32 v = __raw_readl(uart->wk_en);
269 v &= ~uart->wk_mask;
270 __raw_writel(v, uart->wk_en);
271 }
272
273
274 if (cpu_is_omap34xx() && uart->padconf) {
275 u16 v = omap_ctrl_readw(uart->padconf);
276 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
277 omap_ctrl_writew(v, uart->padconf);
278 }
279}
280
281static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
282 int enable)
283{
284 struct plat_serial8250_port *p = uart->p;
285 u16 sysc;
286
287 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
288 if (enable)
289 sysc |= 0x2 << 3;
290 else
291 sysc |= 0x1 << 3;
292
293 serial_write_reg(p, UART_OMAP_SYSC, sysc);
294}
295
296static void omap_uart_block_sleep(struct omap_uart_state *uart)
297{
298 omap_uart_enable_clocks(uart);
299
300 omap_uart_smart_idle_enable(uart, 0);
301 uart->can_sleep = 0;
302 if (uart->timeout)
303 mod_timer(&uart->timer, jiffies + uart->timeout);
304 else
305 del_timer(&uart->timer);
306}
307
308static void omap_uart_allow_sleep(struct omap_uart_state *uart)
309{
310 if (device_may_wakeup(&uart->pdev.dev))
311 omap_uart_enable_wakeup(uart);
312 else
313 omap_uart_disable_wakeup(uart);
314
315 if (!uart->clocked)
316 return;
317
318 omap_uart_smart_idle_enable(uart, 1);
319 uart->can_sleep = 1;
320 del_timer(&uart->timer);
321}
322
323static void omap_uart_idle_timer(unsigned long data)
324{
325 struct omap_uart_state *uart = (struct omap_uart_state *)data;
326
327 omap_uart_allow_sleep(uart);
328}
329
330void omap_uart_prepare_idle(int num)
331{
332 struct omap_uart_state *uart;
333
334 list_for_each_entry(uart, &uart_list, node) {
335 if (num == uart->num && uart->can_sleep) {
336 omap_uart_disable_clocks(uart);
337 return;
338 }
339 }
340}
341
342void omap_uart_resume_idle(int num)
343{
344 struct omap_uart_state *uart;
345
346 list_for_each_entry(uart, &uart_list, node) {
347 if (num == uart->num) {
348 omap_uart_enable_clocks(uart);
349
350
351 if (cpu_is_omap34xx() && uart->padconf) {
352 u16 p = omap_ctrl_readw(uart->padconf);
353
354 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
355 omap_uart_block_sleep(uart);
356 }
357
358
359 if (__raw_readl(uart->wk_st) & uart->wk_mask)
360 omap_uart_block_sleep(uart);
361 return;
362 }
363 }
364}
365
366void omap_uart_prepare_suspend(void)
367{
368 struct omap_uart_state *uart;
369
370 list_for_each_entry(uart, &uart_list, node) {
371 omap_uart_allow_sleep(uart);
372 }
373}
374
375int omap_uart_can_sleep(void)
376{
377 struct omap_uart_state *uart;
378 int can_sleep = 1;
379
380 list_for_each_entry(uart, &uart_list, node) {
381 if (!uart->clocked)
382 continue;
383
384 if (!uart->can_sleep) {
385 can_sleep = 0;
386 continue;
387 }
388
389
390 omap_uart_allow_sleep(uart);
391 }
392
393 return can_sleep;
394}
395
396
397
398
399
400
401
402
403
404
405static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
406{
407 struct omap_uart_state *uart = dev_id;
408
409 omap_uart_block_sleep(uart);
410
411 return IRQ_NONE;
412}
413
414static void omap_uart_idle_init(struct omap_uart_state *uart)
415{
416 struct plat_serial8250_port *p = uart->p;
417 int ret;
418
419 uart->can_sleep = 0;
420 uart->timeout = DEFAULT_TIMEOUT;
421 setup_timer(&uart->timer, omap_uart_idle_timer,
422 (unsigned long) uart);
423 mod_timer(&uart->timer, jiffies + uart->timeout);
424 omap_uart_smart_idle_enable(uart, 0);
425
426 if (cpu_is_omap34xx()) {
427 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
428 u32 wk_mask = 0;
429 u32 padconf = 0;
430
431 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
432 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
433 switch (uart->num) {
434 case 0:
435 wk_mask = OMAP3430_ST_UART1_MASK;
436 padconf = 0x182;
437 break;
438 case 1:
439 wk_mask = OMAP3430_ST_UART2_MASK;
440 padconf = 0x17a;
441 break;
442 case 2:
443 wk_mask = OMAP3430_ST_UART3_MASK;
444 padconf = 0x19e;
445 break;
446 }
447 uart->wk_mask = wk_mask;
448 uart->padconf = padconf;
449 } else if (cpu_is_omap24xx()) {
450 u32 wk_mask = 0;
451
452 if (cpu_is_omap2430()) {
453 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
454 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
455 } else if (cpu_is_omap2420()) {
456 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
457 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
458 }
459 switch (uart->num) {
460 case 0:
461 wk_mask = OMAP24XX_ST_UART1_MASK;
462 break;
463 case 1:
464 wk_mask = OMAP24XX_ST_UART2_MASK;
465 break;
466 case 2:
467 wk_mask = OMAP24XX_ST_UART3_MASK;
468 break;
469 }
470 uart->wk_mask = wk_mask;
471 } else {
472 uart->wk_en = 0;
473 uart->wk_st = 0;
474 uart->wk_mask = 0;
475 uart->padconf = 0;
476 }
477
478 p->irqflags |= IRQF_SHARED;
479 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
480 "serial idle", (void *)uart);
481 WARN_ON(ret);
482}
483
484void omap_uart_enable_irqs(int enable)
485{
486 int ret;
487 struct omap_uart_state *uart;
488
489 list_for_each_entry(uart, &uart_list, node) {
490 if (enable)
491 ret = request_irq(uart->p->irq, omap_uart_interrupt,
492 IRQF_SHARED, "serial idle", (void *)uart);
493 else
494 free_irq(uart->p->irq, (void *)uart);
495 }
496}
497
498static ssize_t sleep_timeout_show(struct device *dev,
499 struct device_attribute *attr,
500 char *buf)
501{
502 struct platform_device *pdev = container_of(dev,
503 struct platform_device, dev);
504 struct omap_uart_state *uart = container_of(pdev,
505 struct omap_uart_state, pdev);
506
507 return sprintf(buf, "%u\n", uart->timeout / HZ);
508}
509
510static ssize_t sleep_timeout_store(struct device *dev,
511 struct device_attribute *attr,
512 const char *buf, size_t n)
513{
514 struct platform_device *pdev = container_of(dev,
515 struct platform_device, dev);
516 struct omap_uart_state *uart = container_of(pdev,
517 struct omap_uart_state, pdev);
518 unsigned int value;
519
520 if (sscanf(buf, "%u", &value) != 1) {
521 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
522 return -EINVAL;
523 }
524
525 uart->timeout = value * HZ;
526 if (uart->timeout)
527 mod_timer(&uart->timer, jiffies + uart->timeout);
528 else
529
530 omap_uart_block_sleep(uart);
531
532 return n;
533}
534
535DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
536#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
537#else
538static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
539#define DEV_CREATE_FILE(dev, attr)
540#endif
541
542static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
543 {
544 .pdev = {
545 .name = "serial8250",
546 .id = PLAT8250_DEV_PLATFORM,
547 .dev = {
548 .platform_data = serial_platform_data0,
549 },
550 },
551 }, {
552 .pdev = {
553 .name = "serial8250",
554 .id = PLAT8250_DEV_PLATFORM1,
555 .dev = {
556 .platform_data = serial_platform_data1,
557 },
558 },
559 }, {
560 .pdev = {
561 .name = "serial8250",
562 .id = PLAT8250_DEV_PLATFORM2,
563 .dev = {
564 .platform_data = serial_platform_data2,
565 },
566 },
567 },
568#ifdef CONFIG_ARCH_OMAP4
569 {
570 .pdev = {
571 .name = "serial8250",
572 .id = 3,
573 .dev = {
574 .platform_data = serial_platform_data3,
575 },
576 },
577 },
578#endif
579};
580
581void __init omap_serial_early_init(void)
582{
583 int i;
584 char name[16];
585
586
587
588
589
590
591
592 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
593 struct omap_uart_state *uart = &omap_uart[i];
594 struct platform_device *pdev = &uart->pdev;
595 struct device *dev = &pdev->dev;
596 struct plat_serial8250_port *p = dev->platform_data;
597
598 sprintf(name, "uart%d_ick", i+1);
599 uart->ick = clk_get(NULL, name);
600 if (IS_ERR(uart->ick)) {
601 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
602 uart->ick = NULL;
603 }
604
605 sprintf(name, "uart%d_fck", i+1);
606 uart->fck = clk_get(NULL, name);
607 if (IS_ERR(uart->fck)) {
608 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
609 uart->fck = NULL;
610 }
611
612
613 if (!cpu_is_omap44xx()) {
614 if (!uart->ick || !uart->fck)
615 continue;
616 }
617
618 uart->num = i;
619 p->private_data = uart;
620 uart->p = p;
621 list_add_tail(&uart->node, &uart_list);
622
623 if (cpu_is_omap44xx())
624 p->irq += 32;
625
626 omap_uart_enable_clocks(uart);
627 }
628}
629
630void __init omap_serial_init(void)
631{
632 int i;
633
634 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
635 struct omap_uart_state *uart = &omap_uart[i];
636 struct platform_device *pdev = &uart->pdev;
637 struct device *dev = &pdev->dev;
638
639 omap_uart_reset(uart);
640 omap_uart_idle_init(uart);
641
642 if (WARN_ON(platform_device_register(pdev)))
643 continue;
644 if ((cpu_is_omap34xx() && uart->padconf) ||
645 (uart->wk_en && uart->wk_mask)) {
646 device_init_wakeup(dev, true);
647 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
648 }
649 }
650}
651
