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34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/sched.h>
37#include <linux/init.h>
38#include <linux/cpufreq.h>
39#include <linux/err.h>
40#include <linux/regulator/consumer.h>
41
42#include <mach/pxa2xx-regs.h>
43
44#ifdef DEBUG
45static unsigned int freq_debug;
46module_param(freq_debug, uint, 0);
47MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
48#else
49#define freq_debug 0
50#endif
51
52static struct regulator *vcc_core;
53
54static unsigned int pxa27x_maxfreq;
55module_param(pxa27x_maxfreq, uint, 0);
56MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
57 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
58
59typedef struct {
60 unsigned int khz;
61 unsigned int membus;
62 unsigned int cccr;
63 unsigned int div2;
64 unsigned int cclkcfg;
65 int vmin;
66 int vmax;
67} pxa_freqs_t;
68
69
70#define SDRAM_TREF 64
71static unsigned int sdram_rows;
72
73#define CCLKCFG_TURBO 0x1
74#define CCLKCFG_FCS 0x2
75#define CCLKCFG_HALFTURBO 0x4
76#define CCLKCFG_FASTBUS 0x8
77#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
78#define MDREFR_DRI_MASK 0xFFF
79
80#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
81#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
82
83
84
85
86
87#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
88
89static pxa_freqs_t pxa255_run_freqs[] =
90{
91
92 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1},
93 {132700, 132700, 0x123, 1, CCLKCFG, -1, -1},
94 {199100, 99500, 0x141, 0, CCLKCFG, -1, -1},
95 {265400, 132700, 0x143, 1, CCLKCFG, -1, -1},
96 {331800, 165900, 0x145, 1, CCLKCFG, -1, -1},
97 {398100, 99500, 0x161, 0, CCLKCFG, -1, -1},
98};
99
100
101static pxa_freqs_t pxa255_turbo_freqs[] =
102{
103
104 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1},
105 {199100, 99500, 0x221, 0, CCLKCFG, -1, -1},
106 {298500, 99500, 0x321, 0, CCLKCFG, -1, -1},
107 {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1},
108 {398100, 99500, 0x241, 0, CCLKCFG, -1, -1},
109};
110
111#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
112#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
113
114static struct cpufreq_frequency_table
115 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
116static struct cpufreq_frequency_table
117 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
118
119static unsigned int pxa255_turbo_table;
120module_param(pxa255_turbo_table, uint, 0);
121MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
122
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148
149#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
150#define CCLKCFG2(B, HT, T) \
151 (CCLKCFG_FCS | \
152 ((B) ? CCLKCFG_FASTBUS : 0) | \
153 ((HT) ? CCLKCFG_HALFTURBO : 0) | \
154 ((T) ? CCLKCFG_TURBO : 0))
155
156static pxa_freqs_t pxa27x_freqs[] = {
157 {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
158 {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
159 {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
160 {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
161 {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
162 {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
163 {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
164};
165
166#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
167static struct cpufreq_frequency_table
168 pxa27x_freq_table[NUM_PXA27x_FREQS+1];
169
170extern unsigned get_clk_frequency_khz(int info);
171
172#ifdef CONFIG_REGULATOR
173
174static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
175{
176 int ret = 0;
177 int vmin, vmax;
178
179 if (!cpu_is_pxa27x())
180 return 0;
181
182 vmin = pxa_freq->vmin;
183 vmax = pxa_freq->vmax;
184 if ((vmin == -1) || (vmax == -1))
185 return 0;
186
187 ret = regulator_set_voltage(vcc_core, vmin, vmax);
188 if (ret)
189 pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
190 vmin, vmax);
191 return ret;
192}
193
194static __init void pxa_cpufreq_init_voltages(void)
195{
196 vcc_core = regulator_get(NULL, "vcc_core");
197 if (IS_ERR(vcc_core)) {
198 pr_info("cpufreq: Didn't find vcc_core regulator\n");
199 vcc_core = NULL;
200 } else {
201 pr_info("cpufreq: Found vcc_core regulator\n");
202 }
203}
204#else
205static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
206{
207 return 0;
208}
209
210static __init void pxa_cpufreq_init_voltages(void) { }
211#endif
212
213static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
214 pxa_freqs_t **pxa_freqs)
215{
216 if (cpu_is_pxa25x()) {
217 if (!pxa255_turbo_table) {
218 *pxa_freqs = pxa255_run_freqs;
219 *freq_table = pxa255_run_freq_table;
220 } else {
221 *pxa_freqs = pxa255_turbo_freqs;
222 *freq_table = pxa255_turbo_freq_table;
223 }
224 }
225 if (cpu_is_pxa27x()) {
226 *pxa_freqs = pxa27x_freqs;
227 *freq_table = pxa27x_freq_table;
228 }
229}
230
231static void pxa27x_guess_max_freq(void)
232{
233 if (!pxa27x_maxfreq) {
234 pxa27x_maxfreq = 416000;
235 printk(KERN_INFO "PXA CPU 27x max frequency not defined "
236 "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
237 pxa27x_maxfreq);
238 } else {
239 pxa27x_maxfreq *= 1000;
240 }
241}
242
243static void init_sdram_rows(void)
244{
245 uint32_t mdcnfg = MDCNFG;
246 unsigned int drac2 = 0, drac0 = 0;
247
248 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
249 drac2 = MDCNFG_DRAC2(mdcnfg);
250
251 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
252 drac0 = MDCNFG_DRAC0(mdcnfg);
253
254 sdram_rows = 1 << (11 + max(drac0, drac2));
255}
256
257static u32 mdrefr_dri(unsigned int freq)
258{
259 u32 dri = 0;
260
261 if (cpu_is_pxa25x())
262 dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
263 if (cpu_is_pxa27x())
264 dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
265 return dri;
266}
267
268
269static int pxa_verify_policy(struct cpufreq_policy *policy)
270{
271 struct cpufreq_frequency_table *pxa_freqs_table;
272 pxa_freqs_t *pxa_freqs;
273 int ret;
274
275 find_freq_tables(&pxa_freqs_table, &pxa_freqs);
276 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
277
278 if (freq_debug)
279 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
280 policy->min, policy->max);
281
282 return ret;
283}
284
285static unsigned int pxa_cpufreq_get(unsigned int cpu)
286{
287 return get_clk_frequency_khz(0);
288}
289
290static int pxa_set_target(struct cpufreq_policy *policy,
291 unsigned int target_freq,
292 unsigned int relation)
293{
294 struct cpufreq_frequency_table *pxa_freqs_table;
295 pxa_freqs_t *pxa_freq_settings;
296 struct cpufreq_freqs freqs;
297 unsigned int idx;
298 unsigned long flags;
299 unsigned int new_freq_cpu, new_freq_mem;
300 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
301 int ret = 0;
302
303
304 find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
305
306
307 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
308 target_freq, relation, &idx)) {
309 return -EINVAL;
310 }
311
312 new_freq_cpu = pxa_freq_settings[idx].khz;
313 new_freq_mem = pxa_freq_settings[idx].membus;
314 freqs.old = policy->cur;
315 freqs.new = new_freq_cpu;
316 freqs.cpu = policy->cpu;
317
318 if (freq_debug)
319 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
320 "(SDRAM %d Mhz)\n",
321 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
322 (new_freq_mem / 2000) : (new_freq_mem / 1000));
323
324 if (vcc_core && freqs.new > freqs.old)
325 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
326 if (ret)
327 return ret;
328
329
330
331
332
333 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
334
335
336
337
338
339 preset_mdrefr = postset_mdrefr = MDREFR;
340 if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
341 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
342 preset_mdrefr |= mdrefr_dri(new_freq_mem);
343 }
344 postset_mdrefr =
345 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
346
347
348
349
350
351 if (pxa_freq_settings[idx].div2) {
352 preset_mdrefr |= MDREFR_DB2_MASK;
353 postset_mdrefr |= MDREFR_DB2_MASK;
354 } else {
355 postset_mdrefr &= ~MDREFR_DB2_MASK;
356 }
357
358 local_irq_save(flags);
359
360
361 CCCR = pxa_freq_settings[idx].cccr;
362 cclkcfg = pxa_freq_settings[idx].cclkcfg;
363
364 asm volatile(" \n\
365 ldr r4, [%1] \n\
366 b 2f \n\
367 .align 5 \n\
3681: \n\
369 str %3, [%1] \n\
370 mcr p14, 0, %2, c6, c0, 0 \n\
371 str %4, [%1] \n\
372 \n\
373 b 3f \n\
3742: b 1b \n\
3753: nop \n\
376 "
377 : "=&r" (unused)
378 : "r" (&MDREFR), "r" (cclkcfg),
379 "r" (preset_mdrefr), "r" (postset_mdrefr)
380 : "r4", "r5");
381 local_irq_restore(flags);
382
383
384
385
386
387
388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
389
390
391
392
393
394
395
396
397
398
399 if (vcc_core && freqs.new < freqs.old)
400 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
401
402 return 0;
403}
404
405static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
406{
407 int i;
408 unsigned int freq;
409 struct cpufreq_frequency_table *pxa255_freq_table;
410 pxa_freqs_t *pxa255_freqs;
411
412
413 if (cpu_is_pxa27x())
414 pxa27x_guess_max_freq();
415
416 pxa_cpufreq_init_voltages();
417
418 init_sdram_rows();
419
420
421 policy->cpuinfo.transition_latency = 1000;
422 policy->cur = get_clk_frequency_khz(0);
423 policy->min = policy->max = policy->cur;
424
425
426 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
427 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
428 pxa255_run_freq_table[i].index = i;
429 }
430 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
431
432
433 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
434 pxa255_turbo_freq_table[i].frequency =
435 pxa255_turbo_freqs[i].khz;
436 pxa255_turbo_freq_table[i].index = i;
437 }
438 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
439
440 pxa255_turbo_table = !!pxa255_turbo_table;
441
442
443 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
444 freq = pxa27x_freqs[i].khz;
445 if (freq > pxa27x_maxfreq)
446 break;
447 pxa27x_freq_table[i].frequency = freq;
448 pxa27x_freq_table[i].index = i;
449 }
450 pxa27x_freq_table[i].index = i;
451 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
452
453
454
455
456
457 if (cpu_is_pxa25x()) {
458 find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
459 pr_info("PXA255 cpufreq using %s frequency table\n",
460 pxa255_turbo_table ? "turbo" : "run");
461 cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
462 }
463 else if (cpu_is_pxa27x())
464 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
465
466 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
467
468 return 0;
469}
470
471static struct cpufreq_driver pxa_cpufreq_driver = {
472 .verify = pxa_verify_policy,
473 .target = pxa_set_target,
474 .init = pxa_cpufreq_init,
475 .get = pxa_cpufreq_get,
476 .name = "PXA2xx",
477};
478
479static int __init pxa_cpu_init(void)
480{
481 int ret = -ENODEV;
482 if (cpu_is_pxa25x() || cpu_is_pxa27x())
483 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
484 return ret;
485}
486
487static void __exit pxa_cpu_exit(void)
488{
489 cpufreq_unregister_driver(&pxa_cpufreq_driver);
490}
491
492
493MODULE_AUTHOR("Intrinsyc Software Inc.");
494MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
495MODULE_LICENSE("GPL");
496module_init(pxa_cpu_init);
497module_exit(pxa_cpu_exit);
498