1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h>
6
7#include <mach/udc.h>
8#include <mach/pxafb.h>
9#include <mach/mmc.h>
10#include <mach/irda.h>
11#include <plat/i2c.h>
12#include <mach/ohci.h>
13#include <mach/pxa27x_keypad.h>
14#include <mach/pxa2xx_spi.h>
15#include <mach/camera.h>
16#include <mach/audio.h>
17#include <mach/pxa3xx_nand.h>
18
19#include "devices.h"
20#include "generic.h"
21
22void __init pxa_register_device(struct platform_device *dev, void *data)
23{
24 int ret;
25
26 dev->dev.platform_data = data;
27
28 ret = platform_device_register(dev);
29 if (ret)
30 dev_err(&dev->dev, "unable to register device: %d\n", ret);
31}
32
33static struct resource pxamci_resources[] = {
34 [0] = {
35 .start = 0x41100000,
36 .end = 0x41100fff,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_MMC,
41 .end = IRQ_MMC,
42 .flags = IORESOURCE_IRQ,
43 },
44 [2] = {
45 .start = 21,
46 .end = 21,
47 .flags = IORESOURCE_DMA,
48 },
49 [3] = {
50 .start = 22,
51 .end = 22,
52 .flags = IORESOURCE_DMA,
53 },
54};
55
56static u64 pxamci_dmamask = 0xffffffffUL;
57
58struct platform_device pxa_device_mci = {
59 .name = "pxa2xx-mci",
60 .id = 0,
61 .dev = {
62 .dma_mask = &pxamci_dmamask,
63 .coherent_dma_mask = 0xffffffff,
64 },
65 .num_resources = ARRAY_SIZE(pxamci_resources),
66 .resource = pxamci_resources,
67};
68
69void __init pxa_set_mci_info(struct pxamci_platform_data *info)
70{
71 pxa_register_device(&pxa_device_mci, info);
72}
73
74
75static struct pxa2xx_udc_mach_info pxa_udc_info = {
76 .gpio_pullup = -1,
77 .gpio_vbus = -1,
78};
79
80void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
81{
82 memcpy(&pxa_udc_info, info, sizeof *info);
83}
84
85static struct resource pxa2xx_udc_resources[] = {
86 [0] = {
87 .start = 0x40600000,
88 .end = 0x4060ffff,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 .start = IRQ_USB,
93 .end = IRQ_USB,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static u64 udc_dma_mask = ~(u32)0;
99
100struct platform_device pxa25x_device_udc = {
101 .name = "pxa25x-udc",
102 .id = -1,
103 .resource = pxa2xx_udc_resources,
104 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
105 .dev = {
106 .platform_data = &pxa_udc_info,
107 .dma_mask = &udc_dma_mask,
108 }
109};
110
111struct platform_device pxa27x_device_udc = {
112 .name = "pxa27x-udc",
113 .id = -1,
114 .resource = pxa2xx_udc_resources,
115 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
116 .dev = {
117 .platform_data = &pxa_udc_info,
118 .dma_mask = &udc_dma_mask,
119 }
120};
121
122static struct resource pxafb_resources[] = {
123 [0] = {
124 .start = 0x44000000,
125 .end = 0x4400ffff,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = IRQ_LCD,
130 .end = IRQ_LCD,
131 .flags = IORESOURCE_IRQ,
132 },
133};
134
135static u64 fb_dma_mask = ~(u64)0;
136
137struct platform_device pxa_device_fb = {
138 .name = "pxa2xx-fb",
139 .id = -1,
140 .dev = {
141 .dma_mask = &fb_dma_mask,
142 .coherent_dma_mask = 0xffffffff,
143 },
144 .num_resources = ARRAY_SIZE(pxafb_resources),
145 .resource = pxafb_resources,
146};
147
148void __init set_pxa_fb_info(struct pxafb_mach_info *info)
149{
150 pxa_register_device(&pxa_device_fb, info);
151}
152
153void __init set_pxa_fb_parent(struct device *parent_dev)
154{
155 pxa_device_fb.dev.parent = parent_dev;
156}
157
158static struct resource pxa_resource_ffuart[] = {
159 {
160 .start = 0x40100000,
161 .end = 0x40100023,
162 .flags = IORESOURCE_MEM,
163 }, {
164 .start = IRQ_FFUART,
165 .end = IRQ_FFUART,
166 .flags = IORESOURCE_IRQ,
167 }
168};
169
170struct platform_device pxa_device_ffuart= {
171 .name = "pxa2xx-uart",
172 .id = 0,
173 .resource = pxa_resource_ffuart,
174 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
175};
176
177static struct resource pxa_resource_btuart[] = {
178 {
179 .start = 0x40200000,
180 .end = 0x40200023,
181 .flags = IORESOURCE_MEM,
182 }, {
183 .start = IRQ_BTUART,
184 .end = IRQ_BTUART,
185 .flags = IORESOURCE_IRQ,
186 }
187};
188
189struct platform_device pxa_device_btuart = {
190 .name = "pxa2xx-uart",
191 .id = 1,
192 .resource = pxa_resource_btuart,
193 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
194};
195
196static struct resource pxa_resource_stuart[] = {
197 {
198 .start = 0x40700000,
199 .end = 0x40700023,
200 .flags = IORESOURCE_MEM,
201 }, {
202 .start = IRQ_STUART,
203 .end = IRQ_STUART,
204 .flags = IORESOURCE_IRQ,
205 }
206};
207
208struct platform_device pxa_device_stuart = {
209 .name = "pxa2xx-uart",
210 .id = 2,
211 .resource = pxa_resource_stuart,
212 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
213};
214
215static struct resource pxa_resource_hwuart[] = {
216 {
217 .start = 0x41600000,
218 .end = 0x4160002F,
219 .flags = IORESOURCE_MEM,
220 }, {
221 .start = IRQ_HWUART,
222 .end = IRQ_HWUART,
223 .flags = IORESOURCE_IRQ,
224 }
225};
226
227struct platform_device pxa_device_hwuart = {
228 .name = "pxa2xx-uart",
229 .id = 3,
230 .resource = pxa_resource_hwuart,
231 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
232};
233
234static struct resource pxai2c_resources[] = {
235 {
236 .start = 0x40301680,
237 .end = 0x403016a3,
238 .flags = IORESOURCE_MEM,
239 }, {
240 .start = IRQ_I2C,
241 .end = IRQ_I2C,
242 .flags = IORESOURCE_IRQ,
243 },
244};
245
246struct platform_device pxa_device_i2c = {
247 .name = "pxa2xx-i2c",
248 .id = 0,
249 .resource = pxai2c_resources,
250 .num_resources = ARRAY_SIZE(pxai2c_resources),
251};
252
253void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
254{
255 pxa_register_device(&pxa_device_i2c, info);
256}
257
258#ifdef CONFIG_PXA27x
259static struct resource pxa27x_resources_i2c_power[] = {
260 {
261 .start = 0x40f00180,
262 .end = 0x40f001a3,
263 .flags = IORESOURCE_MEM,
264 }, {
265 .start = IRQ_PWRI2C,
266 .end = IRQ_PWRI2C,
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
271struct platform_device pxa27x_device_i2c_power = {
272 .name = "pxa2xx-i2c",
273 .id = 1,
274 .resource = pxa27x_resources_i2c_power,
275 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
276};
277#endif
278
279#ifdef CONFIG_PXA3xx
280static struct resource pxa3xx_resources_i2c_power[] = {
281 {
282 .start = 0x40f500c0,
283 .end = 0x40f500d3,
284 .flags = IORESOURCE_MEM,
285 }, {
286 .start = IRQ_PWRI2C,
287 .end = IRQ_PWRI2C,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292struct platform_device pxa3xx_device_i2c_power = {
293 .name = "pxa3xx-pwri2c",
294 .id = 1,
295 .resource = pxa3xx_resources_i2c_power,
296 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
297};
298#endif
299
300static struct resource pxai2s_resources[] = {
301 {
302 .start = 0x40400000,
303 .end = 0x40400083,
304 .flags = IORESOURCE_MEM,
305 }, {
306 .start = IRQ_I2S,
307 .end = IRQ_I2S,
308 .flags = IORESOURCE_IRQ,
309 },
310};
311
312struct platform_device pxa_device_i2s = {
313 .name = "pxa2xx-i2s",
314 .id = -1,
315 .resource = pxai2s_resources,
316 .num_resources = ARRAY_SIZE(pxai2s_resources),
317};
318
319static u64 pxaficp_dmamask = ~(u32)0;
320
321struct platform_device pxa_device_ficp = {
322 .name = "pxa2xx-ir",
323 .id = -1,
324 .dev = {
325 .dma_mask = &pxaficp_dmamask,
326 .coherent_dma_mask = 0xffffffff,
327 },
328};
329
330void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
331{
332 pxa_register_device(&pxa_device_ficp, info);
333}
334
335static struct resource pxa_rtc_resources[] = {
336 [0] = {
337 .start = 0x40900000,
338 .end = 0x40900000 + 0x3b,
339 .flags = IORESOURCE_MEM,
340 },
341 [1] = {
342 .start = IRQ_RTC1Hz,
343 .end = IRQ_RTC1Hz,
344 .flags = IORESOURCE_IRQ,
345 },
346 [2] = {
347 .start = IRQ_RTCAlrm,
348 .end = IRQ_RTCAlrm,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
353struct platform_device sa1100_device_rtc = {
354 .name = "sa1100-rtc",
355 .id = -1,
356};
357
358struct platform_device pxa_device_rtc = {
359 .name = "pxa-rtc",
360 .id = -1,
361 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
362 .resource = pxa_rtc_resources,
363};
364
365static struct resource pxa_ac97_resources[] = {
366 [0] = {
367 .start = 0x40500000,
368 .end = 0x40500000 + 0xfff,
369 .flags = IORESOURCE_MEM,
370 },
371 [1] = {
372 .start = IRQ_AC97,
373 .end = IRQ_AC97,
374 .flags = IORESOURCE_IRQ,
375 },
376};
377
378static u64 pxa_ac97_dmamask = 0xffffffffUL;
379
380struct platform_device pxa_device_ac97 = {
381 .name = "pxa2xx-ac97",
382 .id = -1,
383 .dev = {
384 .dma_mask = &pxa_ac97_dmamask,
385 .coherent_dma_mask = 0xffffffff,
386 },
387 .num_resources = ARRAY_SIZE(pxa_ac97_resources),
388 .resource = pxa_ac97_resources,
389};
390
391void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
392{
393 pxa_register_device(&pxa_device_ac97, ops);
394}
395
396#ifdef CONFIG_PXA25x
397
398static struct resource pxa25x_resource_pwm0[] = {
399 [0] = {
400 .start = 0x40b00000,
401 .end = 0x40b0000f,
402 .flags = IORESOURCE_MEM,
403 },
404};
405
406struct platform_device pxa25x_device_pwm0 = {
407 .name = "pxa25x-pwm",
408 .id = 0,
409 .resource = pxa25x_resource_pwm0,
410 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
411};
412
413static struct resource pxa25x_resource_pwm1[] = {
414 [0] = {
415 .start = 0x40c00000,
416 .end = 0x40c0000f,
417 .flags = IORESOURCE_MEM,
418 },
419};
420
421struct platform_device pxa25x_device_pwm1 = {
422 .name = "pxa25x-pwm",
423 .id = 1,
424 .resource = pxa25x_resource_pwm1,
425 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
426};
427
428static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
429
430static struct resource pxa25x_resource_ssp[] = {
431 [0] = {
432 .start = 0x41000000,
433 .end = 0x4100001f,
434 .flags = IORESOURCE_MEM,
435 },
436 [1] = {
437 .start = IRQ_SSP,
438 .end = IRQ_SSP,
439 .flags = IORESOURCE_IRQ,
440 },
441 [2] = {
442
443 .start = 13,
444 .end = 13,
445 .flags = IORESOURCE_DMA,
446 },
447 [3] = {
448
449 .start = 14,
450 .end = 14,
451 .flags = IORESOURCE_DMA,
452 },
453};
454
455struct platform_device pxa25x_device_ssp = {
456 .name = "pxa25x-ssp",
457 .id = 0,
458 .dev = {
459 .dma_mask = &pxa25x_ssp_dma_mask,
460 .coherent_dma_mask = DMA_BIT_MASK(32),
461 },
462 .resource = pxa25x_resource_ssp,
463 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
464};
465
466static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
467
468static struct resource pxa25x_resource_nssp[] = {
469 [0] = {
470 .start = 0x41400000,
471 .end = 0x4140002f,
472 .flags = IORESOURCE_MEM,
473 },
474 [1] = {
475 .start = IRQ_NSSP,
476 .end = IRQ_NSSP,
477 .flags = IORESOURCE_IRQ,
478 },
479 [2] = {
480
481 .start = 15,
482 .end = 15,
483 .flags = IORESOURCE_DMA,
484 },
485 [3] = {
486
487 .start = 16,
488 .end = 16,
489 .flags = IORESOURCE_DMA,
490 },
491};
492
493struct platform_device pxa25x_device_nssp = {
494 .name = "pxa25x-nssp",
495 .id = 1,
496 .dev = {
497 .dma_mask = &pxa25x_nssp_dma_mask,
498 .coherent_dma_mask = DMA_BIT_MASK(32),
499 },
500 .resource = pxa25x_resource_nssp,
501 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
502};
503
504static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
505
506static struct resource pxa25x_resource_assp[] = {
507 [0] = {
508 .start = 0x41500000,
509 .end = 0x4150002f,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = IRQ_ASSP,
514 .end = IRQ_ASSP,
515 .flags = IORESOURCE_IRQ,
516 },
517 [2] = {
518
519 .start = 23,
520 .end = 23,
521 .flags = IORESOURCE_DMA,
522 },
523 [3] = {
524
525 .start = 24,
526 .end = 24,
527 .flags = IORESOURCE_DMA,
528 },
529};
530
531struct platform_device pxa25x_device_assp = {
532
533 .name = "pxa25x-nssp",
534 .id = 2,
535 .dev = {
536 .dma_mask = &pxa25x_assp_dma_mask,
537 .coherent_dma_mask = DMA_BIT_MASK(32),
538 },
539 .resource = pxa25x_resource_assp,
540 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
541};
542#endif
543
544#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
545
546static struct resource pxa27x_resource_keypad[] = {
547 [0] = {
548 .start = 0x41500000,
549 .end = 0x4150004c,
550 .flags = IORESOURCE_MEM,
551 },
552 [1] = {
553 .start = IRQ_KEYPAD,
554 .end = IRQ_KEYPAD,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559struct platform_device pxa27x_device_keypad = {
560 .name = "pxa27x-keypad",
561 .id = -1,
562 .resource = pxa27x_resource_keypad,
563 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
564};
565
566void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
567{
568 pxa_register_device(&pxa27x_device_keypad, info);
569}
570
571static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
572
573static struct resource pxa27x_resource_ohci[] = {
574 [0] = {
575 .start = 0x4C000000,
576 .end = 0x4C00ff6f,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = IRQ_USBH1,
581 .end = IRQ_USBH1,
582 .flags = IORESOURCE_IRQ,
583 },
584};
585
586struct platform_device pxa27x_device_ohci = {
587 .name = "pxa27x-ohci",
588 .id = -1,
589 .dev = {
590 .dma_mask = &pxa27x_ohci_dma_mask,
591 .coherent_dma_mask = DMA_BIT_MASK(32),
592 },
593 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
594 .resource = pxa27x_resource_ohci,
595};
596
597void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
598{
599 pxa_register_device(&pxa27x_device_ohci, info);
600}
601
602static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
603
604static struct resource pxa27x_resource_ssp1[] = {
605 [0] = {
606 .start = 0x41000000,
607 .end = 0x4100003f,
608 .flags = IORESOURCE_MEM,
609 },
610 [1] = {
611 .start = IRQ_SSP,
612 .end = IRQ_SSP,
613 .flags = IORESOURCE_IRQ,
614 },
615 [2] = {
616
617 .start = 13,
618 .end = 13,
619 .flags = IORESOURCE_DMA,
620 },
621 [3] = {
622
623 .start = 14,
624 .end = 14,
625 .flags = IORESOURCE_DMA,
626 },
627};
628
629struct platform_device pxa27x_device_ssp1 = {
630 .name = "pxa27x-ssp",
631 .id = 0,
632 .dev = {
633 .dma_mask = &pxa27x_ssp1_dma_mask,
634 .coherent_dma_mask = DMA_BIT_MASK(32),
635 },
636 .resource = pxa27x_resource_ssp1,
637 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
638};
639
640static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
641
642static struct resource pxa27x_resource_ssp2[] = {
643 [0] = {
644 .start = 0x41700000,
645 .end = 0x4170003f,
646 .flags = IORESOURCE_MEM,
647 },
648 [1] = {
649 .start = IRQ_SSP2,
650 .end = IRQ_SSP2,
651 .flags = IORESOURCE_IRQ,
652 },
653 [2] = {
654
655 .start = 15,
656 .end = 15,
657 .flags = IORESOURCE_DMA,
658 },
659 [3] = {
660
661 .start = 16,
662 .end = 16,
663 .flags = IORESOURCE_DMA,
664 },
665};
666
667struct platform_device pxa27x_device_ssp2 = {
668 .name = "pxa27x-ssp",
669 .id = 1,
670 .dev = {
671 .dma_mask = &pxa27x_ssp2_dma_mask,
672 .coherent_dma_mask = DMA_BIT_MASK(32),
673 },
674 .resource = pxa27x_resource_ssp2,
675 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
676};
677
678static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
679
680static struct resource pxa27x_resource_ssp3[] = {
681 [0] = {
682 .start = 0x41900000,
683 .end = 0x4190003f,
684 .flags = IORESOURCE_MEM,
685 },
686 [1] = {
687 .start = IRQ_SSP3,
688 .end = IRQ_SSP3,
689 .flags = IORESOURCE_IRQ,
690 },
691 [2] = {
692
693 .start = 66,
694 .end = 66,
695 .flags = IORESOURCE_DMA,
696 },
697 [3] = {
698
699 .start = 67,
700 .end = 67,
701 .flags = IORESOURCE_DMA,
702 },
703};
704
705struct platform_device pxa27x_device_ssp3 = {
706 .name = "pxa27x-ssp",
707 .id = 2,
708 .dev = {
709 .dma_mask = &pxa27x_ssp3_dma_mask,
710 .coherent_dma_mask = DMA_BIT_MASK(32),
711 },
712 .resource = pxa27x_resource_ssp3,
713 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
714};
715
716static struct resource pxa27x_resource_pwm0[] = {
717 [0] = {
718 .start = 0x40b00000,
719 .end = 0x40b0001f,
720 .flags = IORESOURCE_MEM,
721 },
722};
723
724struct platform_device pxa27x_device_pwm0 = {
725 .name = "pxa27x-pwm",
726 .id = 0,
727 .resource = pxa27x_resource_pwm0,
728 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
729};
730
731static struct resource pxa27x_resource_pwm1[] = {
732 [0] = {
733 .start = 0x40c00000,
734 .end = 0x40c0001f,
735 .flags = IORESOURCE_MEM,
736 },
737};
738
739struct platform_device pxa27x_device_pwm1 = {
740 .name = "pxa27x-pwm",
741 .id = 1,
742 .resource = pxa27x_resource_pwm1,
743 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
744};
745
746static struct resource pxa27x_resource_camera[] = {
747 [0] = {
748 .start = 0x50000000,
749 .end = 0x50000fff,
750 .flags = IORESOURCE_MEM,
751 },
752 [1] = {
753 .start = IRQ_CAMERA,
754 .end = IRQ_CAMERA,
755 .flags = IORESOURCE_IRQ,
756 },
757};
758
759static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
760
761static struct platform_device pxa27x_device_camera = {
762 .name = "pxa27x-camera",
763 .id = 0,
764 .dev = {
765 .dma_mask = &pxa27x_dma_mask_camera,
766 .coherent_dma_mask = 0xffffffff,
767 },
768 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
769 .resource = pxa27x_resource_camera,
770};
771
772void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
773{
774 pxa_register_device(&pxa27x_device_camera, info);
775}
776#endif
777
778#ifdef CONFIG_PXA3xx
779static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
780
781static struct resource pxa3xx_resource_ssp4[] = {
782 [0] = {
783 .start = 0x41a00000,
784 .end = 0x41a0003f,
785 .flags = IORESOURCE_MEM,
786 },
787 [1] = {
788 .start = IRQ_SSP4,
789 .end = IRQ_SSP4,
790 .flags = IORESOURCE_IRQ,
791 },
792 [2] = {
793
794 .start = 2,
795 .end = 2,
796 .flags = IORESOURCE_DMA,
797 },
798 [3] = {
799
800 .start = 3,
801 .end = 3,
802 .flags = IORESOURCE_DMA,
803 },
804};
805
806struct platform_device pxa3xx_device_ssp4 = {
807
808 .name = "pxa27x-ssp",
809 .id = 3,
810 .dev = {
811 .dma_mask = &pxa3xx_ssp4_dma_mask,
812 .coherent_dma_mask = DMA_BIT_MASK(32),
813 },
814 .resource = pxa3xx_resource_ssp4,
815 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
816};
817
818static struct resource pxa3xx_resources_mci2[] = {
819 [0] = {
820 .start = 0x42000000,
821 .end = 0x42000fff,
822 .flags = IORESOURCE_MEM,
823 },
824 [1] = {
825 .start = IRQ_MMC2,
826 .end = IRQ_MMC2,
827 .flags = IORESOURCE_IRQ,
828 },
829 [2] = {
830 .start = 93,
831 .end = 93,
832 .flags = IORESOURCE_DMA,
833 },
834 [3] = {
835 .start = 94,
836 .end = 94,
837 .flags = IORESOURCE_DMA,
838 },
839};
840
841struct platform_device pxa3xx_device_mci2 = {
842 .name = "pxa2xx-mci",
843 .id = 1,
844 .dev = {
845 .dma_mask = &pxamci_dmamask,
846 .coherent_dma_mask = 0xffffffff,
847 },
848 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
849 .resource = pxa3xx_resources_mci2,
850};
851
852void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
853{
854 pxa_register_device(&pxa3xx_device_mci2, info);
855}
856
857static struct resource pxa3xx_resources_mci3[] = {
858 [0] = {
859 .start = 0x42500000,
860 .end = 0x42500fff,
861 .flags = IORESOURCE_MEM,
862 },
863 [1] = {
864 .start = IRQ_MMC3,
865 .end = IRQ_MMC3,
866 .flags = IORESOURCE_IRQ,
867 },
868 [2] = {
869 .start = 100,
870 .end = 100,
871 .flags = IORESOURCE_DMA,
872 },
873 [3] = {
874 .start = 101,
875 .end = 101,
876 .flags = IORESOURCE_DMA,
877 },
878};
879
880struct platform_device pxa3xx_device_mci3 = {
881 .name = "pxa2xx-mci",
882 .id = 2,
883 .dev = {
884 .dma_mask = &pxamci_dmamask,
885 .coherent_dma_mask = 0xffffffff,
886 },
887 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
888 .resource = pxa3xx_resources_mci3,
889};
890
891void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
892{
893 pxa_register_device(&pxa3xx_device_mci3, info);
894}
895
896static struct resource pxa3xx_resources_nand[] = {
897 [0] = {
898 .start = 0x43100000,
899 .end = 0x43100053,
900 .flags = IORESOURCE_MEM,
901 },
902 [1] = {
903 .start = IRQ_NAND,
904 .end = IRQ_NAND,
905 .flags = IORESOURCE_IRQ,
906 },
907 [2] = {
908
909 .start = 97,
910 .end = 97,
911 .flags = IORESOURCE_DMA,
912 },
913 [3] = {
914
915 .start = 99,
916 .end = 99,
917 .flags = IORESOURCE_DMA,
918 },
919};
920
921static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
922
923struct platform_device pxa3xx_device_nand = {
924 .name = "pxa3xx-nand",
925 .id = -1,
926 .dev = {
927 .dma_mask = &pxa3xx_nand_dma_mask,
928 .coherent_dma_mask = DMA_BIT_MASK(32),
929 },
930 .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
931 .resource = pxa3xx_resources_nand,
932};
933
934void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
935{
936 pxa_register_device(&pxa3xx_device_nand, info);
937}
938
939static struct resource pxa3xx_resources_gcu[] = {
940 {
941 .start = 0x54000000,
942 .end = 0x54000fff,
943 .flags = IORESOURCE_MEM,
944 },
945 {
946 .start = IRQ_GCU,
947 .end = IRQ_GCU,
948 .flags = IORESOURCE_IRQ,
949 },
950};
951
952static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
953
954struct platform_device pxa3xx_device_gcu = {
955 .name = "pxa3xx-gcu",
956 .id = -1,
957 .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
958 .resource = pxa3xx_resources_gcu,
959 .dev = {
960 .dma_mask = &pxa3xx_gcu_dmamask,
961 .coherent_dma_mask = 0xffffffff,
962 },
963};
964
965#endif
966
967
968
969void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
970{
971 struct platform_device *pd;
972
973 pd = platform_device_alloc("pxa2xx-spi", id);
974 if (pd == NULL) {
975 printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
976 id);
977 return;
978 }
979
980 pd->dev.platform_data = info;
981 platform_device_add(pd);
982}
983
