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14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H
16
17#include <mach/hardware.h>
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19
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21
22
23#define PXA_CS0_PHYS 0x00000000
24#define PXA_CS1_PHYS 0x04000000
25#define PXA_CS2_PHYS 0x08000000
26#define PXA_CS3_PHYS 0x0C000000
27#define PXA_CS4_PHYS 0x10000000
28#define PXA_CS5_PHYS 0x14000000
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33
34#define MDCNFG __REG(0x48000000)
35#define MDREFR __REG(0x48000004)
36#define MSC0 __REG(0x48000008)
37#define MSC1 __REG(0x4800000C)
38#define MSC2 __REG(0x48000010)
39#define MECR __REG(0x48000014)
40#define SXLCR __REG(0x48000018)
41#define SXCNFG __REG(0x4800001C)
42#define SXMRS __REG(0x48000024)
43#define MCMEM0 __REG(0x48000028)
44#define MCMEM1 __REG(0x4800002C)
45#define MCATT0 __REG(0x48000030)
46#define MCATT1 __REG(0x48000034)
47#define MCIO0 __REG(0x48000038)
48#define MCIO1 __REG(0x4800003C)
49#define MDMRS __REG(0x48000040)
50#define BOOT_DEF __REG(0x48000044)
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55
56
57#define MCMEM(s) __REG2(0x48000028, (s)<<2 )
58#define MCATT(s) __REG2(0x48000030, (s)<<2 )
59#define MCIO(s) __REG2(0x48000038, (s)<<2 )
60
61
62#define MECR_NOS (1 << 0)
63#define MECR_CIT (1 << 1)
64
65#define MDCNFG_DE0 (1 << 0)
66#define MDCNFG_DE1 (1 << 1)
67#define MDCNFG_DE2 (1 << 16)
68#define MDCNFG_DE3 (1 << 17)
69
70#define MDREFR_K0DB4 (1 << 29)
71#define MDREFR_K2FREE (1 << 25)
72#define MDREFR_K1FREE (1 << 24)
73#define MDREFR_K0FREE (1 << 23)
74#define MDREFR_SLFRSH (1 << 22)
75#define MDREFR_APD (1 << 20)
76#define MDREFR_K2DB2 (1 << 19)
77#define MDREFR_K2RUN (1 << 18)
78#define MDREFR_K1DB2 (1 << 17)
79#define MDREFR_K1RUN (1 << 16)
80#define MDREFR_E1PIN (1 << 15)
81#define MDREFR_K0DB2 (1 << 14)
82#define MDREFR_K0RUN (1 << 13)
83#define MDREFR_E0PIN (1 << 12)
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87
88
89#define PMCR __REG(0x40F00000)
90#define PSSR __REG(0x40F00004)
91#define PSPR __REG(0x40F00008)
92#define PWER __REG(0x40F0000C)
93#define PRER __REG(0x40F00010)
94#define PFER __REG(0x40F00014)
95#define PEDR __REG(0x40F00018)
96#define PCFR __REG(0x40F0001C)
97#define PGSR0 __REG(0x40F00020)
98#define PGSR1 __REG(0x40F00024)
99#define PGSR2 __REG(0x40F00028)
100#define PGSR3 __REG(0x40F0002C)
101#define RCSR __REG(0x40F00030)
102
103#define PSLR __REG(0x40F00034)
104#define PSTR __REG(0x40F00038)
105#define PSNR __REG(0x40F0003C)
106#define PVCR __REG(0x40F00040)
107#define PKWR __REG(0x40F00050)
108#define PKSR __REG(0x40F00054)
109#define PCMD(x) __REG2(0x40F00080, (x)<<2)
110#define PCMD0 __REG(0x40F00080 + 0 * 4)
111#define PCMD1 __REG(0x40F00080 + 1 * 4)
112#define PCMD2 __REG(0x40F00080 + 2 * 4)
113#define PCMD3 __REG(0x40F00080 + 3 * 4)
114#define PCMD4 __REG(0x40F00080 + 4 * 4)
115#define PCMD5 __REG(0x40F00080 + 5 * 4)
116#define PCMD6 __REG(0x40F00080 + 6 * 4)
117#define PCMD7 __REG(0x40F00080 + 7 * 4)
118#define PCMD8 __REG(0x40F00080 + 8 * 4)
119#define PCMD9 __REG(0x40F00080 + 9 * 4)
120#define PCMD10 __REG(0x40F00080 + 10 * 4)
121#define PCMD11 __REG(0x40F00080 + 11 * 4)
122#define PCMD12 __REG(0x40F00080 + 12 * 4)
123#define PCMD13 __REG(0x40F00080 + 13 * 4)
124#define PCMD14 __REG(0x40F00080 + 14 * 4)
125#define PCMD15 __REG(0x40F00080 + 15 * 4)
126#define PCMD16 __REG(0x40F00080 + 16 * 4)
127#define PCMD17 __REG(0x40F00080 + 17 * 4)
128#define PCMD18 __REG(0x40F00080 + 18 * 4)
129#define PCMD19 __REG(0x40F00080 + 19 * 4)
130#define PCMD20 __REG(0x40F00080 + 20 * 4)
131#define PCMD21 __REG(0x40F00080 + 21 * 4)
132#define PCMD22 __REG(0x40F00080 + 22 * 4)
133#define PCMD23 __REG(0x40F00080 + 23 * 4)
134#define PCMD24 __REG(0x40F00080 + 24 * 4)
135#define PCMD25 __REG(0x40F00080 + 25 * 4)
136#define PCMD26 __REG(0x40F00080 + 26 * 4)
137#define PCMD27 __REG(0x40F00080 + 27 * 4)
138#define PCMD28 __REG(0x40F00080 + 28 * 4)
139#define PCMD29 __REG(0x40F00080 + 29 * 4)
140#define PCMD30 __REG(0x40F00080 + 30 * 4)
141#define PCMD31 __REG(0x40F00080 + 31 * 4)
142
143#define PCMD_MBC (1<<12)
144#define PCMD_DCE (1<<11)
145#define PCMD_LC (1<<10)
146
147#define PCMD_SQC (3<<8)
148
149#define PVCR_VCSA (0x1<<14)
150#define PVCR_CommandDelay (0xf80)
151#define PCFR_PI2C_EN (0x1 << 6)
152
153#define PSSR_OTGPH (1 << 6)
154#define PSSR_RDH (1 << 5)
155#define PSSR_PH (1 << 4)
156#define PSSR_STS (1 << 3)
157#define PSSR_VFS (1 << 2)
158#define PSSR_BFS (1 << 1)
159#define PSSR_SSS (1 << 0)
160
161#define PSLR_SL_ROD (1 << 20)
162
163#define PCFR_RO (1 << 15)
164#define PCFR_PO (1 << 14)
165#define PCFR_GPROD (1 << 12)
166#define PCFR_L1_EN (1 << 11)
167#define PCFR_FVC (1 << 10)
168#define PCFR_DC_EN (1 << 7)
169#define PCFR_PI2CEN (1 << 6)
170#define PCFR_GPR_EN (1 << 4)
171#define PCFR_DS (1 << 3)
172#define PCFR_FS (1 << 2)
173#define PCFR_FP (1 << 1)
174#define PCFR_OPDE (1 << 0)
175
176#define RCSR_GPR (1 << 3)
177#define RCSR_SMR (1 << 2)
178#define RCSR_WDR (1 << 1)
179#define RCSR_HWR (1 << 0)
180
181#define PWER_GPIO(Nb) (1 << Nb)
182#define PWER_GPIO0 PWER_GPIO (0)
183#define PWER_GPIO1 PWER_GPIO (1)
184#define PWER_GPIO2 PWER_GPIO (2)
185#define PWER_GPIO3 PWER_GPIO (3)
186#define PWER_GPIO4 PWER_GPIO (4)
187#define PWER_GPIO5 PWER_GPIO (5)
188#define PWER_GPIO6 PWER_GPIO (6)
189#define PWER_GPIO7 PWER_GPIO (7)
190#define PWER_GPIO8 PWER_GPIO (8)
191#define PWER_GPIO9 PWER_GPIO (9)
192#define PWER_GPIO10 PWER_GPIO (10)
193#define PWER_GPIO11 PWER_GPIO (11)
194#define PWER_GPIO12 PWER_GPIO (12)
195#define PWER_GPIO13 PWER_GPIO (13)
196#define PWER_GPIO14 PWER_GPIO (14)
197#define PWER_GPIO15 PWER_GPIO (15)
198#define PWER_RTC 0x80000000
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202
203#define CCCR __REG(0x41300000)
204#define CCSR __REG(0x4130000C)
205#define CKEN __REG(0x41300004)
206#define OSCC __REG(0x41300008)
207
208#define CCCR_N_MASK 0x0380
209#define CCCR_M_MASK 0x0060
210#define CCCR_L_MASK 0x001f
211
212#define CKEN_AC97CONF (31)
213#define CKEN_CAMERA (24)
214#define CKEN_SSP1 (23)
215#define CKEN_MEMC (22)
216#define CKEN_MEMSTK (21)
217#define CKEN_IM (20)
218#define CKEN_KEYPAD (19)
219#define CKEN_USIM (18)
220#define CKEN_MSL (17)
221#define CKEN_LCD (16)
222#define CKEN_PWRI2C (15)
223#define CKEN_I2C (14)
224#define CKEN_FICP (13)
225#define CKEN_MMC (12)
226#define CKEN_USB (11)
227#define CKEN_ASSP (10)
228#define CKEN_USBHOST (10)
229#define CKEN_OSTIMER (9)
230#define CKEN_NSSP (9)
231#define CKEN_I2S (8)
232#define CKEN_BTUART (7)
233#define CKEN_FFUART (6)
234#define CKEN_STUART (5)
235#define CKEN_HWUART (4)
236#define CKEN_SSP3 (4)
237#define CKEN_SSP (3)
238#define CKEN_SSP2 (3)
239#define CKEN_AC97 (2)
240#define CKEN_PWM1 (1)
241#define CKEN_PWM0 (0)
242
243#define OSCC_OON (1 << 1)
244#define OSCC_OOK (1 << 0)
245
246
247
248#define PWRMODE_IDLE 0x1
249#define PWRMODE_STANDBY 0x2
250#define PWRMODE_SLEEP 0x3
251#define PWRMODE_DEEPSLEEP 0x7
252
253#endif
254