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13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/sysdev.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/proc-fns.h>
32#include <asm/irq.h>
33
34#include <mach/reset.h>
35#include <mach/idle.h>
36
37#include <plat/cpu-freq.h>
38
39#include <mach/regs-clock.h>
40#include <plat/regs-serial.h>
41#include <mach/regs-power.h>
42#include <mach/regs-gpio.h>
43#include <mach/regs-gpioj.h>
44#include <mach/regs-dsc.h>
45#include <plat/regs-spi.h>
46#include <mach/regs-s3c2412.h>
47
48#include <plat/s3c2412.h>
49#include <plat/cpu.h>
50#include <plat/devs.h>
51#include <plat/clock.h>
52#include <plat/pm.h>
53#include <plat/pll.h>
54
55#ifndef CONFIG_CPU_S3C2412_ONLY
56void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
57
58static inline void s3c2412_init_gpio2(void)
59{
60 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
61}
62#else
63#define s3c2412_init_gpio2() do { } while(0)
64#endif
65
66
67
68static struct map_desc s3c2412_iodesc[] __initdata = {
69 IODESC_ENT(CLKPWR),
70 IODESC_ENT(TIMER),
71 IODESC_ENT(WATCHDOG),
72 {
73 .virtual = (unsigned long)S3C2412_VA_SSMC,
74 .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
75 .length = SZ_1M,
76 .type = MT_DEVICE,
77 },
78 {
79 .virtual = (unsigned long)S3C2412_VA_EBI,
80 .pfn = __phys_to_pfn(S3C2412_PA_EBI),
81 .length = SZ_1M,
82 .type = MT_DEVICE,
83 },
84};
85
86
87
88void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
89{
90 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
91
92
93 s3c_device_sdi.name = "s3c2412-sdi";
94 s3c_device_lcd.name = "s3c2412-lcd";
95 s3c_device_nand.name = "s3c2412-nand";
96
97
98
99 s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
100 s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
101
102
103 s3c_device_spi0.name = "s3c2412-spi";
104 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
105 s3c_device_spi1.name = "s3c2412-spi";
106 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
107 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
108
109}
110
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116
117
118static void s3c2412_idle(void)
119{
120 unsigned long tmp;
121
122
123
124 tmp = __raw_readl(S3C2412_PWRCFG);
125 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
126 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
127 __raw_writel(tmp, S3C2412_PWRCFG);
128
129 cpu_do_idle();
130}
131
132static void s3c2412_hard_reset(void)
133{
134
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142
143 __raw_writel(0x00, S3C2412_CLKSRC);
144 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
145
146 mdelay(1);
147}
148
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154
155void __init s3c2412_map_io(void)
156{
157
158
159 s3c2412_init_gpio2();
160
161
162
163 s3c24xx_idle = s3c2412_idle;
164
165
166
167 s3c24xx_reset_hook = s3c2412_hard_reset;
168
169
170
171 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
172}
173
174void __init_or_cpufreq s3c2412_setup_clocks(void)
175{
176 struct clk *xtal_clk;
177 unsigned long tmp;
178 unsigned long xtal;
179 unsigned long fclk;
180 unsigned long hclk;
181 unsigned long pclk;
182
183 xtal_clk = clk_get(NULL, "xtal");
184 xtal = clk_get_rate(xtal_clk);
185 clk_put(xtal_clk);
186
187
188
189
190 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
191
192 clk_mpll.rate = fclk;
193
194 tmp = __raw_readl(S3C2410_CLKDIVN);
195
196
197
198 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
199 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
200 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
201
202
203
204 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
205 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
206
207 s3c24xx_setup_clocks(fclk, hclk, pclk);
208}
209
210void __init s3c2412_init_clocks(int xtal)
211{
212
213
214
215
216 s3c24xx_register_baseclocks(xtal);
217 s3c2412_setup_clocks();
218 s3c2412_baseclk_add();
219}
220
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225
226
227struct sysdev_class s3c2412_sysclass = {
228 .name = "s3c2412-core",
229};
230
231static int __init s3c2412_core_init(void)
232{
233 return sysdev_class_register(&s3c2412_sysclass);
234}
235
236core_initcall(s3c2412_core_init);
237
238static struct sys_device s3c2412_sysdev = {
239 .cls = &s3c2412_sysclass,
240};
241
242int __init s3c2412_init(void)
243{
244 printk("S3C2412: Initialising architecture\n");
245
246 return sysdev_register(&s3c2412_sysdev);
247}
248