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15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19
20#include <mach/map.h>
21#include <mach/dma.h>
22
23#include <plat/dma-plat.h>
24#include <plat/cpu.h>
25
26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h>
34#include <plat/regs-spi.h>
35
36static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
37 [DMACH_XD0] = {
38 .name = "xdreq0",
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
40 },
41 [DMACH_XD1] = {
42 .name = "xdreq1",
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
44 },
45 [DMACH_SDI] = {
46 .name = "sdi",
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
51 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
53 },
54 [DMACH_SPI0] = {
55 .name = "spi0",
56 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
57 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
58 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
59 },
60 [DMACH_SPI1] = {
61 .name = "spi1",
62 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
63 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
65 },
66 [DMACH_UART0] = {
67 .name = "uart0",
68 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
69 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
70 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
71 },
72 [DMACH_UART1] = {
73 .name = "uart1",
74 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
75 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
77 },
78 [DMACH_UART2] = {
79 .name = "uart2",
80 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
81 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
83 },
84 [DMACH_TIMER] = {
85 .name = "timer",
86 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
87 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
88 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
89 },
90 [DMACH_I2S_IN] = {
91 .name = "i2s-sdi",
92 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
93 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
94 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
95 },
96 [DMACH_I2S_OUT] = {
97 .name = "i2s-sdo",
98 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
99 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
100 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
101 },
102 [DMACH_PCM_IN] = {
103 .name = "pcm-in",
104 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
105 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
106 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
107 },
108 [DMACH_PCM_OUT] = {
109 .name = "pcm-out",
110 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
111 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
112 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
113 },
114 [DMACH_MIC_IN] = {
115 .name = "mic-in",
116 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
117 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
118 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
119 },
120 [DMACH_USB_EP1] = {
121 .name = "usb-ep1",
122 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
123 },
124 [DMACH_USB_EP2] = {
125 .name = "usb-ep2",
126 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
127 },
128 [DMACH_USB_EP3] = {
129 .name = "usb-ep3",
130 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
131 },
132 [DMACH_USB_EP4] = {
133 .name = "usb-ep4",
134 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
135 },
136};
137
138static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
139 struct s3c24xx_dma_map *map)
140{
141 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
142}
143
144static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
145 .select = s3c2440_dma_select,
146 .dcon_mask = 7 << 24,
147 .map = s3c2440_dma_mappings,
148 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
149};
150
151static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
152 .channels = {
153 [DMACH_SDI] = {
154 .list = {
155 [0] = 3 | DMA_CH_VALID,
156 [1] = 2 | DMA_CH_VALID,
157 [2] = 1 | DMA_CH_VALID,
158 [3] = 0 | DMA_CH_VALID,
159 },
160 },
161 [DMACH_I2S_IN] = {
162 .list = {
163 [0] = 1 | DMA_CH_VALID,
164 [1] = 2 | DMA_CH_VALID,
165 },
166 },
167 [DMACH_I2S_OUT] = {
168 .list = {
169 [0] = 2 | DMA_CH_VALID,
170 [1] = 1 | DMA_CH_VALID,
171 },
172 },
173 [DMACH_PCM_IN] = {
174 .list = {
175 [0] = 2 | DMA_CH_VALID,
176 [1] = 1 | DMA_CH_VALID,
177 },
178 },
179 [DMACH_PCM_OUT] = {
180 .list = {
181 [0] = 1 | DMA_CH_VALID,
182 [1] = 3 | DMA_CH_VALID,
183 },
184 },
185 [DMACH_MIC_IN] = {
186 .list = {
187 [0] = 3 | DMA_CH_VALID,
188 [1] = 2 | DMA_CH_VALID,
189 },
190 },
191 },
192};
193
194static int __init s3c2440_dma_add(struct sys_device *sysdev)
195{
196 s3c2410_dma_init();
197 s3c24xx_dma_order_set(&s3c2440_dma_order);
198 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
199}
200
201static struct sysdev_driver s3c2440_dma_driver = {
202 .add = s3c2440_dma_add,
203};
204
205static int __init s3c2440_dma_init(void)
206{
207 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
208}
209
210arch_initcall(s3c2440_dma_init);
211
212
