LXR linux/arch/arm/mach-sa1100/irq.c

   1/*
   2 * linux/arch/arm/mach-sa1100/irq.c
   3 *
   4 * Copyright (C) 1999-2001 Nicolas Pitre
   5 *
   6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 */
  12#include <linux/init.h>
  13#include <linux/module.h>
  14#include <linux/interrupt.h>
  15#include <linux/irq.h>
  16#include <linux/ioport.h>
  17#include <linux/sysdev.h>
  18
  19#include <mach/hardware.h>
  20#include <asm/mach/irq.h>
  21
  22#include "generic.h"
  23
  24
  25/*
  26 * SA1100 GPIO edge detection for IRQs:
  27 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  28 * Use this instead of directly setting GRER/GFER.
  29 */
  30static int GPIO_IRQ_rising_edge;
  31static int GPIO_IRQ_falling_edge;
  32static int GPIO_IRQ_mask = (1 << 11) - 1;
  33
  34/*
  35 * To get the GPIO number from an IRQ number
  36 */
  37#define GPIO_11_27_IRQ(i)       ((i) - 21)
  38#define GPIO11_27_MASK(irq)     (1 << GPIO_11_27_IRQ(irq))
  39
  40static int sa1100_gpio_type(unsigned int irq, unsigned int type)
  41{
  42        unsigned int mask;
  43
  44        if (irq <= 10)
  45                mask = 1 << irq;
  46        else
  47                mask = GPIO11_27_MASK(irq);
  48
  49        if (type == IRQ_TYPE_PROBE) {
  50                if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
  51                        return 0;
  52                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  53        }
  54
  55        if (type & IRQ_TYPE_EDGE_RISING) {
  56                GPIO_IRQ_rising_edge |= mask;
  57        } else
  58                GPIO_IRQ_rising_edge &= ~mask;
  59        if (type & IRQ_TYPE_EDGE_FALLING) {
  60                GPIO_IRQ_falling_edge |= mask;
  61        } else
  62                GPIO_IRQ_falling_edge &= ~mask;
  63
  64        GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  65        GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  66
  67        return 0;
  68}
  69
  70/*
  71 * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
  72 */
  73static void sa1100_low_gpio_ack(unsigned int irq)
  74{
  75        GEDR = (1 << irq);
  76}
  77
  78static void sa1100_low_gpio_mask(unsigned int irq)
  79{
  80        ICMR &= ~(1 << irq);
  81}
  82
  83static void sa1100_low_gpio_unmask(unsigned int irq)
  84{
  85        ICMR |= 1 << irq;
  86}
  87
  88static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
  89{
  90        if (on)
  91                PWER |= 1 << irq;
  92        else
  93                PWER &= ~(1 << irq);
  94        return 0;
  95}
  96
  97static struct irq_chip sa1100_low_gpio_chip = {
  98        .name           = "GPIO-l",
  99        .ack            = sa1100_low_gpio_ack,
 100        .mask           = sa1100_low_gpio_mask,
 101        .unmask         = sa1100_low_gpio_unmask,
 102        .set_type       = sa1100_gpio_type,
 103        .set_wake       = sa1100_low_gpio_wake,
 104};
 105
 106/*
 107 * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 108 * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 109 * and call the handler.
 110 */
 111static void
 112sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 113{
 114        unsigned int mask;
 115
 116        mask = GEDR & 0xfffff800;
 117        do {
 118                /*
 119                 * clear down all currently active IRQ sources.
 120                 * We will be processing them all.
 121                 */
 122                GEDR = mask;
 123
 124                irq = IRQ_GPIO11;
 125                mask >>= 11;
 126                do {
 127                        if (mask & 1)
 128                                generic_handle_irq(irq);
 129                        mask >>= 1;
 130                        irq++;
 131                } while (mask);
 132
 133                mask = GEDR & 0xfffff800;
 134        } while (mask);
 135}
 136
 137/*
 138 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 139 * In addition, the IRQs are all collected up into one bit in the
 140 * interrupt controller registers.
 141 */
 142static void sa1100_high_gpio_ack(unsigned int irq)
 143{
 144        unsigned int mask = GPIO11_27_MASK(irq);
 145
 146        GEDR = mask;
 147}
 148
 149static void sa1100_high_gpio_mask(unsigned int irq)
 150{
 151        unsigned int mask = GPIO11_27_MASK(irq);
 152
 153        GPIO_IRQ_mask &= ~mask;
 154
 155        GRER &= ~mask;
 156        GFER &= ~mask;
 157}
 158
 159static void sa1100_high_gpio_unmask(unsigned int irq)
 160{
 161        unsigned int mask = GPIO11_27_MASK(irq);
 162
 163        GPIO_IRQ_mask |= mask;
 164
 165        GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 166        GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 167}
 168
 169static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
 170{
 171        if (on)
 172                PWER |= GPIO11_27_MASK(irq);
 173        else
 174                PWER &= ~GPIO11_27_MASK(irq);
 175        return 0;
 176}
 177
 178static struct irq_chip sa1100_high_gpio_chip = {
 179        .name           = "GPIO-h",
 180        .ack            = sa1100_high_gpio_ack,
 181        .mask           = sa1100_high_gpio_mask,
 182        .unmask         = sa1100_high_gpio_unmask,
 183        .set_type       = sa1100_gpio_type,
 184        .set_wake       = sa1100_high_gpio_wake,
 185};
 186
 187/*
 188 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 189 * this is for internal IRQs i.e. from 11 to 31.
 190 */
 191static void sa1100_mask_irq(unsigned int irq)
 192{
 193        ICMR &= ~(1 << irq);
 194}
 195
 196static void sa1100_unmask_irq(unsigned int irq)
 197{
 198        ICMR |= (1 << irq);
 199}
 200
 201/*
 202 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 203 */
 204static int sa1100_set_wake(unsigned int irq, unsigned int on)
 205{
 206        if (irq == IRQ_RTCAlrm) {
 207                if (on)
 208                        PWER |= PWER_RTC;
 209                else
 210                        PWER &= ~PWER_RTC;
 211                return 0;
 212        }
 213        return -EINVAL;
 214}
 215
 216static struct irq_chip sa1100_normal_chip = {
 217        .name           = "SC",
 218        .ack            = sa1100_mask_irq,
 219        .mask           = sa1100_mask_irq,
 220        .unmask         = sa1100_unmask_irq,
 221        .set_wake       = sa1100_set_wake,
 222};
 223
 224static struct resource irq_resource = {
 225        .name   = "irqs",
 226        .start  = 0x90050000,
 227        .end    = 0x9005ffff,
 228};
 229
 230static struct sa1100irq_state {
 231        unsigned int    saved;
 232        unsigned int    icmr;
 233        unsigned int    iclr;
 234        unsigned int    iccr;
 235} sa1100irq_state;
 236
 237static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
 238{
 239        struct sa1100irq_state *st = &sa1100irq_state;
 240
 241        st->saved = 1;
 242        st->icmr = ICMR;
 243        st->iclr = ICLR;
 244        st->iccr = ICCR;
 245
 246        /*
 247         * Disable all GPIO-based interrupts.
 248         */
 249        ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
 250                  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
 251                  IC_GPIO1|IC_GPIO0);
 252
 253        /*
 254         * Set the appropriate edges for wakeup.
 255         */
 256        GRER = PWER & GPIO_IRQ_rising_edge;
 257        GFER = PWER & GPIO_IRQ_falling_edge;
 258        
 259        /*
 260         * Clear any pending GPIO interrupts.
 261         */
 262        GEDR = GEDR;
 263
 264        return 0;
 265}
 266
 267static int sa1100irq_resume(struct sys_device *dev)
 268{
 269        struct sa1100irq_state *st = &sa1100irq_state;
 270
 271        if (st->saved) {
 272                ICCR = st->iccr;
 273                ICLR = st->iclr;
 274
 275                GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 276                GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 277
 278                ICMR = st->icmr;
 279        }
 280        return 0;
 281}
 282
 283static struct sysdev_class sa1100irq_sysclass = {
 284        .name           = "sa11x0-irq",
 285        .suspend        = sa1100irq_suspend,
 286        .resume         = sa1100irq_resume,
 287};
 288
 289static struct sys_device sa1100irq_device = {
 290        .id             = 0,
 291        .cls            = &sa1100irq_sysclass,
 292};
 293
 294static int __init sa1100irq_init_devicefs(void)
 295{
 296        sysdev_class_register(&sa1100irq_sysclass);
 297        return sysdev_register(&sa1100irq_device);
 298}
 299
 300device_initcall(sa1100irq_init_devicefs);
 301
 302void __init sa1100_init_irq(void)
 303{
 304        unsigned int irq;
 305
 306        request_resource(&iomem_resource, &irq_resource);
 307
 308        /* disable all IRQs */
 309        ICMR = 0;
 310
 311        /* all IRQs are IRQ, not FIQ */
 312        ICLR = 0;
 313
 314        /* clear all GPIO edge detects */
 315        GFER = 0;
 316        GRER = 0;
 317        GEDR = -1;
 318
 319        /*
 320         * Whatever the doc says, this has to be set for the wait-on-irq
 321         * instruction to work... on a SA1100 rev 9 at least.
 322         */
 323        ICCR = 1;
 324
 325        for (irq = 0; irq <= 10; irq++) {
 326                set_irq_chip(irq, &sa1100_low_gpio_chip);
 327                set_irq_handler(irq, handle_edge_irq);
 328                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 329        }
 330
 331        for (irq = 12; irq <= 31; irq++) {
 332                set_irq_chip(irq, &sa1100_normal_chip);
 333                set_irq_handler(irq, handle_level_irq);
 334                set_irq_flags(irq, IRQF_VALID);
 335        }
 336
 337        for (irq = 32; irq <= 48; irq++) {
 338                set_irq_chip(irq, &sa1100_high_gpio_chip);
 339                set_irq_handler(irq, handle_edge_irq);
 340                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 341        }
 342
 343        /*
 344         * Install handler for GPIO 11-27 edge detect interrupts
 345         */
 346        set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
 347        set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 348
 349        sa1100_init_gpio();
 350}
 351