1/* 2 * 3 * arch/arm/mach-u300/include/mach/u300-regs.h 4 * 5 * 6 * Copyright (C) 2006-2009 ST-Ericsson AB 7 * License terms: GNU General Public License (GPL) version 2 8 * Basic register address definitions in physical memory and 9 * some block defintions for core devices like the timer. 10 * Author: Linus Walleij <linus.walleij@stericsson.com> 11 */ 12 13#ifndef __MACH_U300_REGS_H 14#define __MACH_U300_REGS_H 15 16/* 17 * These are the large blocks of memory allocated for I/O. 18 * the defines are used for setting up the I/O memory mapping. 19 */ 20 21/* NAND Flash CS0 */ 22#define U300_NAND_CS0_PHYS_BASE 0x80000000 23#define U300_NAND_CS0_VIRT_BASE 0xff040000 24 25/* NFIF */ 26#define U300_NAND_IF_PHYS_BASE 0x9f800000 27#define U300_NAND_IF_VIRT_BASE 0xff030000 28 29/* AHB Peripherals */ 30#define U300_AHB_PER_PHYS_BASE 0xa0000000 31#define U300_AHB_PER_VIRT_BASE 0xff010000 32 33/* FAST Peripherals */ 34#define U300_FAST_PER_PHYS_BASE 0xc0000000 35#define U300_FAST_PER_VIRT_BASE 0xff020000 36 37/* SLOW Peripherals */ 38#define U300_SLOW_PER_PHYS_BASE 0xc0010000 39#define U300_SLOW_PER_VIRT_BASE 0xff000000 40 41/* Boot ROM */ 42#define U300_BOOTROM_PHYS_BASE 0xffff0000 43#define U300_BOOTROM_VIRT_BASE 0xffff0000 44 45/* SEMI config base */ 46#ifdef CONFIG_MACH_U300_BS335 47#define U300_SEMI_CONFIG_BASE 0x2FFE0000 48#else 49#define U300_SEMI_CONFIG_BASE 0x30000000 50#endif 51 52/* 53 * All the following peripherals are specified at their PHYSICAL address, 54 * so if you need to access them (in the kernel), you MUST use the macros 55 * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST() 56 * etc. 57 */ 58 59/* 60 * AHB peripherals 61 */ 62 63/* AHB Peripherals Bridge Controller */ 64#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) 65 66/* Vectored Interrupt Controller 0, servicing 32 interrupts */ 67#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) 68#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000) 69 70/* Vectored Interrupt Controller 1, servicing 32 interrupts */ 71#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) 72#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000) 73 74/* Memory Stick Pro (MSPRO) controller */ 75#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) 76 77/* EMIF Configuration Area */ 78#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) 79 80 81/* 82 * FAST peripherals 83 */ 84 85/* FAST bridge control */ 86#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) 87 88/* MMC/SD controller */ 89#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) 90 91/* PCM I2S0 controller */ 92#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) 93 94/* PCM I2S1 controller */ 95#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) 96 97/* I2C0 controller */ 98#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) 99 100/* I2C1 controller */ 101#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) 102 103/* SPI controller */ 104#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) 105 106#ifdef CONFIG_MACH_U300_BS335 107/* Fast UART1 on U335 only */ 108#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) 109#endif 110 111/* 112 * SLOW peripherals 113 */ 114 115/* SLOW bridge control */ 116#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) 117 118/* SYSCON */ 119#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) 120#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000) 121 122/* Watchdog */ 123#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) 124 125/* UART0 */ 126#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) 127 128/* APP side special timer */ 129#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) 130#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000) 131 132/* Keypad */ 133#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) 134 135/* GPIO */ 136#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) 137 138/* RTC */ 139#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) 140 141/* Bus tracer */ 142#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) 143 144/* Event handler (hardware queue) */ 145#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) 146 147/* Genric Timer */ 148#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) 149 150/* PPM */ 151#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) 152 153 154/* 155 * REST peripherals 156 */ 157 158/* ISP (image signal processor) is only available in U335 */ 159#ifdef CONFIG_MACH_U300_BS335 160#define U300_ISP_BASE (0xA0008000) 161#endif 162 163/* DMA Controller base */ 164#define U300_DMAC_BASE (0xC0020000) 165 166/* MSL Base */ 167#define U300_MSL_BASE (0xc0022000) 168 169/* APEX Base */ 170#define U300_APEX_BASE (0xc0030000) 171 172/* Video Encoder Base */ 173#ifdef CONFIG_MACH_U300_BS335 174#define U300_VIDEOENC_BASE (0xc0080000) 175#else 176#define U300_VIDEOENC_BASE (0xc0040000) 177#endif 178 179/* XGAM Base */ 180#define U300_XGAM_BASE (0xd0000000) 181 182/* 183 * Virtual accessor macros for static devices 184 */ 185 186 187#endif 188