LXR linux/arch/arm/mm/alignment.c

   1/*
   2 *  linux/arch/arm/mm/alignment.c
   3 *
   4 *  Copyright (C) 1995  Linus Torvalds
   5 *  Modifications for ARM processor (c) 1995-2001 Russell King
   6 *  Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
   7 *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
   8 *    Copyright (C) 1996, Cygnus Software Technologies Ltd.
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 */
  14#include <linux/compiler.h>
  15#include <linux/kernel.h>
  16#include <linux/errno.h>
  17#include <linux/string.h>
  18#include <linux/proc_fs.h>
  19#include <linux/init.h>
  20#include <linux/sched.h>
  21#include <linux/uaccess.h>
  22
  23#include <asm/unaligned.h>
  24
  25#include "fault.h"
  26
  27/*
  28 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
  29 * /proc/sys/debug/alignment, modified and integrated into
  30 * Linux 2.1 by Russell King
  31 *
  32 * Speed optimisations and better fault handling by Russell King.
  33 *
  34 * *** NOTE ***
  35 * This code is not portable to processors with late data abort handling.
  36 */
  37#define CODING_BITS(i)  (i & 0x0e000000)
  38
  39#define LDST_I_BIT(i)   (i & (1 << 26))         /* Immediate constant   */
  40#define LDST_P_BIT(i)   (i & (1 << 24))         /* Preindex             */
  41#define LDST_U_BIT(i)   (i & (1 << 23))         /* Add offset           */
  42#define LDST_W_BIT(i)   (i & (1 << 21))         /* Writeback            */
  43#define LDST_L_BIT(i)   (i & (1 << 20))         /* Load                 */
  44
  45#define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
  46
  47#define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
  48#define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
  49
  50#define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
  51#define RD_BITS(i)      ((i >> 12) & 15)        /* Rd                   */
  52#define RM_BITS(i)      (i & 15)                /* Rm                   */
  53
  54#define REGMASK_BITS(i) (i & 0xffff)
  55#define OFFSET_BITS(i)  (i & 0x0fff)
  56
  57#define IS_SHIFT(i)     (i & 0x0ff0)
  58#define SHIFT_BITS(i)   ((i >> 7) & 0x1f)
  59#define SHIFT_TYPE(i)   (i & 0x60)
  60#define SHIFT_LSL       0x00
  61#define SHIFT_LSR       0x20
  62#define SHIFT_ASR       0x40
  63#define SHIFT_RORRRX    0x60
  64
  65#define BAD_INSTR       0xdeadc0de
  66
  67/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
  68#define IS_T32(hi16) \
  69        (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
  70
  71static unsigned long ai_user;
  72static unsigned long ai_sys;
  73static unsigned long ai_skipped;
  74static unsigned long ai_half;
  75static unsigned long ai_word;
  76static unsigned long ai_dword;
  77static unsigned long ai_multi;
  78static int ai_usermode;
  79
  80#define UM_WARN         (1 << 0)
  81#define UM_FIXUP        (1 << 1)
  82#define UM_SIGNAL       (1 << 2)
  83
  84#ifdef CONFIG_PROC_FS
  85static const char *usermode_action[] = {
  86        "ignored",
  87        "warn",
  88        "fixup",
  89        "fixup+warn",
  90        "signal",
  91        "signal+warn"
  92};
  93
  94static int
  95proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
  96                    void *data)
  97{
  98        char *p = page;
  99        int len;
 100
 101        p += sprintf(p, "User:\t\t%lu\n", ai_user);
 102        p += sprintf(p, "System:\t\t%lu\n", ai_sys);
 103        p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
 104        p += sprintf(p, "Half:\t\t%lu\n", ai_half);
 105        p += sprintf(p, "Word:\t\t%lu\n", ai_word);
 106        if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
 107                p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
 108        p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
 109        p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
 110                        usermode_action[ai_usermode]);
 111
 112        len = (p - page) - off;
 113        if (len < 0)
 114                len = 0;
 115
 116        *eof = (len <= count) ? 1 : 0;
 117        *start = page + off;
 118
 119        return len;
 120}
 121
 122static int proc_alignment_write(struct file *file, const char __user *buffer,
 123                                unsigned long count, void *data)
 124{
 125        char mode;
 126
 127        if (count > 0) {
 128                if (get_user(mode, buffer))
 129                        return -EFAULT;
 130                if (mode >= '0' && mode <= '5')
 131                        ai_usermode = mode - '0';
 132        }
 133        return count;
 134}
 135
 136#endif /* CONFIG_PROC_FS */
 137
 138union offset_union {
 139        unsigned long un;
 140          signed long sn;
 141};
 142
 143#define TYPE_ERROR      0
 144#define TYPE_FAULT      1
 145#define TYPE_LDST       2
 146#define TYPE_DONE       3
 147
 148#ifdef __ARMEB__
 149#define BE              1
 150#define FIRST_BYTE_16   "mov    %1, %1, ror #8\n"
 151#define FIRST_BYTE_32   "mov    %1, %1, ror #24\n"
 152#define NEXT_BYTE       "ror #24"
 153#else
 154#define BE              0
 155#define FIRST_BYTE_16
 156#define FIRST_BYTE_32
 157#define NEXT_BYTE       "lsr #8"
 158#endif
 159
 160#define __get8_unaligned_check(ins,val,addr,err)        \
 161        __asm__(                                        \
 162 ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 163 THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 164 THUMB( "       add     %2, %2, #1\n"   )               \
 165        "2:\n"                                          \
 166        "       .section .fixup,\"ax\"\n"               \
 167        "       .align  2\n"                            \
 168        "3:     mov     %0, #1\n"                       \
 169        "       b       2b\n"                           \
 170        "       .previous\n"                            \
 171        "       .section __ex_table,\"a\"\n"            \
 172        "       .align  3\n"                            \
 173        "       .long   1b, 3b\n"                       \
 174        "       .previous\n"                            \
 175        : "=r" (err), "=&r" (val), "=r" (addr)          \
 176        : "0" (err), "2" (addr))
 177
 178#define __get16_unaligned_check(ins,val,addr)                   \
 179        do {                                                    \
 180                unsigned int err = 0, v, a = addr;              \
 181                __get8_unaligned_check(ins,v,a,err);            \
 182                val =  v << ((BE) ? 8 : 0);                     \
 183                __get8_unaligned_check(ins,v,a,err);            \
 184                val |= v << ((BE) ? 0 : 8);                     \
 185                if (err)                                        \
 186                        goto fault;                             \
 187        } while (0)
 188
 189#define get16_unaligned_check(val,addr) \
 190        __get16_unaligned_check("ldrb",val,addr)
 191
 192#define get16t_unaligned_check(val,addr) \
 193        __get16_unaligned_check("ldrbt",val,addr)
 194
 195#define __get32_unaligned_check(ins,val,addr)                   \
 196        do {                                                    \
 197                unsigned int err = 0, v, a = addr;              \
 198                __get8_unaligned_check(ins,v,a,err);            \
 199                val =  v << ((BE) ? 24 :  0);                   \
 200                __get8_unaligned_check(ins,v,a,err);            \
 201                val |= v << ((BE) ? 16 :  8);                   \
 202                __get8_unaligned_check(ins,v,a,err);            \
 203                val |= v << ((BE) ?  8 : 16);                   \
 204                __get8_unaligned_check(ins,v,a,err);            \
 205                val |= v << ((BE) ?  0 : 24);                   \
 206                if (err)                                        \
 207                        goto fault;                             \
 208        } while (0)
 209
 210#define get32_unaligned_check(val,addr) \
 211        __get32_unaligned_check("ldrb",val,addr)
 212
 213#define get32t_unaligned_check(val,addr) \
 214        __get32_unaligned_check("ldrbt",val,addr)
 215
 216#define __put16_unaligned_check(ins,val,addr)                   \
 217        do {                                                    \
 218                unsigned int err = 0, v = val, a = addr;        \
 219                __asm__( FIRST_BYTE_16                          \
 220         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 221         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 222         THUMB( "       add     %2, %2, #1\n"   )               \
 223                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 224                "2:     "ins"   %1, [%2]\n"                     \
 225                "3:\n"                                          \
 226                "       .section .fixup,\"ax\"\n"               \
 227                "       .align  2\n"                            \
 228                "4:     mov     %0, #1\n"                       \
 229                "       b       3b\n"                           \
 230                "       .previous\n"                            \
 231                "       .section __ex_table,\"a\"\n"            \
 232                "       .align  3\n"                            \
 233                "       .long   1b, 4b\n"                       \
 234                "       .long   2b, 4b\n"                       \
 235                "       .previous\n"                            \
 236                : "=r" (err), "=&r" (v), "=&r" (a)              \
 237                : "0" (err), "1" (v), "2" (a));                 \
 238                if (err)                                        \
 239                        goto fault;                             \
 240        } while (0)
 241
 242#define put16_unaligned_check(val,addr)  \
 243        __put16_unaligned_check("strb",val,addr)
 244
 245#define put16t_unaligned_check(val,addr) \
 246        __put16_unaligned_check("strbt",val,addr)
 247
 248#define __put32_unaligned_check(ins,val,addr)                   \
 249        do {                                                    \
 250                unsigned int err = 0, v = val, a = addr;        \
 251                __asm__( FIRST_BYTE_32                          \
 252         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
 253         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
 254         THUMB( "       add     %2, %2, #1\n"   )               \
 255                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 256         ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
 257         THUMB( "2:     "ins"   %1, [%2]\n"     )               \
 258         THUMB( "       add     %2, %2, #1\n"   )               \
 259                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 260         ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
 261         THUMB( "3:     "ins"   %1, [%2]\n"     )               \
 262         THUMB( "       add     %2, %2, #1\n"   )               \
 263                "       mov     %1, %1, "NEXT_BYTE"\n"          \
 264                "4:     "ins"   %1, [%2]\n"                     \
 265                "5:\n"                                          \
 266                "       .section .fixup,\"ax\"\n"               \
 267                "       .align  2\n"                            \
 268                "6:     mov     %0, #1\n"                       \
 269                "       b       5b\n"                           \
 270                "       .previous\n"                            \
 271                "       .section __ex_table,\"a\"\n"            \
 272                "       .align  3\n"                            \
 273                "       .long   1b, 6b\n"                       \
 274                "       .long   2b, 6b\n"                       \
 275                "       .long   3b, 6b\n"                       \
 276                "       .long   4b, 6b\n"                       \
 277                "       .previous\n"                            \
 278                : "=r" (err), "=&r" (v), "=&r" (a)              \
 279                : "0" (err), "1" (v), "2" (a));                 \
 280                if (err)                                        \
 281                        goto fault;                             \
 282        } while (0)
 283
 284#define put32_unaligned_check(val,addr) \
 285        __put32_unaligned_check("strb", val, addr)
 286
 287#define put32t_unaligned_check(val,addr) \
 288        __put32_unaligned_check("strbt", val, addr)
 289
 290static void
 291do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
 292{
 293        if (!LDST_U_BIT(instr))
 294                offset.un = -offset.un;
 295
 296        if (!LDST_P_BIT(instr))
 297                addr += offset.un;
 298
 299        if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
 300                regs->uregs[RN_BITS(instr)] = addr;
 301}
 302
 303static int
 304do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 305{
 306        unsigned int rd = RD_BITS(instr);
 307
 308        ai_half += 1;
 309
 310        if (user_mode(regs))
 311                goto user;
 312
 313        if (LDST_L_BIT(instr)) {
 314                unsigned long val;
 315                get16_unaligned_check(val, addr);
 316
 317                /* signed half-word? */
 318                if (instr & 0x40)
 319                        val = (signed long)((signed short) val);
 320
 321                regs->uregs[rd] = val;
 322        } else
 323                put16_unaligned_check(regs->uregs[rd], addr);
 324
 325        return TYPE_LDST;
 326
 327 user:
 328        if (LDST_L_BIT(instr)) {
 329                unsigned long val;
 330                get16t_unaligned_check(val, addr);
 331
 332                /* signed half-word? */
 333                if (instr & 0x40)
 334                        val = (signed long)((signed short) val);
 335
 336                regs->uregs[rd] = val;
 337        } else
 338                put16t_unaligned_check(regs->uregs[rd], addr);
 339
 340        return TYPE_LDST;
 341
 342 fault:
 343        return TYPE_FAULT;
 344}
 345
 346static int
 347do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
 348                      struct pt_regs *regs)
 349{
 350        unsigned int rd = RD_BITS(instr);
 351        unsigned int rd2;
 352        int load;
 353
 354        if ((instr & 0xfe000000) == 0xe8000000) {
 355                /* ARMv7 Thumb-2 32-bit LDRD/STRD */
 356                rd2 = (instr >> 8) & 0xf;
 357                load = !!(LDST_L_BIT(instr));
 358        } else if (((rd & 1) == 1) || (rd == 14))
 359                goto bad;
 360        else {
 361                load = ((instr & 0xf0) == 0xd0);
 362                rd2 = rd + 1;
 363        }
 364
 365        ai_dword += 1;
 366
 367        if (user_mode(regs))
 368                goto user;
 369
 370        if (load) {
 371                unsigned long val;
 372                get32_unaligned_check(val, addr);
 373                regs->uregs[rd] = val;
 374                get32_unaligned_check(val, addr + 4);
 375                regs->uregs[rd2] = val;
 376        } else {
 377                put32_unaligned_check(regs->uregs[rd], addr);
 378                put32_unaligned_check(regs->uregs[rd2], addr + 4);
 379        }
 380
 381        return TYPE_LDST;
 382
 383 user:
 384        if (load) {
 385                unsigned long val;
 386                get32t_unaligned_check(val, addr);
 387                regs->uregs[rd] = val;
 388                get32t_unaligned_check(val, addr + 4);
 389                regs->uregs[rd2] = val;
 390        } else {
 391                put32t_unaligned_check(regs->uregs[rd], addr);
 392                put32t_unaligned_check(regs->uregs[rd2], addr + 4);
 393        }
 394
 395        return TYPE_LDST;
 396 bad:
 397        return TYPE_ERROR;
 398 fault:
 399        return TYPE_FAULT;
 400}
 401
 402static int
 403do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 404{
 405        unsigned int rd = RD_BITS(instr);
 406
 407        ai_word += 1;
 408
 409        if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
 410                goto trans;
 411
 412        if (LDST_L_BIT(instr)) {
 413                unsigned int val;
 414                get32_unaligned_check(val, addr);
 415                regs->uregs[rd] = val;
 416        } else
 417                put32_unaligned_check(regs->uregs[rd], addr);
 418        return TYPE_LDST;
 419
 420 trans:
 421        if (LDST_L_BIT(instr)) {
 422                unsigned int val;
 423                get32t_unaligned_check(val, addr);
 424                regs->uregs[rd] = val;
 425        } else
 426                put32t_unaligned_check(regs->uregs[rd], addr);
 427        return TYPE_LDST;
 428
 429 fault:
 430        return TYPE_FAULT;
 431}
 432
 433/*
 434 * LDM/STM alignment handler.
 435 *
 436 * There are 4 variants of this instruction:
 437 *
 438 * B = rn pointer before instruction, A = rn pointer after instruction
 439 *              ------ increasing address ----->
 440 *              |    | r0 | r1 | ... | rx |    |
 441 * PU = 01             B                    A
 442 * PU = 11        B                    A
 443 * PU = 00        A                    B
 444 * PU = 10             A                    B
 445 */
 446static int
 447do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
 448{
 449        unsigned int rd, rn, correction, nr_regs, regbits;
 450        unsigned long eaddr, newaddr;
 451
 452        if (LDM_S_BIT(instr))
 453                goto bad;
 454
 455        correction = 4; /* processor implementation defined */
 456        regs->ARM_pc += correction;
 457
 458        ai_multi += 1;
 459
 460        /* count the number of registers in the mask to be transferred */
 461        nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
 462
 463        rn = RN_BITS(instr);
 464        newaddr = eaddr = regs->uregs[rn];
 465
 466        if (!LDST_U_BIT(instr))
 467                nr_regs = -nr_regs;
 468        newaddr += nr_regs;
 469        if (!LDST_U_BIT(instr))
 470                eaddr = newaddr;
 471
 472        if (LDST_P_EQ_U(instr)) /* U = P */
 473                eaddr += 4;
 474
 475        /*
 476         * For alignment faults on the ARM922T/ARM920T the MMU  makes
 477         * the FSR (and hence addr) equal to the updated base address
 478         * of the multiple access rather than the restored value.
 479         * Switch this message off if we've got a ARM92[02], otherwise
 480         * [ls]dm alignment faults are noisy!
 481         */
 482#if !(defined CONFIG_CPU_ARM922T)  && !(defined CONFIG_CPU_ARM920T)
 483        /*
 484         * This is a "hint" - we already have eaddr worked out by the
 485         * processor for us.
 486         */
 487        if (addr != eaddr) {
 488                printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
 489                        "addr = %08lx, eaddr = %08lx\n",
 490                         instruction_pointer(regs), instr, addr, eaddr);
 491                show_regs(regs);
 492        }
 493#endif
 494
 495        if (user_mode(regs)) {
 496                for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 497                     regbits >>= 1, rd += 1)
 498                        if (regbits & 1) {
 499                                if (LDST_L_BIT(instr)) {
 500                                        unsigned int val;
 501                                        get32t_unaligned_check(val, eaddr);
 502                                        regs->uregs[rd] = val;
 503                                } else
 504                                        put32t_unaligned_check(regs->uregs[rd], eaddr);
 505                                eaddr += 4;
 506                        }
 507        } else {
 508                for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
 509                     regbits >>= 1, rd += 1)
 510                        if (regbits & 1) {
 511                                if (LDST_L_BIT(instr)) {
 512                                        unsigned int val;
 513                                        get32_unaligned_check(val, eaddr);
 514                                        regs->uregs[rd] = val;
 515                                } else
 516                                        put32_unaligned_check(regs->uregs[rd], eaddr);
 517                                eaddr += 4;
 518                        }
 519        }
 520
 521        if (LDST_W_BIT(instr))
 522                regs->uregs[rn] = newaddr;
 523        if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
 524                regs->ARM_pc -= correction;
 525        return TYPE_DONE;
 526
 527fault:
 528        regs->ARM_pc -= correction;
 529        return TYPE_FAULT;
 530
 531bad:
 532        printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
 533        return TYPE_ERROR;
 534}
 535
 536/*
 537 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
 538 * we can reuse ARM userland alignment fault fixups for Thumb.
 539 *
 540 * This implementation was initially based on the algorithm found in
 541 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
 542 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
 543 *
 544 * NOTES:
 545 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
 546 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
 547 *    decode, we return 0xdeadc0de. This should never happen under normal
 548 *    circumstances but if it does, we've got other problems to deal with
 549 *    elsewhere and we obviously can't fix those problems here.
 550 */
 551
 552static unsigned long
 553thumb2arm(u16 tinstr)
 554{
 555        u32 L = (tinstr & (1<<11)) >> 11;
 556
 557        switch ((tinstr & 0xf800) >> 11) {
 558        /* 6.5.1 Format 1: */
 559        case 0x6000 >> 11:                              /* 7.1.52 STR(1) */
 560        case 0x6800 >> 11:                              /* 7.1.26 LDR(1) */
 561        case 0x7000 >> 11:                              /* 7.1.55 STRB(1) */
 562        case 0x7800 >> 11:                              /* 7.1.30 LDRB(1) */
 563                return 0xe5800000 |
 564                        ((tinstr & (1<<12)) << (22-12)) |       /* fixup */
 565                        (L<<20) |                               /* L==1? */
 566                        ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 567                        ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 568                        ((tinstr & (31<<6)) >>                  /* immed_5 */
 569                                (6 - ((tinstr & (1<<12)) ? 0 : 2)));
 570        case 0x8000 >> 11:                              /* 7.1.57 STRH(1) */
 571        case 0x8800 >> 11:                              /* 7.1.32 LDRH(1) */
 572                return 0xe1c000b0 |
 573                        (L<<20) |                               /* L==1? */
 574                        ((tinstr & (7<<0)) << (12-0)) |         /* Rd */
 575                        ((tinstr & (7<<3)) << (16-3)) |         /* Rn */
 576                        ((tinstr & (7<<6)) >> (6-1)) |   /* immed_5[2:0] */
 577                        ((tinstr & (3<<9)) >> (9-8));    /* immed_5[4:3] */
 578
 579        /* 6.5.1 Format 2: */
 580        case 0x5000 >> 11:
 581        case 0x5800 >> 11:
 582                {
 583                        static const u32 subset[8] = {
 584                                0xe7800000,             /* 7.1.53 STR(2) */
 585                                0xe18000b0,             /* 7.1.58 STRH(2) */
 586                                0xe7c00000,             /* 7.1.56 STRB(2) */
 587                                0xe19000d0,             /* 7.1.34 LDRSB */
 588                                0xe7900000,             /* 7.1.27 LDR(2) */
 589                                0xe19000b0,             /* 7.1.33 LDRH(2) */
 590                                0xe7d00000,             /* 7.1.31 LDRB(2) */
 591                                0xe19000f0              /* 7.1.35 LDRSH */
 592                        };
 593                        return subset[(tinstr & (7<<9)) >> 9] |
 594                            ((tinstr & (7<<0)) << (12-0)) |     /* Rd */
 595                            ((tinstr & (7<<3)) << (16-3)) |     /* Rn */
 596                            ((tinstr & (7<<6)) >> (6-0));       /* Rm */
 597                }
 598
 599        /* 6.5.1 Format 3: */
 600        case 0x4800 >> 11:                              /* 7.1.28 LDR(3) */
 601                /* NOTE: This case is not technically possible. We're
 602                 *       loading 32-bit memory data via PC relative
 603                 *       addressing mode. So we can and should eliminate
 604                 *       this case. But I'll leave it here for now.
 605                 */
 606                return 0xe59f0000 |
 607                    ((tinstr & (7<<8)) << (12-8)) |             /* Rd */
 608                    ((tinstr & 255) << (2-0));                  /* immed_8 */
 609
 610        /* 6.5.1 Format 4: */
 611        case 0x9000 >> 11:                              /* 7.1.54 STR(3) */
 612        case 0x9800 >> 11:                              /* 7.1.29 LDR(4) */
 613                return 0xe58d0000 |
 614                        (L<<20) |                               /* L==1? */
 615                        ((tinstr & (7<<8)) << (12-8)) |         /* Rd */
 616                        ((tinstr & 255) << 2);                  /* immed_8 */
 617
 618        /* 6.6.1 Format 1: */
 619        case 0xc000 >> 11:                              /* 7.1.51 STMIA */
 620        case 0xc800 >> 11:                              /* 7.1.25 LDMIA */
 621                {
 622                        u32 Rn = (tinstr & (7<<8)) >> 8;
 623                        u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
 624
 625                        return 0xe8800000 | W | (L<<20) | (Rn<<16) |
 626                                (tinstr&255);
 627                }
 628
 629        /* 6.6.1 Format 2: */
 630        case 0xb000 >> 11:                              /* 7.1.48 PUSH */
 631        case 0xb800 >> 11:                              /* 7.1.47 POP */
 632                if ((tinstr & (3 << 9)) == 0x0400) {
 633                        static const u32 subset[4] = {
 634                                0xe92d0000,     /* STMDB sp!,{registers} */
 635                                0xe92d4000,     /* STMDB sp!,{registers,lr} */
 636                                0xe8bd0000,     /* LDMIA sp!,{registers} */
 637                                0xe8bd8000      /* LDMIA sp!,{registers,pc} */
 638                        };
 639                        return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
 640                            (tinstr & 255);             /* register_list */
 641                }
 642                /* Else fall through for illegal instruction case */
 643
 644        default:
 645                return BAD_INSTR;
 646        }
 647}
 648
 649/*
 650 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
 651 * handlable by ARM alignment handler, also find the corresponding handler,
 652 * so that we can reuse ARM userland alignment fault fixups for Thumb.
 653 *
 654 * @pinstr: original Thumb-2 instruction; returns new handlable instruction
 655 * @regs: register context.
 656 * @poffset: return offset from faulted addr for later writeback
 657 *
 658 * NOTES:
 659 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
 660 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
 661 */
 662static void *
 663do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
 664                            union offset_union *poffset)
 665{
 666        unsigned long instr = *pinstr;
 667        u16 tinst1 = (instr >> 16) & 0xffff;
 668        u16 tinst2 = instr & 0xffff;
 669        poffset->un = 0;
 670
 671        switch (tinst1 & 0xffe0) {
 672        /* A6.3.5 Load/Store multiple */
 673        case 0xe880:            /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
 674        case 0xe8a0:            /* ...above writeback version */
 675        case 0xe900:            /* STMDB/STMFD, LDMDB/LDMEA */
 676        case 0xe920:            /* ...above writeback version */
 677                /* no need offset decision since handler calculates it */
 678                return do_alignment_ldmstm;
 679
 680        case 0xf840:            /* POP/PUSH T3 (single register) */
 681                if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
 682                        u32 L = !!(LDST_L_BIT(instr));
 683                        const u32 subset[2] = {
 684                                0xe92d0000,     /* STMDB sp!,{registers} */
 685                                0xe8bd0000,     /* LDMIA sp!,{registers} */
 686                        };
 687                        *pinstr = subset[L] | (1<<RD_BITS(instr));
 688                        return do_alignment_ldmstm;
 689                }
 690                /* Else fall through for illegal instruction case */
 691                break;
 692
 693        /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
 694        case 0xe860:
 695        case 0xe960:
 696        case 0xe8e0:
 697        case 0xe9e0:
 698                poffset->un = (tinst2 & 0xff) << 2;
 699        case 0xe940:
 700        case 0xe9c0:
 701                return do_alignment_ldrdstrd;
 702
 703        /*
 704         * No need to handle load/store instructions up to word size
 705         * since ARMv6 and later CPUs can perform unaligned accesses.
 706         */
 707        default:
 708                break;
 709        }
 710        return NULL;
 711}
 712
 713static int
 714do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 715{
 716        union offset_union offset;
 717        unsigned long instr = 0, instrptr;
 718        int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
 719        unsigned int type;
 720        mm_segment_t fs;
 721        unsigned int fault;
 722        u16 tinstr = 0;
 723        int isize = 4;
 724        int thumb2_32b = 0;
 725
 726        instrptr = instruction_pointer(regs);
 727
 728        fs = get_fs();
 729        set_fs(KERNEL_DS);
 730        if (thumb_mode(regs)) {
 731                fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
 732                if (!fault) {
 733                        if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
 734                            IS_T32(tinstr)) {
 735                                /* Thumb-2 32-bit */
 736                                u16 tinst2 = 0;
 737                                fault = __get_user(tinst2, (u16 *)(instrptr+2));
 738                                instr = (tinstr << 16) | tinst2;
 739                                thumb2_32b = 1;
 740                        } else {
 741                                isize = 2;
 742                                instr = thumb2arm(tinstr);
 743                        }
 744                }
 745        } else
 746                fault = __get_user(instr, (u32 *)instrptr);
 747        set_fs(fs);
 748
 749        if (fault) {
 750                type = TYPE_FAULT;
 751                goto bad_or_fault;
 752        }
 753
 754        if (user_mode(regs))
 755                goto user;
 756
 757        ai_sys += 1;
 758
 759 fixup:
 760
 761        regs->ARM_pc += isize;
 762
 763        switch (CODING_BITS(instr)) {
 764        case 0x00000000:        /* 3.13.4 load/store instruction extensions */
 765                if (LDSTHD_I_BIT(instr))
 766                        offset.un = (instr & 0xf00) >> 4 | (instr & 15);
 767                else
 768                        offset.un = regs->uregs[RM_BITS(instr)];
 769
 770                if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
 771                    (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
 772                        handler = do_alignment_ldrhstrh;
 773                else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
 774                         (instr & 0x001000f0) == 0x000000f0)   /* STRD */
 775                        handler = do_alignment_ldrdstrd;
 776                else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
 777                        goto swp;
 778                else
 779                        goto bad;
 780                break;
 781
 782        case 0x04000000:        /* ldr or str immediate */
 783                offset.un = OFFSET_BITS(instr);
 784                handler = do_alignment_ldrstr;
 785                break;
 786
 787        case 0x06000000:        /* ldr or str register */
 788                offset.un = regs->uregs[RM_BITS(instr)];
 789
 790                if (IS_SHIFT(instr)) {
 791                        unsigned int shiftval = SHIFT_BITS(instr);
 792
 793                        switch(SHIFT_TYPE(instr)) {
 794                        case SHIFT_LSL:
 795                                offset.un <<= shiftval;
 796                                break;
 797
 798                        case SHIFT_LSR:
 799                                offset.un >>= shiftval;
 800                                break;
 801
 802                        case SHIFT_ASR:
 803                                offset.sn >>= shiftval;
 804                                break;
 805
 806                        case SHIFT_RORRRX:
 807                                if (shiftval == 0) {
 808                                        offset.un >>= 1;
 809                                        if (regs->ARM_cpsr & PSR_C_BIT)
 810                                                offset.un |= 1 << 31;
 811                                } else
 812                                        offset.un = offset.un >> shiftval |
 813                                                          offset.un << (32 - shiftval);
 814                                break;
 815                        }
 816                }
 817                handler = do_alignment_ldrstr;
 818                break;
 819
 820        case 0x08000000:        /* ldm or stm, or thumb-2 32bit instruction */
 821                if (thumb2_32b)
 822                        handler = do_alignment_t32_to_handler(&instr, regs, &offset);
 823                else
 824                        handler = do_alignment_ldmstm;
 825                break;
 826
 827        default:
 828                goto bad;
 829        }
 830
 831        if (!handler)
 832                goto bad;
 833        type = handler(addr, instr, regs);
 834
 835        if (type == TYPE_ERROR || type == TYPE_FAULT) {
 836                regs->ARM_pc -= isize;
 837                goto bad_or_fault;
 838        }
 839
 840        if (type == TYPE_LDST)
 841                do_alignment_finish_ldst(addr, instr, regs, offset);
 842
 843        return 0;
 844
 845 bad_or_fault:
 846        if (type == TYPE_ERROR)
 847                goto bad;
 848        /*
 849         * We got a fault - fix it up, or die.
 850         */
 851        do_bad_area(addr, fsr, regs);
 852        return 0;
 853
 854 swp:
 855        printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
 856
 857 bad:
 858        /*
 859         * Oops, we didn't handle the instruction.
 860         */
 861        printk(KERN_ERR "Alignment trap: not handling instruction "
 862                "%0*lx at [<%08lx>]\n",
 863                isize << 1,
 864                isize == 2 ? tinstr : instr, instrptr);
 865        ai_skipped += 1;
 866        return 1;
 867
 868 user:
 869        ai_user += 1;
 870
 871        if (ai_usermode & UM_WARN)
 872                printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
 873                       "Address=0x%08lx FSR 0x%03x\n", current->comm,
 874                        task_pid_nr(current), instrptr,
 875                        isize << 1,
 876                        isize == 2 ? tinstr : instr,
 877                        addr, fsr);
 878
 879        if (ai_usermode & UM_FIXUP)
 880                goto fixup;
 881
 882        if (ai_usermode & UM_SIGNAL)
 883                force_sig(SIGBUS, current);
 884        else
 885                set_cr(cr_no_alignment);
 886
 887        return 0;
 888}
 889
 890/*
 891 * This needs to be done after sysctl_init, otherwise sys/ will be
 892 * overwritten.  Actually, this shouldn't be in sys/ at all since
 893 * it isn't a sysctl, and it doesn't contain sysctl information.
 894 * We now locate it in /proc/cpu/alignment instead.
 895 */
 896static int __init alignment_init(void)
 897{
 898#ifdef CONFIG_PROC_FS
 899        struct proc_dir_entry *res;
 900
 901        res = proc_mkdir("cpu", NULL);
 902        if (!res)
 903                return -ENOMEM;
 904
 905        res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
 906        if (!res)
 907                return -ENOMEM;
 908
 909        res->read_proc = proc_alignment_read;
 910        res->write_proc = proc_alignment_write;
 911#endif
 912
 913        /*
 914         * ARMv6 and later CPUs can perform unaligned accesses for
 915         * most single load and store instructions up to word size.
 916         * LDM, STM, LDRD and STRD still need to be handled.
 917         *
 918         * Ignoring the alignment fault is not an option on these
 919         * CPUs since we spin re-faulting the instruction without
 920         * making any progress.
 921         */
 922        if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) {
 923                cr_alignment &= ~CR_A;
 924                cr_no_alignment &= ~CR_A;
 925                set_cr(cr_alignment);
 926                ai_usermode = UM_FIXUP;
 927        }
 928
 929        hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
 930        hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
 931
 932        return 0;
 933}
 934
 935fs_initcall(alignment_init);
 936