1/* 2 * arch/arm/plat-omap/include/mach/control.h 3 * 4 * OMAP2/3/4 System Control Module definitions 5 * 6 * Copyright (C) 2007-2009 Texas Instruments, Inc. 7 * Copyright (C) 2007-2008 Nokia Corporation 8 * 9 * Written by Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation. 14 */ 15 16#ifndef __ASM_ARCH_CONTROL_H 17#define __ASM_ARCH_CONTROL_H 18 19#include <mach/io.h> 20 21#ifndef __ASSEMBLY__ 22#define OMAP242X_CTRL_REGADDR(reg) \ 23 OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 24#define OMAP243X_CTRL_REGADDR(reg) \ 25 OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 26#define OMAP343X_CTRL_REGADDR(reg) \ 27 OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 28#else 29#define OMAP242X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 30#define OMAP243X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 31#define OMAP343X_CTRL_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 32#endif /* __ASSEMBLY__ */ 33 34/* 35 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 36 * OMAP24XX and OMAP34XX. 37 */ 38 39/* Control submodule offsets */ 40 41#define OMAP2_CONTROL_INTERFACE 0x000 42#define OMAP2_CONTROL_PADCONFS 0x030 43#define OMAP2_CONTROL_GENERAL 0x270 44#define OMAP343X_CONTROL_MEM_WKUP 0x600 45#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 46#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 47 48/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ 49 50#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) 51 52/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ 53#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) 54#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) 55#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) 56#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) 57#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) 58#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) 59#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) 60#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) 61#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) 62#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) 63#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) 64#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) 65 66/* 242x-only CONTROL_GENERAL register offsets */ 67#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ 68#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) 69 70/* 243x-only CONTROL_GENERAL register offsets */ 71/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ 72#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) 73#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) 74#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 75#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 76#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) 77#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) 78 79/* 24xx-only CONTROL_GENERAL register offsets */ 80#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) 81#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) 82#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) 83#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) 84#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) 85#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) 86#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) 87#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) 88#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) 89#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) 90#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) 91#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 92#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 93#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) 94#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) 95#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) 96#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) 97#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) 98#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) 99#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) 100#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) 101#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) 102#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) 103#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) 104#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) 105#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) 106#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) 107#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) 108#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) 109#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 110#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 111 112/* 34xx-only CONTROL_GENERAL register offsets */ 113#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 114#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 115#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) 116#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) 117#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) 118#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) 119#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) 120#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) 121#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) 122#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) 123#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) 124#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) 125#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) 126#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) 127#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) 128#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) 129#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) 130#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) 131#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) 132#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) 133#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) 134#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) 135#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) 136#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) 137#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) 138#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) 139#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) 140#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) 141#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 142#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 143#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 144#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) 145#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) 146 147/* 34xx D2D idle-related pins, handled by PM core */ 148#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 149#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 150 151/* 152 * REVISIT: This list of registers is not comprehensive - there are more 153 * that should be added. 154 */ 155 156/* 157 * Control module register bit defines - these should eventually go into 158 * their own regbits file. Some of these will be complicated, depending 159 * on the device type (general-purpose, emulator, test, secure, bad, other) 160 * and the security mode (secure, non-secure, don't care) 161 */ 162/* CONTROL_DEVCONF0 bits */ 163#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ 164#define OMAP24XX_USBSTANDBYCTRL (1 << 15) 165#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) 166#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) 167 168/* CONTROL_DEVCONF1 bits */ 169#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) 170#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ 171#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ 172#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ 173#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ 174 175/* CONTROL_STATUS bits */ 176#define OMAP2_DEVICETYPE_MASK (0x7 << 8) 177#define OMAP2_SYSBOOT_5_MASK (1 << 5) 178#define OMAP2_SYSBOOT_4_MASK (1 << 4) 179#define OMAP2_SYSBOOT_3_MASK (1 << 3) 180#define OMAP2_SYSBOOT_2_MASK (1 << 2) 181#define OMAP2_SYSBOOT_1_MASK (1 << 1) 182#define OMAP2_SYSBOOT_0_MASK (1 << 0) 183 184/* CONTROL_PBIAS_LITE bits */ 185#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) 186#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) 187#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) 188#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) 189#define OMAP343X_PBIASLITEVMODE1 (1 << 8) 190#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) 191#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) 192#define OMAP2_PBIASSPEEDCTRL0 (1 << 2) 193#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 194#define OMAP2_PBIASLITEVMODE0 (1 << 0) 195 196/* CONTROL_IVA2_BOOTMOD bits */ 197#define OMAP3_IVA2_BOOTMOD_SHIFT 0 198#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) 199#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) 200 201/* CONTROL_PADCONF_X bits */ 202#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) 203#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) 204 205#ifndef __ASSEMBLY__ 206#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ 207 defined(CONFIG_ARCH_OMAP4) 208extern void __iomem *omap_ctrl_base_get(void); 209extern u8 omap_ctrl_readb(u16 offset); 210extern u16 omap_ctrl_readw(u16 offset); 211extern u32 omap_ctrl_readl(u16 offset); 212extern void omap_ctrl_writeb(u8 val, u16 offset); 213extern void omap_ctrl_writew(u16 val, u16 offset); 214extern void omap_ctrl_writel(u32 val, u16 offset); 215#else 216#define omap_ctrl_base_get() 0 217#define omap_ctrl_readb(x) 0 218#define omap_ctrl_readw(x) 0 219#define omap_ctrl_readl(x) 0 220#define omap_ctrl_writeb(x, y) WARN_ON(1) 221#define omap_ctrl_writew(x, y) WARN_ON(1) 222#define omap_ctrl_writel(x, y) WARN_ON(1) 223#endif 224#endif /* __ASSEMBLY__ */ 225 226#endif /* __ASM_ARCH_CONTROL_H */ 227 228