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11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/bitops.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19
20static DEFINE_SPINLOCK(gpio_lock);
21static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
22static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
23
24static inline void __set_direction(unsigned pin, int input)
25{
26 u32 u;
27
28 u = readl(GPIO_IO_CONF(pin));
29 if (input)
30 u |= 1 << (pin & 31);
31 else
32 u &= ~(1 << (pin & 31));
33 writel(u, GPIO_IO_CONF(pin));
34}
35
36static void __set_level(unsigned pin, int high)
37{
38 u32 u;
39
40 u = readl(GPIO_OUT(pin));
41 if (high)
42 u |= 1 << (pin & 31);
43 else
44 u &= ~(1 << (pin & 31));
45 writel(u, GPIO_OUT(pin));
46}
47
48static inline void __set_blinking(unsigned pin, int blink)
49{
50 u32 u;
51
52 u = readl(GPIO_BLINK_EN(pin));
53 if (blink)
54 u |= 1 << (pin & 31);
55 else
56 u &= ~(1 << (pin & 31));
57 writel(u, GPIO_BLINK_EN(pin));
58}
59
60static inline int orion_gpio_is_valid(unsigned pin, int mode)
61{
62 if (pin < GPIO_MAX) {
63 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
64 goto err_out;
65 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
66 goto err_out;
67 return true;
68 }
69
70err_out:
71 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
72 return false;
73}
74
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76
77
78static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
79{
80 unsigned long flags;
81
82 if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK))
83 return -EINVAL;
84
85 spin_lock_irqsave(&gpio_lock, flags);
86
87
88 __set_direction(pin, 1);
89
90 spin_unlock_irqrestore(&gpio_lock, flags);
91
92 return 0;
93}
94
95static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin)
96{
97 int val;
98
99 if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
100 val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
101 else
102 val = readl(GPIO_OUT(pin));
103
104 return (val >> (pin & 31)) & 1;
105}
106
107static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
108 int value)
109{
110 unsigned long flags;
111
112 if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
113 return -EINVAL;
114
115 spin_lock_irqsave(&gpio_lock, flags);
116
117
118 __set_blinking(pin, 0);
119
120
121 __set_level(pin, value);
122
123
124 __set_direction(pin, 0);
125
126 spin_unlock_irqrestore(&gpio_lock, flags);
127
128 return 0;
129}
130
131static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin,
132 int value)
133{
134 unsigned long flags;
135
136 spin_lock_irqsave(&gpio_lock, flags);
137
138
139 __set_level(pin, value);
140
141 spin_unlock_irqrestore(&gpio_lock, flags);
142}
143
144static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
145{
146 if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) ||
147 orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
148 return 0;
149 return -EINVAL;
150}
151
152static struct gpio_chip orion_gpiochip = {
153 .label = "orion_gpio",
154 .direction_input = orion_gpio_direction_input,
155 .get = orion_gpio_get_value,
156 .direction_output = orion_gpio_direction_output,
157 .set = orion_gpio_set_value,
158 .request = orion_gpio_request,
159 .base = 0,
160 .ngpio = GPIO_MAX,
161 .can_sleep = 0,
162};
163
164void __init orion_gpio_init(void)
165{
166 gpiochip_add(&orion_gpiochip);
167}
168
169
170
171
172void __init orion_gpio_set_unused(unsigned pin)
173{
174
175 __set_level(pin, 0);
176 __set_direction(pin, 0);
177}
178
179void __init orion_gpio_set_valid(unsigned pin, int mode)
180{
181 if (mode == 1)
182 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
183 if (mode & GPIO_INPUT_OK)
184 __set_bit(pin, gpio_valid_input);
185 else
186 __clear_bit(pin, gpio_valid_input);
187 if (mode & GPIO_OUTPUT_OK)
188 __set_bit(pin, gpio_valid_output);
189 else
190 __clear_bit(pin, gpio_valid_output);
191}
192
193void orion_gpio_set_blink(unsigned pin, int blink)
194{
195 unsigned long flags;
196
197 spin_lock_irqsave(&gpio_lock, flags);
198
199
200 __set_level(pin, 0);
201
202
203 __set_blinking(pin, blink);
204
205 spin_unlock_irqrestore(&gpio_lock, flags);
206}
207EXPORT_SYMBOL(orion_gpio_set_blink);
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236static void gpio_irq_ack(u32 irq)
237{
238 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
239 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
240 int pin = irq_to_gpio(irq);
241 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
242 }
243}
244
245static void gpio_irq_mask(u32 irq)
246{
247 int pin = irq_to_gpio(irq);
248 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
249 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
250 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
251 u32 u = readl(reg);
252 u &= ~(1 << (pin & 31));
253 writel(u, reg);
254}
255
256static void gpio_irq_unmask(u32 irq)
257{
258 int pin = irq_to_gpio(irq);
259 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
260 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
261 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
262 u32 u = readl(reg);
263 u |= 1 << (pin & 31);
264 writel(u, reg);
265}
266
267static int gpio_irq_set_type(u32 irq, u32 type)
268{
269 int pin = irq_to_gpio(irq);
270 struct irq_desc *desc;
271 u32 u;
272
273 u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
274 if (!u) {
275 printk(KERN_ERR "orion gpio_irq_set_type failed "
276 "(irq %d, pin %d).\n", irq, pin);
277 return -EINVAL;
278 }
279
280 desc = irq_desc + irq;
281
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284
285 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
286 desc->handle_irq = handle_edge_irq;
287 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
288 desc->handle_irq = handle_level_irq;
289 } else {
290 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
291 return -EINVAL;
292 }
293
294
295
296
297 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
298 u = readl(GPIO_IN_POL(pin));
299 u &= ~(1 << (pin & 31));
300 writel(u, GPIO_IN_POL(pin));
301 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
302 u = readl(GPIO_IN_POL(pin));
303 u |= 1 << (pin & 31);
304 writel(u, GPIO_IN_POL(pin));
305 } else if (type == IRQ_TYPE_EDGE_BOTH) {
306 u32 v;
307
308 v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
309
310
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313 u = readl(GPIO_IN_POL(pin));
314 if (v & (1 << (pin & 31)))
315 u |= 1 << (pin & 31);
316 else
317 u &= ~(1 << (pin & 31));
318 writel(u, GPIO_IN_POL(pin));
319 }
320
321 desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
322
323 return 0;
324}
325
326struct irq_chip orion_gpio_irq_chip = {
327 .name = "orion_gpio_irq",
328 .ack = gpio_irq_ack,
329 .mask = gpio_irq_mask,
330 .unmask = gpio_irq_unmask,
331 .set_type = gpio_irq_set_type,
332};
333
334void orion_gpio_irq_handler(int pinoff)
335{
336 u32 cause;
337 int pin;
338
339 cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
340 cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
341
342 for (pin = pinoff; pin < pinoff + 8; pin++) {
343 int irq = gpio_to_irq(pin);
344 struct irq_desc *desc = irq_desc + irq;
345
346 if (!(cause & (1 << (pin & 31))))
347 continue;
348
349 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
350
351 u32 polarity;
352
353 polarity = readl(GPIO_IN_POL(pin));
354 polarity ^= 1 << (pin & 31);
355 writel(polarity, GPIO_IN_POL(pin));
356 }
357 desc_handle_irq(irq, desc);
358 }
359}
360