1#ifndef __PLAT_GPIO_H 2#define __PLAT_GPIO_H 3 4/* 5 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 6 * one set of registers. The register offsets are organized below: 7 * 8 * GPLR GPDR GPSR GPCR GRER GFER GEDR 9 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 10 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 11 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 12 * 13 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 14 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 15 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 16 * 17 * NOTE: 18 * BANK 3 is only available on PXA27x and later processors. 19 * BANK 4 and 5 are only available on PXA935 20 */ 21 22#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) 23 24#define GPLR_OFFSET 0x00 25#define GPDR_OFFSET 0x0C 26#define GPSR_OFFSET 0x18 27#define GPCR_OFFSET 0x24 28#define GRER_OFFSET 0x30 29#define GFER_OFFSET 0x3C 30#define GEDR_OFFSET 0x48 31 32static inline int gpio_get_value(unsigned gpio) 33{ 34 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) 35 return GPLR(gpio) & GPIO_bit(gpio); 36 else 37 return __gpio_get_value(gpio); 38} 39 40static inline void gpio_set_value(unsigned gpio, int value) 41{ 42 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { 43 if (value) 44 GPSR(gpio) = GPIO_bit(gpio); 45 else 46 GPCR(gpio) = GPIO_bit(gpio); 47 } else 48 __gpio_set_value(gpio, value); 49} 50 51#define gpio_cansleep __gpio_cansleep 52 53/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). 54 * Those cases currently cause holes in the GPIO number space, the 55 * actual number of the last GPIO is recorded by 'pxa_last_gpio'. 56 */ 57extern int pxa_last_gpio; 58 59typedef int (*set_wake_t)(unsigned int irq, unsigned int on); 60 61extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); 62#endif /* __PLAT_GPIO_H */ 63