1/* arch/arm/mach-s3c2410/include/mach/regs-spi.h 2 * 3 * Copyright (c) 2004 Fetron GmbH 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * S3C2410 SPI register definition 10*/ 11 12#ifndef __ASM_ARCH_REGS_SPI_H 13#define __ASM_ARCH_REGS_SPI_H 14 15#define S3C2410_SPI1 (0x20) 16#define S3C2412_SPI1 (0x100) 17 18#define S3C2410_SPCON (0x00) 19 20#define S3C2412_SPCON_RXFIFO_RB2 (0<<14) 21#define S3C2412_SPCON_RXFIFO_RB4 (1<<14) 22#define S3C2412_SPCON_RXFIFO_RB12 (2<<14) 23#define S3C2412_SPCON_RXFIFO_RB14 (3<<14) 24#define S3C2412_SPCON_TXFIFO_RB2 (0<<12) 25#define S3C2412_SPCON_TXFIFO_RB4 (1<<12) 26#define S3C2412_SPCON_TXFIFO_RB12 (2<<12) 27#define S3C2412_SPCON_TXFIFO_RB14 (3<<12) 28#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */ 29#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */ 30#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */ 31#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */ 32 33#define S3C2412_SPCON_DIRC_RX (1<<7) 34 35#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ 36#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ 37#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ 38#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */ 39#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select 40 0: slave, 1: master */ 41#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */ 42#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */ 43 44#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */ 45#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */ 46 47#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */ 48 49 50#define S3C2410_SPSTA (0x04) 51 52#define S3C2412_SPSTA_RXFIFO_AE (1<<11) 53#define S3C2412_SPSTA_TXFIFO_AE (1<<10) 54#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9) 55#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8) 56#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7) 57#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6) 58#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5) 59#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4) 60 61#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ 62#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ 63#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ 64#define S3C2412_SPSTA_READY_ORG (1<<3) 65 66#define S3C2410_SPPIN (0x08) 67 68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ 69#define S3C2410_SPPIN_RESERVED (1<<1) 70#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ 71#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ 72 73#define S3C2410_SPPRE (0x0C) 74#define S3C2410_SPTDAT (0x10) 75#define S3C2410_SPRDAT (0x14) 76 77#define S3C2412_TXFIFO (0x18) 78#define S3C2412_RXFIFO (0x18) 79#define S3C2412_SPFIC (0x24) 80 81 82#endif /* __ASM_ARCH_REGS_SPI_H */ 83