1/* 2 * Clock control driver for Freescale STMP37XX/STMP378X - internal header file 3 * 4 * Author: Vitaly Wool <vital@embeddedalley.com> 5 * 6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 8 */ 9 10/* 11 * The code contained herein is licensed under the GNU General Public 12 * License. You may obtain a copy of the GNU General Public License 13 * Version 2 or later at the following locations: 14 * 15 * http://www.opensource.org/licenses/gpl-license.html 16 * http://www.gnu.org/copyleft/gpl.html 17 */ 18#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__ 19#define __ARCH_ARM_STMX3XXX_CLOCK_H__ 20 21#ifndef __ASSEMBLER__ 22 23struct clk_ops { 24 int (*enable) (struct clk *); 25 int (*disable) (struct clk *); 26 long (*get_rate) (struct clk *); 27 long (*round_rate) (struct clk *, u32); 28 int (*set_rate) (struct clk *, u32); 29 int (*set_parent) (struct clk *, struct clk *); 30}; 31 32struct clk { 33 struct clk *parent; 34 u32 rate; 35 u32 flags; 36 u8 scale_shift; 37 u8 enable_shift; 38 u8 bypass_shift; 39 u8 busy_bit; 40 s8 usage; 41 int enable_wait; 42 int enable_negate; 43 u32 saved_div; 44 void __iomem *enable_reg; 45 void __iomem *scale_reg; 46 void __iomem *bypass_reg; 47 void __iomem *busy_reg; 48 struct clk_ops *ops; 49}; 50 51#endif /* __ASSEMBLER__ */ 52 53/* Flags */ 54#define RATE_PROPAGATES (1<<0) 55#define NEEDS_INITIALIZATION (1<<1) 56#define PARENT_SET_RATE (1<<2) 57#define FIXED_RATE (1<<3) 58#define ENABLED (1<<4) 59#define NEEDS_SET_PARENT (1<<5) 60 61#endif 62