LXR linux/arch/arm/plat-stmp3xxx/include/mach/pinmux.h

   1/*
   2 * Freescale STMP37XX/STMP378X Pin Multiplexing
   3 *
   4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
   5 *
   6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
   7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   8 */
   9
  10/*
  11 * The code contained herein is licensed under the GNU General Public
  12 * License. You may obtain a copy of the GNU General Public License
  13 * Version 2 or later at the following locations:
  14 *
  15 * http://www.opensource.org/licenses/gpl-license.html
  16 * http://www.gnu.org/copyleft/gpl.html
  17 */
  18#ifndef __PINMUX_H
  19#define __PINMUX_H
  20
  21#include <linux/spinlock.h>
  22#include <linux/types.h>
  23#include <linux/gpio.h>
  24#include <asm-generic/gpio.h>
  25
  26/* Pin definitions */
  27#include "pins.h"
  28#include <mach/pins.h>
  29
  30/*
  31 * Each pin may be routed up to four different HW interfaces
  32 * including GPIO
  33 */
  34enum pin_fun {
  35        PIN_FUN1 = 0,
  36        PIN_FUN2,
  37        PIN_FUN3,
  38        PIN_GPIO,
  39};
  40
  41/*
  42 * Each pin may have different output drive strength in range from
  43 * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
  44 */
  45enum pin_strength {
  46        PIN_4MA = 0,
  47        PIN_8MA,
  48        PIN_12MA,
  49        PIN_16MA,
  50        PIN_20MA,
  51};
  52
  53/*
  54 * Each pin can be programmed for 1.8V or 3.3V
  55 */
  56enum pin_voltage {
  57        PIN_1_8V = 0,
  58        PIN_3_3V,
  59};
  60
  61/*
  62 * Structure to define a group of pins and their parameters
  63 */
  64struct pin_desc {
  65        unsigned id;
  66        enum pin_fun fun;
  67        enum pin_strength strength;
  68        enum pin_voltage voltage;
  69        unsigned pullup:1;
  70};
  71
  72struct pin_group {
  73        struct pin_desc *pins;
  74        int nr_pins;
  75};
  76
  77/* Set pin drive strength */
  78void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
  79                           const char *label);
  80
  81/* Set pin voltage */
  82void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
  83                           const char *label);
  84
  85/* Enable pull-up resistor for a pin */
  86void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
  87
  88/*
  89 * Request a pin ownership, only one module (identified by @label)
  90 * may own a pin.
  91 */
  92int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
  93
  94/* Release pin */
  95void stmp3xxx_release_pin(unsigned id, const char *label);
  96
  97void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
  98
  99/*
 100 * Each bank is associated with a number of registers to control
 101 * pin function, drive strength, voltage and pull-up reigster. The
 102 * number of registers of a given type depends on the number of bits
 103 * describin particular pin.
 104 */
 105#define HW_MUXSEL_NUM           2       /* registers per bank */
 106#define HW_MUXSEL_PIN_LEN       2       /* bits per pin */
 107#define HW_MUXSEL_PIN_NUM       16      /* pins per register */
 108#define HW_MUXSEL_PINFUN_MASK   0x3     /* pin function mask */
 109#define HW_MUXSEL_PINFUN_NUM    4       /* four options for a pin */
 110
 111#define HW_DRIVE_NUM            4       /* registers per bank */
 112#define HW_DRIVE_PIN_LEN        4       /* bits per pin */
 113#define HW_DRIVE_PIN_NUM        8       /* pins per register */
 114#define HW_DRIVE_PINDRV_MASK    0x3     /* pin strength mask - 2 bits */
 115#define HW_DRIVE_PINDRV_NUM     5       /* five possible strength values */
 116#define HW_DRIVE_PINV_MASK      0x4     /* pin voltage mask - 1 bit */
 117
 118
 119struct stmp3xxx_pinmux_bank {
 120        struct gpio_chip chip;
 121
 122        /* Pins allocation map */
 123        unsigned long pin_map;
 124
 125        /* Pin owner names */
 126        const char *pin_labels[32];
 127
 128        /* Bank registers */
 129        void __iomem *hw_muxsel[HW_MUXSEL_NUM];
 130        void __iomem *hw_drive[HW_DRIVE_NUM];
 131        void __iomem *hw_pull;
 132
 133        void __iomem *pin2irq,
 134                *irqlevel,
 135                *irqpolarity,
 136                *irqen,
 137                *irqstat;
 138
 139        /* HW MUXSEL register function bit values */
 140        u8 functions[HW_MUXSEL_PINFUN_NUM];
 141
 142        /*
 143         * HW DRIVE register strength bit values:
 144         * 0xff - requested strength is not supported for this bank
 145         */
 146        u8 strengths[HW_DRIVE_PINDRV_NUM];
 147
 148        /* GPIO things */
 149        void __iomem *hw_gpio_in,
 150                     *hw_gpio_out,
 151                     *hw_gpio_doe;
 152        int irq, virq;
 153};
 154
 155int __init stmp3xxx_pinmux_init(int virtual_irq_start);
 156
 157#endif /* __PINMUX_H */
 158