1
2
3
4
5
6mainmenu "Blackfin Kernel Configuration"
7
8config MMU
9 def_bool n
10
11config FPU
12 def_bool n
13
14config RWSEM_GENERIC_SPINLOCK
15 def_bool y
16
17config RWSEM_XCHGADD_ALGORITHM
18 def_bool n
19
20config BLACKFIN
21 def_bool y
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
24 select HAVE_IDE
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
28 select HAVE_OPROFILE
29 select ARCH_WANT_OPTIONAL_GPIOLIB
30
31config GENERIC_BUG
32 def_bool y
33 depends on BUG
34
35config ZONE_DMA
36 def_bool y
37
38config GENERIC_FIND_NEXT_BIT
39 def_bool y
40
41config GENERIC_HWEIGHT
42 def_bool y
43
44config GENERIC_HARDIRQS
45 def_bool y
46
47config GENERIC_IRQ_PROBE
48 def_bool y
49
50config GENERIC_HARDIRQS_NO__DO_IRQ
51 def_bool y
52
53config GENERIC_GPIO
54 def_bool y
55
56config FORCE_MAX_ZONEORDER
57 int
58 default "14"
59
60config GENERIC_CALIBRATE_DELAY
61 def_bool y
62
63config LOCKDEP_SUPPORT
64 def_bool y
65
66config STACKTRACE_SUPPORT
67 def_bool y
68
69config TRACE_IRQFLAGS_SUPPORT
70 def_bool y
71
72source "init/Kconfig"
73
74source "kernel/Kconfig.preempt"
75
76source "kernel/Kconfig.freezer"
77
78menu "Blackfin Processor Options"
79
80comment "Processor and Board Settings"
81
82choice
83 prompt "CPU"
84 default BF533
85
86config BF512
87 bool "BF512"
88 help
89 BF512 Processor Support.
90
91config BF514
92 bool "BF514"
93 help
94 BF514 Processor Support.
95
96config BF516
97 bool "BF516"
98 help
99 BF516 Processor Support.
100
101config BF518
102 bool "BF518"
103 help
104 BF518 Processor Support.
105
106config BF522
107 bool "BF522"
108 help
109 BF522 Processor Support.
110
111config BF523
112 bool "BF523"
113 help
114 BF523 Processor Support.
115
116config BF524
117 bool "BF524"
118 help
119 BF524 Processor Support.
120
121config BF525
122 bool "BF525"
123 help
124 BF525 Processor Support.
125
126config BF526
127 bool "BF526"
128 help
129 BF526 Processor Support.
130
131config BF527
132 bool "BF527"
133 help
134 BF527 Processor Support.
135
136config BF531
137 bool "BF531"
138 help
139 BF531 Processor Support.
140
141config BF532
142 bool "BF532"
143 help
144 BF532 Processor Support.
145
146config BF533
147 bool "BF533"
148 help
149 BF533 Processor Support.
150
151config BF534
152 bool "BF534"
153 help
154 BF534 Processor Support.
155
156config BF536
157 bool "BF536"
158 help
159 BF536 Processor Support.
160
161config BF537
162 bool "BF537"
163 help
164 BF537 Processor Support.
165
166config BF538
167 bool "BF538"
168 help
169 BF538 Processor Support.
170
171config BF539
172 bool "BF539"
173 help
174 BF539 Processor Support.
175
176config BF542
177 bool "BF542"
178 help
179 BF542 Processor Support.
180
181config BF542M
182 bool "BF542m"
183 help
184 BF542 Processor Support.
185
186config BF544
187 bool "BF544"
188 help
189 BF544 Processor Support.
190
191config BF544M
192 bool "BF544m"
193 help
194 BF544 Processor Support.
195
196config BF547
197 bool "BF547"
198 help
199 BF547 Processor Support.
200
201config BF547M
202 bool "BF547m"
203 help
204 BF547 Processor Support.
205
206config BF548
207 bool "BF548"
208 help
209 BF548 Processor Support.
210
211config BF548M
212 bool "BF548m"
213 help
214 BF548 Processor Support.
215
216config BF549
217 bool "BF549"
218 help
219 BF549 Processor Support.
220
221config BF549M
222 bool "BF549m"
223 help
224 BF549 Processor Support.
225
226config BF561
227 bool "BF561"
228 help
229 BF561 Processor Support.
230
231endchoice
232
233config SMP
234 depends on BF561
235 select GENERIC_CLOCKEVENTS
236 bool "Symmetric multi-processing support"
237 ---help---
238 This enables support for systems with more than one CPU,
239 like the dual core BF561. If you have a system with only one
240 CPU, say N. If you have a system with more than one CPU, say Y.
241
242 If you don't know what to do here, say N.
243
244config NR_CPUS
245 int
246 depends on SMP
247 default 2 if BF561
248
249config IRQ_PER_CPU
250 bool
251 depends on SMP
252 default y
253
254config BF_REV_MIN
255 int
256 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
257 default 2 if (BF537 || BF536 || BF534)
258 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
259 default 4 if (BF538 || BF539)
260
261config BF_REV_MAX
262 int
263 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
264 default 3 if (BF537 || BF536 || BF534 || BF54xM)
265 default 5 if (BF561 || BF538 || BF539)
266 default 6 if (BF533 || BF532 || BF531)
267
268choice
269 prompt "Silicon Rev"
270 default BF_REV_0_0 if (BF51x || BF52x)
271 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
272 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
273
274config BF_REV_0_0
275 bool "0.0"
276 depends on (BF51x || BF52x || (BF54x && !BF54xM))
277
278config BF_REV_0_1
279 bool "0.1"
280 depends on (BF51x || BF52x || (BF54x && !BF54xM))
281
282config BF_REV_0_2
283 bool "0.2"
284 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
285
286config BF_REV_0_3
287 bool "0.3"
288 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
289
290config BF_REV_0_4
291 bool "0.4"
292 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
293
294config BF_REV_0_5
295 bool "0.5"
296 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
297
298config BF_REV_0_6
299 bool "0.6"
300 depends on (BF533 || BF532 || BF531)
301
302config BF_REV_ANY
303 bool "any"
304
305config BF_REV_NONE
306 bool "none"
307
308endchoice
309
310config BF51x
311 bool
312 depends on (BF512 || BF514 || BF516 || BF518)
313 default y
314
315config BF52x
316 bool
317 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
318 default y
319
320config BF53x
321 bool
322 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
323 default y
324
325config BF54xM
326 bool
327 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
328 default y
329
330config BF54x
331 bool
332 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
333 default y
334
335config MEM_GENERIC_BOARD
336 bool
337 depends on GENERIC_BOARD
338 default y
339
340config MEM_MT48LC64M4A2FB_7E
341 bool
342 depends on (BFIN533_STAMP)
343 default y
344
345config MEM_MT48LC16M16A2TG_75
346 bool
347 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
348 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
349 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
350 || BFIN527_BLUETECHNIX_CM)
351 default y
352
353config MEM_MT48LC32M8A2_75
354 bool
355 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
356 default y
357
358config MEM_MT48LC8M32B2B5_7
359 bool
360 depends on (BFIN561_BLUETECHNIX_CM)
361 default y
362
363config MEM_MT48LC32M16A2TG_75
364 bool
365 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
366 default y
367
368config MEM_MT48LC32M8A2_75
369 bool
370 depends on (BFIN518F_EZBRD)
371 default y
372
373config MEM_MT48H32M16LFCJ_75
374 bool
375 depends on (BFIN526_EZBRD)
376 default y
377
378source "arch/blackfin/mach-bf518/Kconfig"
379source "arch/blackfin/mach-bf527/Kconfig"
380source "arch/blackfin/mach-bf533/Kconfig"
381source "arch/blackfin/mach-bf561/Kconfig"
382source "arch/blackfin/mach-bf537/Kconfig"
383source "arch/blackfin/mach-bf538/Kconfig"
384source "arch/blackfin/mach-bf548/Kconfig"
385
386menu "Board customizations"
387
388config CMDLINE_BOOL
389 bool "Default bootloader kernel arguments"
390
391config CMDLINE
392 string "Initial kernel command string"
393 depends on CMDLINE_BOOL
394 default "console=ttyBF0,57600"
395 help
396 If you don't have a boot loader capable of passing a command line string
397 to the kernel, you may specify one here. As a minimum, you should specify
398 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
399
400config BOOT_LOAD
401 hex "Kernel load address for booting"
402 default "0x1000"
403 range 0x1000 0x20000000
404 help
405 This option allows you to set the load address of the kernel.
406 This can be useful if you are on a board which has a small amount
407 of memory or you wish to reserve some memory at the beginning of
408 the address space.
409
410 Note that you need to keep this value above 4k (0x1000) as this
411 memory region is used to capture NULL pointer references as well
412 as some core kernel functions.
413
414config ROM_BASE
415 hex "Kernel ROM Base"
416 depends on ROMKERNEL
417 default "0x20040000"
418 range 0x20000000 0x20400000 if !(BF54x || BF561)
419 range 0x20000000 0x30000000 if (BF54x || BF561)
420 help
421
422comment "Clock/PLL Setup"
423
424config CLKIN_HZ
425 int "Frequency of the crystal on the board in Hz"
426 default "10000000" if BFIN532_IP0X
427 default "11059200" if BFIN533_STAMP
428 default "24576000" if PNAV10
429 default "25000000"
430 default "27000000" if BFIN533_EZKIT
431 default "30000000" if BFIN561_EZKIT
432 help
433 The frequency of CLKIN crystal oscillator on the board in Hz.
434 Warning: This value should match the crystal on the board. Otherwise,
435 peripherals won't work properly.
436
437config BFIN_KERNEL_CLOCK
438 bool "Re-program Clocks while Kernel boots?"
439 default n
440 help
441 This option decides if kernel clocks are re-programed from the
442 bootloader settings. If the clocks are not set, the SDRAM settings
443 are also not changed, and the Bootloader does 100% of the hardware
444 configuration.
445
446config PLL_BYPASS
447 bool "Bypass PLL"
448 depends on BFIN_KERNEL_CLOCK
449 default n
450
451config CLKIN_HALF
452 bool "Half Clock In"
453 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
454 default n
455 help
456 If this is set the clock will be divided by 2, before it goes to the PLL.
457
458config VCO_MULT
459 int "VCO Multiplier"
460 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
461 range 1 64
462 default "22" if BFIN533_EZKIT
463 default "45" if BFIN533_STAMP
464 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
465 default "22" if BFIN533_BLUETECHNIX_CM
466 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
467 default "20" if BFIN561_EZKIT
468 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
469 help
470 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
471 PLL Frequency = (Crystal Frequency) * (this setting)
472
473choice
474 prompt "Core Clock Divider"
475 depends on BFIN_KERNEL_CLOCK
476 default CCLK_DIV_1
477 help
478 This sets the frequency of the core. It can be 1, 2, 4 or 8
479 Core Frequency = (PLL frequency) / (this setting)
480
481config CCLK_DIV_1
482 bool "1"
483
484config CCLK_DIV_2
485 bool "2"
486
487config CCLK_DIV_4
488 bool "4"
489
490config CCLK_DIV_8
491 bool "8"
492endchoice
493
494config SCLK_DIV
495 int "System Clock Divider"
496 depends on BFIN_KERNEL_CLOCK
497 range 1 15
498 default 5
499 help
500 This sets the frequency of the system clock (including SDRAM or DDR).
501 This can be between 1 and 15
502 System Clock = (PLL frequency) / (this setting)
503
504choice
505 prompt "DDR SDRAM Chip Type"
506 depends on BFIN_KERNEL_CLOCK
507 depends on BF54x
508 default MEM_MT46V32M16_5B
509
510config MEM_MT46V32M16_6T
511 bool "MT46V32M16_6T"
512
513config MEM_MT46V32M16_5B
514 bool "MT46V32M16_5B"
515endchoice
516
517choice
518 prompt "DDR/SDRAM Timing"
519 depends on BFIN_KERNEL_CLOCK
520 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
521 help
522 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
523 The calculated SDRAM timing parameters may not be 100%
524 accurate - This option is therefore marked experimental.
525
526config BFIN_KERNEL_CLOCK_MEMINIT_CALC
527 bool "Calculate Timings (EXPERIMENTAL)"
528 depends on EXPERIMENTAL
529
530config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
531 bool "Provide accurate Timings based on target SCLK"
532 help
533 Please consult the Blackfin Hardware Reference Manuals as well
534 as the memory device datasheet.
535 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
536endchoice
537
538menu "Memory Init Control"
539 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
540
541config MEM_DDRCTL0
542 depends on BF54x
543 hex "DDRCTL0"
544 default 0x0
545
546config MEM_DDRCTL1
547 depends on BF54x
548 hex "DDRCTL1"
549 default 0x0
550
551config MEM_DDRCTL2
552 depends on BF54x
553 hex "DDRCTL2"
554 default 0x0
555
556config MEM_EBIU_DDRQUE
557 depends on BF54x
558 hex "DDRQUE"
559 default 0x0
560
561config MEM_SDRRC
562 depends on !BF54x
563 hex "SDRRC"
564 default 0x0
565
566config MEM_SDGCTL
567 depends on !BF54x
568 hex "SDGCTL"
569 default 0x0
570endmenu
571
572
573
574
575config MAX_VCO_HZ
576 int
577 default 400000000 if BF512
578 default 400000000 if BF514
579 default 400000000 if BF516
580 default 400000000 if BF518
581 default 400000000 if BF522
582 default 600000000 if BF523
583 default 400000000 if BF524
584 default 600000000 if BF525
585 default 400000000 if BF526
586 default 600000000 if BF527
587 default 400000000 if BF531
588 default 400000000 if BF532
589 default 750000000 if BF533
590 default 500000000 if BF534
591 default 400000000 if BF536
592 default 600000000 if BF537
593 default 533333333 if BF538
594 default 533333333 if BF539
595 default 600000000 if BF542
596 default 533333333 if BF544
597 default 600000000 if BF547
598 default 600000000 if BF548
599 default 533333333 if BF549
600 default 600000000 if BF561
601
602config MIN_VCO_HZ
603 int
604 default 50000000
605
606config MAX_SCLK_HZ
607 int
608 default 133333333
609
610config MIN_SCLK_HZ
611 int
612 default 27000000
613
614comment "Kernel Timer/Scheduler"
615
616source kernel/Kconfig.hz
617
618config GENERIC_TIME
619 def_bool y
620
621config GENERIC_CLOCKEVENTS
622 bool "Generic clock events"
623 default y
624
625choice
626 prompt "Kernel Tick Source"
627 depends on GENERIC_CLOCKEVENTS
628 default TICKSOURCE_CORETMR
629
630config TICKSOURCE_GPTMR0
631 bool "Gptimer0 (SCLK domain)"
632 select BFIN_GPTIMERS
633
634config TICKSOURCE_CORETMR
635 bool "Core timer (CCLK domain)"
636
637endchoice
638
639config CYCLES_CLOCKSOURCE
640 bool "Use 'CYCLES' as a clocksource"
641 depends on GENERIC_CLOCKEVENTS
642 depends on !BFIN_SCRATCH_REG_CYCLES
643 depends on !SMP
644 help
645 If you say Y here, you will enable support for using the 'cycles'
646 registers as a clock source. Doing so means you will be unable to
647 safely write to the 'cycles' register during runtime. You will
648 still be able to read it (such as for performance monitoring), but
649 writing the registers will most likely crash the kernel.
650
651config GPTMR0_CLOCKSOURCE
652 bool "Use GPTimer0 as a clocksource"
653 select BFIN_GPTIMERS
654 depends on GENERIC_CLOCKEVENTS
655 depends on !TICKSOURCE_GPTMR0
656
657config ARCH_USES_GETTIMEOFFSET
658 depends on !GENERIC_CLOCKEVENTS
659 def_bool y
660
661source kernel/time/Kconfig
662
663comment "Misc"
664
665choice
666 prompt "Blackfin Exception Scratch Register"
667 default BFIN_SCRATCH_REG_RETN
668 help
669 Select the resource to reserve for the Exception handler:
670 - RETN: Non-Maskable Interrupt (NMI)
671 - RETE: Exception Return (JTAG/ICE)
672 - CYCLES: Performance counter
673
674 If you are unsure, please select "RETN".
675
676config BFIN_SCRATCH_REG_RETN
677 bool "RETN"
678 help
679 Use the RETN register in the Blackfin exception handler
680 as a stack scratch register. This means you cannot
681 safely use NMI on the Blackfin while running Linux, but
682 you can debug the system with a JTAG ICE and use the
683 CYCLES performance registers.
684
685 If you are unsure, please select "RETN".
686
687config BFIN_SCRATCH_REG_RETE
688 bool "RETE"
689 help
690 Use the RETE register in the Blackfin exception handler
691 as a stack scratch register. This means you cannot
692 safely use a JTAG ICE while debugging a Blackfin board,
693 but you can safely use the CYCLES performance registers
694 and the NMI.
695
696 If you are unsure, please select "RETN".
697
698config BFIN_SCRATCH_REG_CYCLES
699 bool "CYCLES"
700 help
701 Use the CYCLES register in the Blackfin exception handler
702 as a stack scratch register. This means you cannot
703 safely use the CYCLES performance registers on a Blackfin
704 board at anytime, but you can debug the system with a JTAG
705 ICE and use the NMI.
706
707 If you are unsure, please select "RETN".
708
709endchoice
710
711endmenu
712
713
714menu "Blackfin Kernel Optimizations"
715 depends on !SMP
716
717comment "Memory Optimizations"
718
719config I_ENTRY_L1
720 bool "Locate interrupt entry code in L1 Memory"
721 default y
722 help
723 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
724 into L1 instruction memory. (less latency)
725
726config EXCPT_IRQ_SYSC_L1
727 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
728 default y
729 help
730 If enabled, the entire ASM lowlevel exception and interrupt entry code
731 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
732 (less latency)
733
734config DO_IRQ_L1
735 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
736 default y
737 help
738 If enabled, the frequently called do_irq dispatcher function is linked
739 into L1 instruction memory. (less latency)
740
741config CORE_TIMER_IRQ_L1
742 bool "Locate frequently called timer_interrupt() function in L1 Memory"
743 default y
744 help
745 If enabled, the frequently called timer_interrupt() function is linked
746 into L1 instruction memory. (less latency)
747
748config IDLE_L1
749 bool "Locate frequently idle function in L1 Memory"
750 default y
751 help
752 If enabled, the frequently called idle function is linked
753 into L1 instruction memory. (less latency)
754
755config SCHEDULE_L1
756 bool "Locate kernel schedule function in L1 Memory"
757 default y
758 help
759 If enabled, the frequently called kernel schedule is linked
760 into L1 instruction memory. (less latency)
761
762config ARITHMETIC_OPS_L1
763 bool "Locate kernel owned arithmetic functions in L1 Memory"
764 default y
765 help
766 If enabled, arithmetic functions are linked
767 into L1 instruction memory. (less latency)
768
769config ACCESS_OK_L1
770 bool "Locate access_ok function in L1 Memory"
771 default y
772 help
773 If enabled, the access_ok function is linked
774 into L1 instruction memory. (less latency)
775
776config MEMSET_L1
777 bool "Locate memset function in L1 Memory"
778 default y
779 help
780 If enabled, the memset function is linked
781 into L1 instruction memory. (less latency)
782
783config MEMCPY_L1
784 bool "Locate memcpy function in L1 Memory"
785 default y
786 help
787 If enabled, the memcpy function is linked
788 into L1 instruction memory. (less latency)
789
790config SYS_BFIN_SPINLOCK_L1
791 bool "Locate sys_bfin_spinlock function in L1 Memory"
792 default y
793 help
794 If enabled, sys_bfin_spinlock function is linked
795 into L1 instruction memory. (less latency)
796
797config IP_CHECKSUM_L1
798 bool "Locate IP Checksum function in L1 Memory"
799 default n
800 help
801 If enabled, the IP Checksum function is linked
802 into L1 instruction memory. (less latency)
803
804config CACHELINE_ALIGNED_L1
805 bool "Locate cacheline_aligned data to L1 Data Memory"
806 default y if !BF54x
807 default n if BF54x
808 depends on !BF531
809 help
810 If enabled, cacheline_aligned data is linked
811 into L1 data memory. (less latency)
812
813config SYSCALL_TAB_L1
814 bool "Locate Syscall Table L1 Data Memory"
815 default n
816 depends on !BF531
817 help
818 If enabled, the Syscall LUT is linked
819 into L1 data memory. (less latency)
820
821config CPLB_SWITCH_TAB_L1
822 bool "Locate CPLB Switch Tables L1 Data Memory"
823 default n
824 depends on !BF531
825 help
826 If enabled, the CPLB Switch Tables are linked
827 into L1 data memory. (less latency)
828
829config APP_STACK_L1
830 bool "Support locating application stack in L1 Scratch Memory"
831 default y
832 help
833 If enabled the application stack can be located in L1
834 scratch memory (less latency).
835
836 Currently only works with FLAT binaries.
837
838config EXCEPTION_L1_SCRATCH
839 bool "Locate exception stack in L1 Scratch Memory"
840 default n
841 depends on !APP_STACK_L1
842 help
843 Whenever an exception occurs, use the L1 Scratch memory for
844 stack storage. You cannot place the stacks of FLAT binaries
845 in L1 when using this option.
846
847 If you don't use L1 Scratch, then you should say Y here.
848
849comment "Speed Optimizations"
850config BFIN_INS_LOWOVERHEAD
851 bool "ins[bwl] low overhead, higher interrupt latency"
852 default y
853 help
854 Reads on the Blackfin are speculative. In Blackfin terms, this means
855 they can be interrupted at any time (even after they have been issued
856 on to the external bus), and re-issued after the interrupt occurs.
857 For memory - this is not a big deal, since memory does not change if
858 it sees a read.
859
860 If a FIFO is sitting on the end of the read, it will see two reads,
861 when the core only sees one since the FIFO receives both the read
862 which is cancelled (and not delivered to the core) and the one which
863 is re-issued (which is delivered to the core).
864
865 To solve this, interrupts are turned off before reads occur to
866 I/O space. This option controls which the overhead/latency of
867 controlling interrupts during this time
868 "n" turns interrupts off every read
869 (higher overhead, but lower interrupt latency)
870 "y" turns interrupts off every loop
871 (low overhead, but longer interrupt latency)
872
873 default behavior is to leave this set to on (type "Y"). If you are experiencing
874 interrupt latency issues, it is safe and OK to turn this off.
875
876endmenu
877
878choice
879 prompt "Kernel executes from"
880 help
881 Choose the memory type that the kernel will be running in.
882
883config RAMKERNEL
884 bool "RAM"
885 help
886 The kernel will be resident in RAM when running.
887
888config ROMKERNEL
889 bool "ROM"
890 help
891 The kernel will be resident in FLASH/ROM when running.
892
893endchoice
894
895source "mm/Kconfig"
896
897config BFIN_GPTIMERS
898 tristate "Enable Blackfin General Purpose Timers API"
899 default n
900 help
901 Enable support for the General Purpose Timers API. If you
902 are unsure, say N.
903
904 To compile this driver as a module, choose M here: the module
905 will be called gptimers.
906
907choice
908 prompt "Uncached DMA region"
909 default DMA_UNCACHED_1M
910config DMA_UNCACHED_4M
911 bool "Enable 4M DMA region"
912config DMA_UNCACHED_2M
913 bool "Enable 2M DMA region"
914config DMA_UNCACHED_1M
915 bool "Enable 1M DMA region"
916config DMA_UNCACHED_NONE
917 bool "Disable DMA region"
918endchoice
919
920
921comment "Cache Support"
922
923config BFIN_ICACHE
924 bool "Enable ICACHE"
925 default y
926config BFIN_EXTMEM_ICACHEABLE
927 bool "Enable ICACHE for external memory"
928 depends on BFIN_ICACHE
929 default y
930config BFIN_L2_ICACHEABLE
931 bool "Enable ICACHE for L2 SRAM"
932 depends on BFIN_ICACHE
933 depends on BF54x || BF561
934 default n
935
936config BFIN_DCACHE
937 bool "Enable DCACHE"
938 default y
939config BFIN_DCACHE_BANKA
940 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
941 depends on BFIN_DCACHE && !BF531
942 default n
943config BFIN_EXTMEM_DCACHEABLE
944 bool "Enable DCACHE for external memory"
945 depends on BFIN_DCACHE
946 default y
947choice
948 prompt "External memory DCACHE policy"
949 depends on BFIN_EXTMEM_DCACHEABLE
950 default BFIN_EXTMEM_WRITEBACK if !SMP
951 default BFIN_EXTMEM_WRITETHROUGH if SMP
952config BFIN_EXTMEM_WRITEBACK
953 bool "Write back"
954 depends on !SMP
955 help
956 Write Back Policy:
957 Cached data will be written back to SDRAM only when needed.
958 This can give a nice increase in performance, but beware of
959 broken drivers that do not properly invalidate/flush their
960 cache.
961
962 Write Through Policy:
963 Cached data will always be written back to SDRAM when the
964 cache is updated. This is a completely safe setting, but
965 performance is worse than Write Back.
966
967 If you are unsure of the options and you want to be safe,
968 then go with Write Through.
969
970config BFIN_EXTMEM_WRITETHROUGH
971 bool "Write through"
972 help
973 Write Back Policy:
974 Cached data will be written back to SDRAM only when needed.
975 This can give a nice increase in performance, but beware of
976 broken drivers that do not properly invalidate/flush their
977 cache.
978
979 Write Through Policy:
980 Cached data will always be written back to SDRAM when the
981 cache is updated. This is a completely safe setting, but
982 performance is worse than Write Back.
983
984 If you are unsure of the options and you want to be safe,
985 then go with Write Through.
986
987endchoice
988
989config BFIN_L2_DCACHEABLE
990 bool "Enable DCACHE for L2 SRAM"
991 depends on BFIN_DCACHE
992 depends on (BF54x || BF561) && !SMP
993 default n
994choice
995 prompt "L2 SRAM DCACHE policy"
996 depends on BFIN_L2_DCACHEABLE
997 default BFIN_L2_WRITEBACK
998config BFIN_L2_WRITEBACK
999 bool "Write back"
1000
1001config BFIN_L2_WRITETHROUGH
1002 bool "Write through"
1003endchoice
1004
1005
1006comment "Memory Protection Unit"
1007config MPU
1008 bool "Enable the memory protection unit (EXPERIMENTAL)"
1009 default n
1010 help
1011 Use the processor's MPU to protect applications from accessing
1012 memory they do not own. This comes at a performance penalty
1013 and is recommended only for debugging.
1014
1015comment "Asynchronous Memory Configuration"
1016
1017menu "EBIU_AMGCTL Global Control"
1018config C_AMCKEN
1019 bool "Enable CLKOUT"
1020 default y
1021
1022config C_CDPRIO
1023 bool "DMA has priority over core for ext. accesses"
1024 default n
1025
1026config C_B0PEN
1027 depends on BF561
1028 bool "Bank 0 16 bit packing enable"
1029 default y
1030
1031config C_B1PEN
1032 depends on BF561
1033 bool "Bank 1 16 bit packing enable"
1034 default y
1035
1036config C_B2PEN
1037 depends on BF561
1038 bool "Bank 2 16 bit packing enable"
1039 default y
1040
1041config C_B3PEN
1042 depends on BF561
1043 bool "Bank 3 16 bit packing enable"
1044 default n
1045
1046choice
1047 prompt "Enable Asynchronous Memory Banks"
1048 default C_AMBEN_ALL
1049
1050config C_AMBEN
1051 bool "Disable All Banks"
1052
1053config C_AMBEN_B0
1054 bool "Enable Bank 0"
1055
1056config C_AMBEN_B0_B1
1057 bool "Enable Bank 0 & 1"
1058
1059config C_AMBEN_B0_B1_B2
1060 bool "Enable Bank 0 & 1 & 2"
1061
1062config C_AMBEN_ALL
1063 bool "Enable All Banks"
1064endchoice
1065endmenu
1066
1067menu "EBIU_AMBCTL Control"
1068config BANK_0
1069 hex "Bank 0 (AMBCTL0.L)"
1070 default 0x7BB0
1071 help
1072 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1073 used to control the Asynchronous Memory Bank 0 settings.
1074
1075config BANK_1
1076 hex "Bank 1 (AMBCTL0.H)"
1077 default 0x7BB0
1078 default 0x5558 if BF54x
1079 help
1080 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1081 used to control the Asynchronous Memory Bank 1 settings.
1082
1083config BANK_2
1084 hex "Bank 2 (AMBCTL1.L)"
1085 default 0x7BB0
1086 help
1087 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1088 used to control the Asynchronous Memory Bank 2 settings.
1089
1090config BANK_3
1091 hex "Bank 3 (AMBCTL1.H)"
1092 default 0x99B3
1093 help
1094 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1095 used to control the Asynchronous Memory Bank 3 settings.
1096
1097endmenu
1098
1099config EBIU_MBSCTLVAL
1100 hex "EBIU Bank Select Control Register"
1101 depends on BF54x
1102 default 0
1103
1104config EBIU_MODEVAL
1105 hex "Flash Memory Mode Control Register"
1106 depends on BF54x
1107 default 1
1108
1109config EBIU_FCTLVAL
1110 hex "Flash Memory Bank Control Register"
1111 depends on BF54x
1112 default 6
1113endmenu
1114
1115
1116menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1117
1118config PCI
1119 bool "PCI support"
1120 depends on BROKEN
1121 help
1122 Support for PCI bus.
1123
1124source "drivers/pci/Kconfig"
1125
1126config HOTPLUG
1127 bool "Support for hot-pluggable device"
1128 help
1129 Say Y here if you want to plug devices into your computer while
1130 the system is running, and be able to use them quickly. In many
1131 cases, the devices can likewise be unplugged at any time too.
1132
1133 One well known example of this is PCMCIA- or PC-cards, credit-card
1134 size devices such as network cards, modems or hard drives which are
1135 plugged into slots found on all modern laptop computers. Another
1136 example, used on modern desktops as well as laptops, is USB.
1137
1138 Enable HOTPLUG and build a modular kernel. Get agent software
1139 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1140 Then your kernel will automatically call out to a user mode "policy
1141 agent" (/sbin/hotplug) to load modules and set up software needed
1142 to use devices as you hotplug them.
1143
1144source "drivers/pcmcia/Kconfig"
1145
1146source "drivers/pci/hotplug/Kconfig"
1147
1148endmenu
1149
1150menu "Executable file formats"
1151
1152source "fs/Kconfig.binfmt"
1153
1154endmenu
1155
1156menu "Power management options"
1157 depends on !SMP
1158
1159source "kernel/power/Kconfig"
1160
1161config ARCH_SUSPEND_POSSIBLE
1162 def_bool y
1163
1164choice
1165 prompt "Standby Power Saving Mode"
1166 depends on PM
1167 default PM_BFIN_SLEEP_DEEPER
1168config PM_BFIN_SLEEP_DEEPER
1169 bool "Sleep Deeper"
1170 help
1171 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1172 power dissipation by disabling the clock to the processor core (CCLK).
1173 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1174 to 0.85 V to provide the greatest power savings, while preserving the
1175 processor state.
1176 The PLL and system clock (SCLK) continue to operate at a very low
1177 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1178 the SDRAM is put into Self Refresh Mode. Typically an external event
1179 such as GPIO interrupt or RTC activity wakes up the processor.
1180 Various Peripherals such as UART, SPORT, PPI may not function as
1181 normal during Sleep Deeper, due to the reduced SCLK frequency.
1182 When in the sleep mode, system DMA access to L1 memory is not supported.
1183
1184 If unsure, select "Sleep Deeper".
1185
1186config PM_BFIN_SLEEP
1187 bool "Sleep"
1188 help
1189 Sleep Mode (High Power Savings) - The sleep mode reduces power
1190 dissipation by disabling the clock to the processor core (CCLK).
1191 The PLL and system clock (SCLK), however, continue to operate in
1192 this mode. Typically an external event or RTC activity will wake
1193 up the processor. When in the sleep mode, system DMA access to L1
1194 memory is not supported.
1195
1196 If unsure, select "Sleep Deeper".
1197endchoice
1198
1199config PM_WAKEUP_BY_GPIO
1200 bool "Allow Wakeup from Standby by GPIO"
1201 depends on PM && !BF54x
1202
1203config PM_WAKEUP_GPIO_NUMBER
1204 int "GPIO number"
1205 range 0 47
1206 depends on PM_WAKEUP_BY_GPIO
1207 default 2
1208
1209choice
1210 prompt "GPIO Polarity"
1211 depends on PM_WAKEUP_BY_GPIO
1212 default PM_WAKEUP_GPIO_POLAR_H
1213config PM_WAKEUP_GPIO_POLAR_H
1214 bool "Active High"
1215config PM_WAKEUP_GPIO_POLAR_L
1216 bool "Active Low"
1217config PM_WAKEUP_GPIO_POLAR_EDGE_F
1218 bool "Falling EDGE"
1219config PM_WAKEUP_GPIO_POLAR_EDGE_R
1220 bool "Rising EDGE"
1221config PM_WAKEUP_GPIO_POLAR_EDGE_B
1222 bool "Both EDGE"
1223endchoice
1224
1225comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1226 depends on PM
1227
1228config PM_BFIN_WAKE_PH6
1229 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1230 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1231 default n
1232 help
1233 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1234
1235config PM_BFIN_WAKE_GP
1236 bool "Allow Wake-Up from GPIOs"
1237 depends on PM && BF54x
1238 default n
1239 help
1240 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1241 (all processors, except ADSP-BF549). This option sets
1242 the general-purpose wake-up enable (GPWE) control bit to enable
1243 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1244 On ADSP-BF549 this option enables the the same functionality on the
1245 /MRXON pin also PH7.
1246
1247endmenu
1248
1249menu "CPU Frequency scaling"
1250 depends on !SMP
1251
1252source "drivers/cpufreq/Kconfig"
1253
1254config BFIN_CPU_FREQ
1255 bool
1256 depends on CPU_FREQ
1257 select CPU_FREQ_TABLE
1258 default y
1259
1260config CPU_VOLTAGE
1261 bool "CPU Voltage scaling"
1262 depends on EXPERIMENTAL
1263 depends on CPU_FREQ
1264 default n
1265 help
1266 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1267 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1268 manuals. There is a theoretical risk that during VDDINT transitions
1269 the PLL may unlock.
1270
1271endmenu
1272
1273source "net/Kconfig"
1274
1275source "drivers/Kconfig"
1276
1277source "fs/Kconfig"
1278
1279source "arch/blackfin/Kconfig.debug"
1280
1281source "security/Kconfig"
1282
1283source "crypto/Kconfig"
1284
1285source "lib/Kconfig"
1286
