LXR linux/arch/blackfin/include/asm/cacheflush.h

   1/*
   2 * Blackfin low-level cache routines
   3 *
   4 * Copyright 2004-2009 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#ifndef _BLACKFIN_CACHEFLUSH_H
  10#define _BLACKFIN_CACHEFLUSH_H
  11
  12#include <asm/blackfin.h>       /* for SSYNC() */
  13
  14extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
  15extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
  16extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
  17extern void blackfin_dflush_page(void *page);
  18extern void blackfin_invalidate_entire_dcache(void);
  19extern void blackfin_invalidate_entire_icache(void);
  20
  21#define flush_dcache_mmap_lock(mapping)         do { } while (0)
  22#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
  23#define flush_cache_mm(mm)                      do { } while (0)
  24#define flush_cache_range(vma, start, end)      do { } while (0)
  25#define flush_cache_page(vma, vmaddr)           do { } while (0)
  26#define flush_cache_vmap(start, end)            do { } while (0)
  27#define flush_cache_vunmap(start, end)          do { } while (0)
  28
  29#ifdef CONFIG_SMP
  30#define flush_icache_range_others(start, end)   \
  31        smp_icache_flush_range_others((start), (end))
  32#else
  33#define flush_icache_range_others(start, end)   do { } while (0)
  34#endif
  35
  36static inline void flush_icache_range(unsigned start, unsigned end)
  37{
  38#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  39        blackfin_dcache_flush_range(start, end);
  40#endif
  41
  42        /* Make sure all write buffers in the data side of the core
  43         * are flushed before trying to invalidate the icache.  This
  44         * needs to be after the data flush and before the icache
  45         * flush so that the SSYNC does the right thing in preventing
  46         * the instruction prefetcher from hitting things in cached
  47         * memory at the wrong time -- it runs much further ahead than
  48         * the pipeline.
  49         */
  50        SSYNC();
  51#if defined(CONFIG_BFIN_ICACHE)
  52        blackfin_icache_flush_range(start, end);
  53        flush_icache_range_others(start, end);
  54#endif
  55}
  56
  57#define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
  58do { memcpy(dst, src, len);                                             \
  59     flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len));    \
  60} while (0)
  61
  62#define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
  63
  64#if defined(CONFIG_BFIN_DCACHE)
  65# define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
  66#else
  67# define invalidate_dcache_range(start,end)     do { } while (0)
  68#endif
  69#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
  70# define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
  71# define flush_dcache_page(page)                blackfin_dflush_page(page_address(page))
  72#else
  73# define flush_dcache_range(start,end)          do { } while (0)
  74# define flush_dcache_page(page)                do { } while (0)
  75#endif
  76
  77extern unsigned long reserved_mem_dcache_on;
  78extern unsigned long reserved_mem_icache_on;
  79
  80static inline int bfin_addr_dcacheable(unsigned long addr)
  81{
  82#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
  83        if (addr < (_ramend - DMA_UNCACHED_REGION))
  84                return 1;
  85#endif
  86
  87        if (reserved_mem_dcache_on &&
  88                addr >= _ramend && addr < physical_mem_end)
  89                return 1;
  90
  91#ifdef CONFIG_BFIN_L2_DCACHEABLE
  92        if (addr >= L2_START && addr < L2_START + L2_LENGTH)
  93                return 1;
  94#endif
  95
  96        return 0;
  97}
  98
  99#endif                          /* _BLACKFIN_ICACHEFLUSH_H */
 100