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7#include <linux/serial.h>
8#include <asm/dma.h>
9#include <asm/portmux.h>
10
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
14#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
15#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
16#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18
19#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
20#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
21#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
22#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
23#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
24#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
25#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
26#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
27
28#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
29#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
30
31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
36
37#ifdef CONFIG_BFIN_UART0_CTSRTS
38# define CONFIG_SERIAL_BFIN_CTSRTS
39# ifndef CONFIG_UART0_CTS_PIN
40# define CONFIG_UART0_CTS_PIN -1
41# endif
42# ifndef CONFIG_UART0_RTS_PIN
43# define CONFIG_UART0_RTS_PIN -1
44# endif
45#endif
46
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49struct bfin_serial_port {
50 struct uart_port port;
51 unsigned int old_status;
52 int status_irq;
53 unsigned int lsr;
54#ifdef CONFIG_SERIAL_BFIN_DMA
55 int tx_done;
56 int tx_count;
57 struct circ_buf rx_dma_buf;
58 struct timer_list rx_dma_timer;
59 int rx_dma_nrows;
60 unsigned int tx_dma_channel;
61 unsigned int rx_dma_channel;
62 struct work_struct tx_dma_workqueue;
63#else
64# if ANOMALY_05000363
65 unsigned int anomaly_threshold;
66# endif
67#endif
68#ifdef CONFIG_SERIAL_BFIN_CTSRTS
69 struct timer_list cts_timer;
70 int cts_pin;
71 int rts_pin;
72#endif
73};
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77
78
79static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
80{
81 unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
82 uart->lsr |= (lsr & (BI|FE|PE|OE));
83 return lsr | uart->lsr;
84}
85
86static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
87{
88 uart->lsr = 0;
89 bfin_write16(uart->port.membase + OFFSET_LSR, -1);
90}
91
92struct bfin_serial_res {
93 unsigned long uart_base_addr;
94 int uart_irq;
95 int uart_status_irq;
96#ifdef CONFIG_SERIAL_BFIN_DMA
97 unsigned int uart_tx_dma_channel;
98 unsigned int uart_rx_dma_channel;
99#endif
100#ifdef CONFIG_SERIAL_BFIN_CTSRTS
101 int uart_cts_pin;
102 int uart_rts_pin;
103#endif
104};
105
106struct bfin_serial_res bfin_serial_resource[] = {
107 {
108 0xFFC00400,
109 IRQ_UART0_RX,
110 IRQ_UART0_ERROR,
111#ifdef CONFIG_SERIAL_BFIN_DMA
112 CH_UART0_TX,
113 CH_UART0_RX,
114#endif
115#ifdef CONFIG_SERIAL_BFIN_CTSRTS
116 CONFIG_UART0_CTS_PIN,
117 CONFIG_UART0_RTS_PIN,
118#endif
119 }
120};
121
122#define DRIVER_NAME "bfin-uart"
123