LXR linux/arch/blackfin/mach-bf537/dma.c

   1/*
   2 * Copyright 2007-2009 Analog Devices Inc.
   3 *
   4 * Licensed under the GPL-2 or later.
   5 *
   6 * This file contains the simple DMA Implementation for Blackfin
   7 */
   8
   9#include <linux/module.h>
  10
  11#include <asm/blackfin.h>
  12#include <asm/dma.h>
  13
  14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
  15        (struct dma_register *) DMA0_NEXT_DESC_PTR,
  16        (struct dma_register *) DMA1_NEXT_DESC_PTR,
  17        (struct dma_register *) DMA2_NEXT_DESC_PTR,
  18        (struct dma_register *) DMA3_NEXT_DESC_PTR,
  19        (struct dma_register *) DMA4_NEXT_DESC_PTR,
  20        (struct dma_register *) DMA5_NEXT_DESC_PTR,
  21        (struct dma_register *) DMA6_NEXT_DESC_PTR,
  22        (struct dma_register *) DMA7_NEXT_DESC_PTR,
  23        (struct dma_register *) DMA8_NEXT_DESC_PTR,
  24        (struct dma_register *) DMA9_NEXT_DESC_PTR,
  25        (struct dma_register *) DMA10_NEXT_DESC_PTR,
  26        (struct dma_register *) DMA11_NEXT_DESC_PTR,
  27        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
  28        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
  29        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
  30        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
  31};
  32EXPORT_SYMBOL(dma_io_base_addr);
  33
  34int channel2irq(unsigned int channel)
  35{
  36        int ret_irq = -1;
  37
  38        switch (channel) {
  39        case CH_PPI:
  40                ret_irq = IRQ_PPI;
  41                break;
  42
  43        case CH_EMAC_RX:
  44                ret_irq = IRQ_MAC_RX;
  45                break;
  46
  47        case CH_EMAC_TX:
  48                ret_irq = IRQ_MAC_TX;
  49                break;
  50
  51        case CH_UART1_RX:
  52                ret_irq = IRQ_UART1_RX;
  53                break;
  54
  55        case CH_UART1_TX:
  56                ret_irq = IRQ_UART1_TX;
  57                break;
  58
  59        case CH_SPORT0_RX:
  60                ret_irq = IRQ_SPORT0_RX;
  61                break;
  62
  63        case CH_SPORT0_TX:
  64                ret_irq = IRQ_SPORT0_TX;
  65                break;
  66
  67        case CH_SPORT1_RX:
  68                ret_irq = IRQ_SPORT1_RX;
  69                break;
  70
  71        case CH_SPORT1_TX:
  72                ret_irq = IRQ_SPORT1_TX;
  73                break;
  74
  75        case CH_SPI:
  76                ret_irq = IRQ_SPI;
  77                break;
  78
  79        case CH_UART0_RX:
  80                ret_irq = IRQ_UART0_RX;
  81                break;
  82
  83        case CH_UART0_TX:
  84                ret_irq = IRQ_UART0_TX;
  85                break;
  86
  87        case CH_MEM_STREAM0_SRC:
  88        case CH_MEM_STREAM0_DEST:
  89                ret_irq = IRQ_MEM_DMA0;
  90                break;
  91
  92        case CH_MEM_STREAM1_SRC:
  93        case CH_MEM_STREAM1_DEST:
  94                ret_irq = IRQ_MEM_DMA1;
  95                break;
  96        }
  97        return ret_irq;
  98}
  99