LXR linux/arch/blackfin/mach-bf537/include/mach/bfin_serial

   1/*
   2 * Copyright 2006-2009 Analog Devices Inc.
   3 *
   4 * Licensed under the GPL-2 or later
   5 */
   6
   7#include <linux/serial.h>
   8#include <asm/dma.h>
   9#include <asm/portmux.h>
  10
  11#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  12#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  13#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  14#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  15#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  16#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  17#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  18
  19#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  20#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  21#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
  22#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
  23#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
  24#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  25#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  26#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  27
  28#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
  29#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
  30
  31#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
  32#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
  33#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
  34#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
  35#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
  36
  37#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  38# define CONFIG_SERIAL_BFIN_CTSRTS
  39
  40# ifndef CONFIG_UART0_CTS_PIN
  41#  define CONFIG_UART0_CTS_PIN -1
  42# endif
  43
  44# ifndef CONFIG_UART0_RTS_PIN
  45#  define CONFIG_UART0_RTS_PIN -1
  46# endif
  47
  48# ifndef CONFIG_UART1_CTS_PIN
  49#  define CONFIG_UART1_CTS_PIN -1
  50# endif
  51
  52# ifndef CONFIG_UART1_RTS_PIN
  53#  define CONFIG_UART1_RTS_PIN -1
  54# endif
  55#endif
  56
  57#define BFIN_UART_TX_FIFO_SIZE  2
  58
  59/*
  60 * The pin configuration is different from schematic
  61 */
  62struct bfin_serial_port {
  63        struct uart_port        port;
  64        unsigned int            old_status;
  65        int                     status_irq;
  66        unsigned int lsr;
  67#ifdef CONFIG_SERIAL_BFIN_DMA
  68        int                     tx_done;
  69        int                     tx_count;
  70        struct circ_buf         rx_dma_buf;
  71        struct timer_list       rx_dma_timer;
  72        int                     rx_dma_nrows;
  73        unsigned int            tx_dma_channel;
  74        unsigned int            rx_dma_channel;
  75        struct work_struct      tx_dma_workqueue;
  76#endif
  77#ifdef CONFIG_SERIAL_BFIN_CTSRTS
  78        int             cts_pin;
  79        int             rts_pin;
  80#endif
  81};
  82
  83/* The hardware clears the LSR bits upon read, so we need to cache
  84 * some of the more fun bits in software so they don't get lost
  85 * when checking the LSR in other code paths (TX).
  86 */
  87static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
  88{
  89        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
  90        uart->lsr |= (lsr & (BI|FE|PE|OE));
  91        return lsr | uart->lsr;
  92}
  93
  94static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
  95{
  96        uart->lsr = 0;
  97        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
  98}
  99
 100struct bfin_serial_res {
 101        unsigned long   uart_base_addr;
 102        int             uart_irq;
 103        int             uart_status_irq;
 104#ifdef CONFIG_SERIAL_BFIN_DMA
 105        unsigned int    uart_tx_dma_channel;
 106        unsigned int    uart_rx_dma_channel;
 107#endif
 108#ifdef CONFIG_SERIAL_BFIN_CTSRTS
 109        int     uart_cts_pin;
 110        int     uart_rts_pin;
 111#endif
 112};
 113
 114struct bfin_serial_res bfin_serial_resource[] = {
 115#ifdef CONFIG_SERIAL_BFIN_UART0
 116        {
 117        0xFFC00400,
 118        IRQ_UART0_RX,
 119        IRQ_UART0_ERROR,
 120#ifdef CONFIG_SERIAL_BFIN_DMA
 121        CH_UART0_TX,
 122        CH_UART0_RX,
 123#endif
 124#ifdef CONFIG_SERIAL_BFIN_CTSRTS
 125        CONFIG_UART0_CTS_PIN,
 126        CONFIG_UART0_RTS_PIN,
 127#endif
 128        },
 129#endif
 130#ifdef CONFIG_SERIAL_BFIN_UART1
 131        {
 132        0xFFC02000,
 133        IRQ_UART1_RX,
 134        IRQ_UART1_ERROR,
 135#ifdef CONFIG_SERIAL_BFIN_DMA
 136        CH_UART1_TX,
 137        CH_UART1_RX,
 138#endif
 139#ifdef CONFIG_SERIAL_BFIN_CTSRTS
 140        CONFIG_UART1_CTS_PIN,
 141        CONFIG_UART1_RTS_PIN,
 142#endif
 143        },
 144#endif
 145};
 146
 147#define DRIVER_NAME "bfin-uart"
 148