1/* 2 * Copyright 2005-2008 Analog Devices Inc. 3 * 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 5 */ 6 7#ifndef _DEF_BF534_H 8#define _DEF_BF534_H 9 10/* Include all Core registers and bit definitions */ 11#include <asm/def_LPBlackfin.h> 12 13/************************************************************************************ 14** System MMR Register Map 15*************************************************************************************/ 16/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 17#define PLL_CTL 0xFFC00000 /* PLL Control Register */ 18#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ 19#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ 20#define PLL_STAT 0xFFC0000C /* PLL Status Register */ 21#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ 22#define CHIPID 0xFFC00014 /* Chip ID Register */ 23 24/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 25#define SWRST 0xFFC00100 /* Software Reset Register */ 26#define SYSCR 0xFFC00104 /* System Configuration Register */ 27#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ 28#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ 29#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 30#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 31#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 32#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 33#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ 34#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ 35 36/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 37#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ 38#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ 39#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ 40 41/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ 42#define RTC_STAT 0xFFC00300 /* RTC Status Register */ 43#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ 44#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ 45#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ 46#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ 47#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ 48#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */ 49 50/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ 51#define UART0_THR 0xFFC00400 /* Transmit Holding register */ 52#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ 53#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 54#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ 55#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 56#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ 57#define UART0_LCR 0xFFC0040C /* Line Control Register */ 58#define UART0_MCR 0xFFC00410 /* Modem Control Register */ 59#define UART0_LSR 0xFFC00414 /* Line Status Register */ 60#define UART0_MSR 0xFFC00418 /* Modem Status Register */ 61#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ 62#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 63 64/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 65#define SPI0_REGBASE 0xFFC00500 66#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 67#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 68#define SPI_STAT 0xFFC00508 /* SPI Status register */ 69#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ 70#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ 71#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ 72#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ 73 74/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ 75#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ 76#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ 77#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ 78#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ 79 80#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ 81#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ 82#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ 83#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ 84 85#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ 86#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ 87#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ 88#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ 89 90#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ 91#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ 92#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ 93#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ 94 95#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ 96#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ 97#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ 98#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ 99 100#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ 101#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ 102#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ 103#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ 104 105#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ 106#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ 107#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ 108#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ 109 110#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ 111#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ 112#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ 113#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ 114 115#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ 116#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ 117#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ 118 119/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ 120#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ 121#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ 122#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ 123#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ 124#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ 125#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ 126#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ 127#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ 128#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ 129#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ 130#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ 131#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ 132#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ 133#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ 134#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ 135#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ 136#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ 137 138/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 139#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 140#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 141#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 142#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 143#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 144#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 145#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 146#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 147#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 148#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 149#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 150#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 151#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 152#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 153#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 154#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 155#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 156#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 157#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 158#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 159#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 160#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 161 162/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 163#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 164#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 165#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 166#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 167#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 168#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 169#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 170#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 171#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 172#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 173#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 174#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 175#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 176#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 177#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 178#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 179#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 180#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 181#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 182#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 183#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 184#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 185 186/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 187#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 188#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ 189#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ 190#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ 191#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ 192#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ 193#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 194 195/* DMA Traffic Control Registers */ 196#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 197#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 198 199/* Alternate deprecated register names (below) provided for backwards code compatibility */ 200#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ 201#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 202 203/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 204#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 205#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ 206#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 207#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ 208#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ 209#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ 210#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ 211#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 212#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 213#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ 214#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ 215#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 216#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 217 218#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ 219#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ 220#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ 221#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ 222#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ 223#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ 224#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ 225#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 226#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 227#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ 228#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ 229#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 230#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 231 232#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ 233#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ 234#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ 235#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ 236#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ 237#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ 238#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ 239#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 240#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 241#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ 242#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ 243#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 244#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 245 246#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ 247#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ 248#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ 249#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ 250#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ 251#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ 252#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ 253#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 254#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 255#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ 256#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ 257#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 258#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 259 260#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ 261#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ 262#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ 263#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ 264#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ 265#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ 266#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ 267#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 268#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 269#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ 270#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ 271#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 272#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 273 274#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ 275#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ 276#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ 277#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ 278#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ 279#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ 280#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ 281#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 282#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 283#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ 284#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ 285#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 286#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 287 288#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ 289#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ 290#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ 291#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ 292#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ 293#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ 294#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ 295#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 296#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 297#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ 298#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ 299#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 300#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 301 302#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ 303#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ 304#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ 305#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ 306#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ 307#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ 308#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ 309#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 310#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 311#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ 312#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ 313#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 314#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 315 316#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ 317#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ 318#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ 319#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ 320#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ 321#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ 322#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ 323#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ 324#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ 325#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ 326#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ 327#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ 328#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ 329 330#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ 331#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ 332#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ 333#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ 334#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ 335#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ 336#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ 337#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ 338#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ 339#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ 340#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ 341#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ 342#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ 343 344#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ 345#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ 346#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ 347#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ 348#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ 349#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ 350#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ 351#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 352#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ 353#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ 354#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ 355#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ 356#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ 357 358#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ 359#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ 360#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ 361#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ 362#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ 363#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ 364#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ 365#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 366#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ 367#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ 368#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ 369#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ 370#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ 371 372#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ 373#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ 374#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ 375#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ 376#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ 377#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ 378#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ 379#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 380#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ 381#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ 382#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ 383#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ 384#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ 385 386#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ 387#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ 388#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ 389#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ 390#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ 391#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ 392#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ 393#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 394#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ 395#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ 396#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ 397#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ 398#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ 399 400#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ 401#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ 402#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ 403#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ 404#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ 405#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ 406#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ 407#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 408#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ 409#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ 410#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ 411#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ 412#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 413 414#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ 415#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ 416#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ 417#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ 418#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ 419#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ 420#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ 421#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 422#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ 423#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ 424#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ 425#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ 426#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ 427 428/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ 429#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 430#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ 431#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ 432#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ 433#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 434 435/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 436#define TWI0_REGBASE 0xFFC01400 437#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 438#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 439#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 440#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 441#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 442#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 443#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 444#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 445#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ 446#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ 447#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 448#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 449#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 450#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 451#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 452#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 453 454/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 455#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ 456#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ 457#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ 458#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ 459#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ 460#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ 461#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ 462#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ 463#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ 464#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ 465#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ 466#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ 467#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ 468#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ 469#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ 470#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ 471#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ 472 473/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ 474#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ 475#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ 476#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ 477#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ 478#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ 479#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ 480#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ 481#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ 482#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ 483#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ 484#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ 485#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ 486#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ 487#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ 488#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ 489#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ 490#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ 491 492/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ 493#define UART1_THR 0xFFC02000 /* Transmit Holding register */ 494#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ 495#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ 496#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ 497#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ 498#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ 499#define UART1_LCR 0xFFC0200C /* Line Control Register */ 500#define UART1_MCR 0xFFC02010 /* Modem Control Register */ 501#define UART1_LSR 0xFFC02014 /* Line Status Register */ 502#define UART1_MSR 0xFFC02018 /* Modem Status Register */ 503#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ 504#define UART1_GCTL 0xFFC02024 /* Global Control Register */ 505 506/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ 507/* For Mailboxes 0-15 */ 508#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ 509#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ 510#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ 511#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ 512#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ 513#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ 514#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ 515#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ 516#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ 517#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ 518#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ 519#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ 520#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */ 521 522/* For Mailboxes 16-31 */ 523#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ 524#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ 525#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ 526#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ 527#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ 528#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ 529#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ 530#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ 531#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ 532#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ 533#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ 534#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ 535#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */ 536 537/* CAN Configuration, Control, and Status Registers */ 538#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ 539#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ 540#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ 541#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ 542#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ 543#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ 544#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ 545#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ 546#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ 547#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ 548 549#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ 550#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ 551#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ 552#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ 553#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ 554#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ 555#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ 556 557/* Mailbox Acceptance Masks */ 558#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ 559#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ 560#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ 561#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ 562#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ 563#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ 564#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ 565#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ 566#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ 567#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ 568#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ 569#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ 570#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ 571#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ 572#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ 573#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ 574#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ 575#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ 576#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ 577#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ 578#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ 579#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ 580#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ 581#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ 582#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ 583#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ 584#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ 585#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ 586#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ 587#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ 588#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ 589#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ 590 591#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ 592#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ 593#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ 594#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ 595#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ 596#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ 597#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ 598#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ 599#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ 600#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ 601#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ 602#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ 603#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ 604#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ 605#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ 606#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ 607#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ 608#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ 609#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ 610#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ 611#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ 612#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ 613#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ 614#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ 615#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ 616#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ 617#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ 618#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ 619#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ 620#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ 621#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ 622#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ 623 624/* CAN Acceptance Mask Macros */ 625#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) 626#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) 627 628/* Mailbox Registers */ 629#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ 630#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ 631#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ 632#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ 633#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ 634#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ 635#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ 636#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ 637 638#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ 639#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ 640#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ 641#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ 642#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ 643#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ 644#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ 645#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ 646 647#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ 648#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ 649#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ 650#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ 651#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ 652#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ 653#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ 654#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ 655 656#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ 657#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ 658#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ 659#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ 660#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ 661#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ 662#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ 663#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ 664 665#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ 666#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ 667#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ 668#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ 669#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ 670#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ 671#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ 672#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ 673 674#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ 675#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ 676#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ 677#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ 678#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ 679#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ 680#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ 681#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ 682 683#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ 684#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ 685#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ 686#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ 687#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ 688#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ 689#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ 690#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ 691 692#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ 693#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ 694#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ 695#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ 696#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ 697#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ 698#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ 699#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ 700 701#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ 702#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ 703#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ 704#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ 705#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ 706#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ 707#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ 708#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ 709 710#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ 711#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ 712#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ 713#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ 714#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ 715#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ 716#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ 717#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ 718 719#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ 720#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ 721#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ 722#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ 723#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ 724#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ 725#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ 726#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ 727 728#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ 729#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ 730#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ 731#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ 732#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ 733#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ 734#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ 735#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ 736 737#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ 738#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ 739#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ 740#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ 741#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ 742#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ 743#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ 744#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ 745 746#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ 747#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ 748#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ 749#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ 750#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ 751#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ 752#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ 753#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ 754 755#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ 756#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ 757#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ 758#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ 759#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ 760#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ 761#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ 762#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ 763 764#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ 765#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ 766#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ 767#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ 768#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ 769#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ 770#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ 771#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ 772 773#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ 774#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ 775#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ 776#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ 777#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ 778#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ 779#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ 780#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ 781 782#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ 783#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ 784#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ 785#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ 786#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ 787#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ 788#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ 789#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ 790 791#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ 792#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ 793#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ 794#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ 795#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ 796#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ 797#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ 798#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ 799 800#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ 801#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ 802#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ 803#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ 804#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ 805#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ 806#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ 807#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ 808 809#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ 810#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ 811#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ 812#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ 813#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ 814#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ 815#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ 816#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ 817 818#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ 819#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ 820#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ 821#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ 822#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ 823#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ 824#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ 825#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ 826 827#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ 828#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ 829#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ 830#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ 831#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ 832#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ 833#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ 834#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ 835 836#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ 837#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ 838#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ 839#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ 840#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ 841#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ 842#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ 843#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ 844 845#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ 846#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ 847#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ 848#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ 849#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ 850#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ 851#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ 852#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ 853 854#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ 855#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ 856#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ 857#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ 858#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ 859#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ 860#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ 861#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ 862 863#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ 864#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ 865#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ 866#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ 867#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ 868#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ 869#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ 870#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ 871 872#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ 873#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ 874#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ 875#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ 876#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ 877#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ 878#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ 879#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ 880 881#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ 882#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ 883#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ 884#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ 885#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ 886#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ 887#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ 888#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ 889 890#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ 891#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ 892#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ 893#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ 894#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ 895#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ 896#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ 897#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ 898 899#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ 900#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ 901#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ 902#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ 903#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ 904#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ 905#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ 906#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ 907 908#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ 909#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ 910#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ 911#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ 912#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ 913#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ 914#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ 915#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ 916 917/* CAN Mailbox Area Macros */ 918#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) 919#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) 920#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) 921#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) 922#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) 923#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) 924#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) 925#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) 926 927/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ 928#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ 929#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ 930#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ 931#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ 932 933/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ 934#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ 935#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ 936#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ 937#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ 938#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ 939#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 940#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 941 942#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ 943#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ 944#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ 945#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ 946#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ 947#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 948#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ 949 950/*********************************************************************************** 951** System MMR Register Bits And Macros 952** 953** Disclaimer: All macros are intended to make C and Assembly code more readable. 954** Use these macros carefully, as any that do left shifts for field 955** depositing will result in the lower order bits being destroyed. Any 956** macro that shifts left to properly position the bit-field should be 957** used as part of an OR to initialize a register and NOT as a dynamic 958** modifier UNLESS the lower order bits are saved and ORed back in when 959** the macro is used. 960*************************************************************************************/ 961/* 962** ********************* PLL AND RESET MASKS ****************************************/ 963/* PLL_CTL Masks */ 964#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 965#define PLL_OFF 0x0002 /* PLL Not Powered */ 966#define STOPCK 0x0008 /* Core Clock Off */ 967#define PDWN 0x0020 /* Enter Deep Sleep Mode */ 968#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ 969#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ 970#define BYPASS 0x0100 /* Bypass the PLL */ 971#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ 972/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ 973#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ 974 975/* PLL_DIV Masks */ 976#define SSEL 0x000F /* System Select */ 977#define CSEL 0x0030 /* Core Select */ 978#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ 979#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ 980#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ 981#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ 982/* PLL_DIV Macros */ 983#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ 984 985/* VR_CTL Masks */ 986#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ 987#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 988#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 989#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 990#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 991 992#define GAIN 0x000C /* Voltage Level Gain */ 993#define GAIN_5 0x0000 /* GAIN = 5 */ 994#define GAIN_10 0x0004 /* GAIN = 10 */ 995#define GAIN_20 0x0008 /* GAIN = 20 */ 996#define GAIN_50 0x000C /* GAIN = 50 */ 997 998#define VLEV 0x00F0 /* Internal Voltage Level */ 999#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 1000#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
1001#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 1002#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 1003#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 1004#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 1005#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 1006#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 1007#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 1008#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 1009 1010#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 1011#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 1012#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 1013#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ 1014#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ 1015#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ 1016 1017/* PLL_STAT Masks */ 1018#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 1019#define FULL_ON 0x0002 /* Processor In Full On Mode */ 1020#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 1021#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 1022 1023/* CHIPID Masks */ 1024#define CHIPID_VERSION 0xF0000000 1025#define CHIPID_FAMILY 0x0FFFF000 1026#define CHIPID_MANUFACTURE 0x00000FFE 1027 1028/* SWRST Masks */ 1029#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1030#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1031#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ 1032#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 1033#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1034 1035/* SYSCR Masks */ 1036#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */ 1037#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ 1038 1039/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ 1040 1041/* SIC_IAR0 Macros */ 1042#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ 1043#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ 1044#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ 1045#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */ 1046#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ 1047#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ 1048#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ 1049#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ 1050 1051/* SIC_IAR1 Macros */ 1052#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */ 1053#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ 1054#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ 1055#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */ 1056#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ 1057#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ 1058#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ 1059#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ 1060 1061/* SIC_IAR2 Macros */ 1062#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */ 1063#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ 1064#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ 1065#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */ 1066#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ 1067#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ 1068#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ 1069#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ 1070 1071/* SIC_IAR3 Macros */ 1072#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */ 1073#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */ 1074#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */ 1075#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */ 1076#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */ 1077#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */ 1078#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */ 1079#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */ 1080 1081/* SIC_IMASK Masks */ 1082#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ 1083#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ 1084#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ 1085#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ 1086 1087/* SIC_IWR Masks */ 1088#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1089#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 1090#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1091#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1092 1093/* ************** UART CONTROLLER MASKS *************************/ 1094/* UARTx_LCR Masks */ 1095#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 1096#define STB 0x04 /* Stop Bits */ 1097#define PEN 0x08 /* Parity Enable */ 1098#define EPS 0x10 /* Even Parity Select */ 1099#define STP 0x20 /* Stick Parity */ 1100#define SB 0x40 /* Set Break */ 1101#define DLAB 0x80 /* Divisor Latch Access */ 1102 1103/* UARTx_MCR Mask */ 1104#define LOOP_ENA 0x10 /* Loopback Mode Enable */ 1105#define LOOP_ENA_P 0x04 1106/* UARTx_LSR Masks */ 1107#define DR 0x01 /* Data Ready */ 1108#define OE 0x02 /* Overrun Error */ 1109#define PE 0x04 /* Parity Error */ 1110#define FE 0x08 /* Framing Error */ 1111#define BI 0x10 /* Break Interrupt */ 1112#define THRE 0x20 /* THR Empty */ 1113#define TEMT 0x40 /* TSR and UART_THR Empty */ 1114 1115/* UARTx_IER Masks */ 1116#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ 1117#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ 1118#define ELSI 0x04 /* Enable RX Status Interrupt */ 1119 1120/* UARTx_IIR Masks */ 1121#define NINT 0x01 /* Pending Interrupt */ 1122#define IIR_TX_READY 0x02 /* UART_THR empty */ 1123#define IIR_RX_READY 0x04 /* Receive data ready */ 1124#define IIR_LINE_CHANGE 0x06 /* Receive line status */ 1125#define IIR_STATUS 0x06 1126 1127/* UARTx_GCTL Masks */ 1128#define UCEN 0x01 /* Enable UARTx Clocks */ 1129#define IREN 0x02 /* Enable IrDA Mode */ 1130#define TPOLC 0x04 /* IrDA TX Polarity Change */ 1131#define RPOLC 0x08 /* IrDA RX Polarity Change */ 1132#define FPE 0x10 /* Force Parity Error On Transmit */ 1133#define FFE 0x20 /* Force Framing Error On Transmit */ 1134 1135/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ 1136/* SPI_CTL Masks */ 1137#define TIMOD 0x0003 /* Transfer Initiate Mode */ 1138#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ 1139#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ 1140#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ 1141#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ 1142#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ 1143#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ 1144#define PSSE 0x0010 /* Slave-Select Input Enable */ 1145#define EMISO 0x0020 /* Enable MISO As Output */ 1146#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ 1147#define LSBF 0x0200 /* LSB First */ 1148#define CPHA 0x0400 /* Clock Phase */ 1149#define CPOL 0x0800 /* Clock Polarity */ 1150#define MSTR 0x1000 /* Master/Slave* */ 1151#define WOM 0x2000 /* Write Open Drain Master */ 1152#define SPE 0x4000 /* SPI Enable */ 1153 1154/* SPI_FLG Masks */ 1155#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ 1156#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ 1157#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ 1158#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ 1159#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ 1160#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ 1161#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ 1162#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ 1163#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ 1164#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ 1165#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ 1166#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ 1167#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ 1168#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ 1169 1170/* SPI_STAT Masks */ 1171#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ 1172#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ 1173#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ 1174#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ 1175#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ 1176#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ 1177#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ 1178 1179/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1180/* TIMER_ENABLE Masks */ 1181#define TIMEN0 0x0001 /* Enable Timer 0 */ 1182#define TIMEN1 0x0002 /* Enable Timer 1 */ 1183#define TIMEN2 0x0004 /* Enable Timer 2 */ 1184#define TIMEN3 0x0008 /* Enable Timer 3 */ 1185#define TIMEN4 0x0010 /* Enable Timer 4 */ 1186#define TIMEN5 0x0020 /* Enable Timer 5 */ 1187#define TIMEN6 0x0040 /* Enable Timer 6 */ 1188#define TIMEN7 0x0080 /* Enable Timer 7 */ 1189 1190/* TIMER_DISABLE Masks */ 1191#define TIMDIS0 TIMEN0 /* Disable Timer 0 */ 1192#define TIMDIS1 TIMEN1 /* Disable Timer 1 */ 1193#define TIMDIS2 TIMEN2 /* Disable Timer 2 */ 1194#define TIMDIS3 TIMEN3 /* Disable Timer 3 */ 1195#define TIMDIS4 TIMEN4 /* Disable Timer 4 */ 1196#define TIMDIS5 TIMEN5 /* Disable Timer 5 */ 1197#define TIMDIS6 TIMEN6 /* Disable Timer 6 */ 1198#define TIMDIS7 TIMEN7 /* Disable Timer 7 */ 1199 1200/* TIMER_STATUS Masks */ 1201#define TIMIL0 0x00000001 /* Timer 0 Interrupt */ 1202#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ 1203#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ 1204#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ 1205#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ 1206#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ 1207#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ 1208#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ 1209#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ 1210#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ 1211#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ 1212#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ 1213#define TIMIL4 0x00010000 /* Timer 4 Interrupt */ 1214#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ 1215#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ 1216#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ 1217#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ 1218#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ 1219#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ 1220#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ 1221#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 1222#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 1223#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 1224#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 1225 1226/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 1227#define TOVL_ERR0 TOVF_ERR0 1228#define TOVL_ERR1 TOVF_ERR1 1229#define TOVL_ERR2 TOVF_ERR2 1230#define TOVL_ERR3 TOVF_ERR3 1231#define TOVL_ERR4 TOVF_ERR4 1232#define TOVL_ERR5 TOVF_ERR5 1233#define TOVL_ERR6 TOVF_ERR6 1234#define TOVL_ERR7 TOVF_ERR7 1235/* TIMERx_CONFIG Masks */ 1236#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ 1237#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ 1238#define EXT_CLK 0x0003 /* External Clock Mode */ 1239#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ 1240#define PERIOD_CNT 0x0008 /* Period Count */ 1241#define IRQ_ENA 0x0010 /* Interrupt Request Enable */ 1242#define TIN_SEL 0x0020 /* Timer Input Select */ 1243#define OUT_DIS 0x0040 /* Output Pad Disable */ 1244#define CLK_SEL 0x0080 /* Timer Clock Select */ 1245#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ 1246#define EMU_RUN 0x0200 /* Emulation Behavior Select */ 1247#define ERR_TYP 0xC000 /* Error Type */ 1248 1249/* ****************** GPIO PORTS F, G, H MASKS ***********************/ 1250/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ 1251/* Port F Masks */ 1252#define PF0 0x0001 1253#define PF1 0x0002 1254#define PF2 0x0004 1255#define PF3 0x0008 1256#define PF4 0x0010 1257#define PF5 0x0020 1258#define PF6 0x0040 1259#define PF7 0x0080 1260#define PF8 0x0100 1261#define PF9 0x0200 1262#define PF10 0x0400 1263#define PF11 0x0800 1264#define PF12 0x1000 1265#define PF13 0x2000 1266#define PF14 0x4000 1267#define PF15 0x8000 1268 1269/* Port G Masks */ 1270#define PG0 0x0001 1271#define PG1 0x0002 1272#define PG2 0x0004 1273#define PG3 0x0008 1274#define PG4 0x0010 1275#define PG5 0x0020 1276#define PG6 0x0040 1277#define PG7 0x0080 1278#define PG8 0x0100 1279#define PG9 0x0200 1280#define PG10 0x0400 1281#define PG11 0x0800 1282#define PG12 0x1000 1283#define PG13 0x2000 1284#define PG14 0x4000 1285#define PG15 0x8000 1286 1287/* Port H Masks */ 1288#define PH0 0x0001 1289#define PH1 0x0002 1290#define PH2 0x0004 1291#define PH3 0x0008 1292#define PH4 0x0010 1293#define PH5 0x0020 1294#define PH6 0x0040 1295#define PH7 0x0080 1296#define PH8 0x0100 1297#define PH9 0x0200 1298#define PH10 0x0400 1299#define PH11 0x0800 1300#define PH12 0x1000 1301#define PH13 0x2000 1302#define PH14 0x4000 1303#define PH15 0x8000 1304 1305/* ******************* SERIAL PORT MASKS **************************************/ 1306/* SPORTx_TCR1 Masks */ 1307#define TSPEN 0x0001 /* Transmit Enable */ 1308#define ITCLK 0x0002 /* Internal Transmit Clock Select */ 1309#define DTYPE_NORM 0x0004 /* Data Format Normal */ 1310#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 1311#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 1312#define TLSBIT 0x0010 /* Transmit Bit Order */ 1313#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ 1314#define TFSR 0x0400 /* Transmit Frame Sync Required Select */ 1315#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ 1316#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ 1317#define LATFS 0x2000 /* Late Transmit Frame Sync Select */ 1318#define TCKFE 0x4000 /* Clock Falling Edge Select */ 1319 1320/* SPORTx_TCR2 Masks and Macro */ 1321#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ 1322#define TXSE 0x0100 /* TX Secondary Enable */ 1323#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ 1324#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ 1325 1326/* SPORTx_RCR1 Masks */ 1327#define RSPEN 0x0001 /* Receive Enable */ 1328#define IRCLK 0x0002 /* Internal Receive Clock Select */ 1329#define DTYPE_NORM 0x0004 /* Data Format Normal */ 1330#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 1331#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 1332#define RLSBIT 0x0010 /* Receive Bit Order */ 1333#define IRFS 0x0200 /* Internal Receive Frame Sync Select */ 1334#define RFSR 0x0400 /* Receive Frame Sync Required Select */ 1335#define LRFS 0x1000 /* Low Receive Frame Sync Select */ 1336#define LARFS 0x2000 /* Late Receive Frame Sync Select */ 1337#define RCKFE 0x4000 /* Clock Falling Edge Select */ 1338 1339/* SPORTx_RCR2 Masks */ 1340#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ 1341#define RXSE 0x0100 /* RX Secondary Enable */ 1342#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ 1343#define RRFST 0x0400 /* Right-First Data Order */ 1344 1345/* SPORTx_STAT Masks */ 1346#define RXNE 0x0001 /* Receive FIFO Not Empty Status */ 1347#define RUVF 0x0002 /* Sticky Receive Underflow Status */ 1348#define ROVF 0x0004 /* Sticky Receive Overflow Status */ 1349#define TXF 0x0008 /* Transmit FIFO Full Status */ 1350#define TUVF 0x0010 /* Sticky Transmit Underflow Status */ 1351#define TOVF 0x0020 /* Sticky Transmit Overflow Status */ 1352#define TXHRE 0x0040 /* Transmit Hold Register Empty */ 1353 1354/* SPORTx_MCMC1 Macros */ 1355#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ 1356 1357/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ 1358#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ 1359 1360/* SPORTx_MCMC2 Masks */ 1361#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ 1362#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ 1363#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ 1364#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ 1365#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ 1366#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ 1367#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ 1368#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ 1369#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ 1370#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ 1371#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ 1372#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ 1373#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ 1374#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ 1375#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ 1376#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ 1377#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ 1378#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ 1379#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ 1380#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ 1381#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ 1382#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ 1383#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ 1384 1385/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/ 1386/* EBIU_AMGCTL Masks */ 1387#define AMCKEN 0x0001 /* Enable CLKOUT */ 1388#define AMBEN_NONE 0x0000 /* All Banks Disabled */ 1389#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */ 1390#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */ 1391#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */ 1392#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */ 1393 1394/* EBIU_AMBCTL0 Masks */ 1395#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */ 1396#define B0RDYPOL 0x00000002 /* B0 RDY Active High */ 1397#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */ 1398#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */ 1399#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */ 1400#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ 1401#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ 1402#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ 1403#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ 1404#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ 1405#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ 1406#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ 1407#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ 1408#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ 1409#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */ 1410#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */ 1411#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */ 1412#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */ 1413#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */ 1414#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */ 1415#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */ 1416#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */ 1417#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */ 1418#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */ 1419#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */ 1420#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */ 1421#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */ 1422#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */ 1423#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */ 1424#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */ 1425#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */ 1426#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */ 1427#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */ 1428#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */ 1429#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */ 1430#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */ 1431#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */ 1432#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */ 1433#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */ 1434#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */ 1435#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */ 1436#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */ 1437#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */ 1438#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */ 1439 1440#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */ 1441#define B1RDYPOL 0x00020000 /* B1 RDY Active High */ 1442#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */ 1443#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */ 1444#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */ 1445#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */ 1446#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */ 1447#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */ 1448#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */ 1449#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */ 1450#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */ 1451#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */ 1452#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */ 1453#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */ 1454#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */ 1455#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */ 1456#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */ 1457#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */ 1458#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */ 1459#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */ 1460#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */ 1461#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */ 1462#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */ 1463#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */ 1464#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */ 1465#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */ 1466#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */ 1467#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */ 1468#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */ 1469#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */ 1470#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */ 1471#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */ 1472#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */ 1473#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */ 1474#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */ 1475#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */ 1476#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */ 1477#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */ 1478#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */ 1479#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */ 1480#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */ 1481#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */ 1482#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */ 1483#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */ 1484 1485/* EBIU_AMBCTL1 Masks */ 1486#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */ 1487#define B2RDYPOL 0x00000002 /* B2 RDY Active High */ 1488#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */ 1489#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */ 1490#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */ 1491#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */ 1492#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */ 1493#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */ 1494#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */ 1495#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */ 1496#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */ 1497#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */ 1498#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */ 1499#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */ 1500#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */ 1501#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */ 1502#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */ 1503#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */ 1504#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */ 1505#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */ 1506#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */ 1507#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */ 1508#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */ 1509#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */ 1510#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */ 1511#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */ 1512#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */ 1513#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */ 1514#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */ 1515#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */ 1516#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */ 1517#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */ 1518#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */ 1519#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */ 1520#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */ 1521#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */ 1522#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */ 1523#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */ 1524#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */ 1525#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */ 1526#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */ 1527#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */ 1528#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */ 1529#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */ 1530 1531#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */ 1532#define B3RDYPOL 0x00020000 /* B3 RDY Active High */ 1533#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */ 1534#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */ 1535#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */ 1536#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */ 1537#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */ 1538#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */ 1539#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */ 1540#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */ 1541#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */ 1542#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */ 1543#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */ 1544#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */ 1545#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */ 1546#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */ 1547#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */ 1548#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */ 1549#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */ 1550#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */ 1551#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */ 1552#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */ 1553#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */ 1554#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */ 1555#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */ 1556#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */ 1557#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */ 1558#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */ 1559#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */ 1560#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */ 1561#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */ 1562#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */ 1563#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */ 1564#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */ 1565#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */ 1566#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */ 1567#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */ 1568#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */ 1569#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */ 1570#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */ 1571#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */ 1572#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */ 1573#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */ 1574#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */ 1575 1576/* ********************** SDRAM CONTROLLER MASKS **********************************************/ 1577/* EBIU_SDGCTL Masks */ 1578#define SCTLE 0x00000001 /* Enable SDRAM Signals */ 1579#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */ 1580#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */ 1581#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ 1582#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ 1583#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ 1584#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 1585#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 1586#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 1587#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ 1588#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ 1589#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ 1590#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ 1591#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ 1592#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ 1593#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ 1594#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ 1595#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ 1596#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ 1597#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ 1598#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ 1599#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ 1600#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ 1601#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ 1602#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ 1603#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ 1604#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ 1605#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ 1606#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ 1607#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ 1608#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ 1609#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ 1610#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ 1611#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ 1612#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ 1613#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ 1614#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ 1615#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ 1616#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */ 1617#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */ 1618#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */ 1619#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */ 1620#define EBUFE 0x02000000 /* Enable External Buffering Timing */ 1621#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */ 1622#define EMREN 0x10000000 /* Extended Mode Register Enable */ 1623#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */ 1624#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */ 1625 1626/* EBIU_SDBCTL Masks */ 1627#define EBE 0x0001 /* Enable SDRAM External Bank */ 1628#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */ 1629#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ 1630#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ 1631#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ 1632#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ 1633#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ 1634#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ 1635#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ 1636#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ 1637#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */ 1638 1639/* EBIU_SDSTAT Masks */ 1640#define SDCI 0x0001 /* SDRAM Controller Idle */ 1641#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */ 1642#define SDPUA 0x0004 /* SDRAM Power-Up Active */ 1643#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */ 1644#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */ 1645#define BGSTAT 0x0020 /* Bus Grant Status */ 1646 1647/* ************************** DMA CONTROLLER MASKS ********************************/ 1648/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ 1649#define DMAEN 0x0001 /* DMA Channel Enable */ 1650#define WNR 0x0002 /* Channel Direction (W/R*) */ 1651#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ 1652#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ 1653#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ 1654#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ 1655#define RESTART 0x0020 /* DMA Buffer Clear */ 1656#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ 1657#define DI_EN 0x0080 /* Data Interrupt Enable */ 1658#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 1659#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 1660#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 1661#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ 1662#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ 1663#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ 1664#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ 1665#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ 1666#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 1667#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 1668#define NDSIZE 0x0900 /* Next Descriptor Size */ 1669 1670#define DMAFLOW 0x7000 /* Flow Control */ 1671#define DMAFLOW_STOP 0x0000 /* Stop Mode */ 1672#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ 1673#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 1674#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 1675#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 1676 1677/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1678#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ 1679#define PMAP 0xF000 /* Peripheral Mapped To This Channel */ 1680#define PMAP_PPI 0x0000 /* PPI Port DMA */ 1681#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */ 1682#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */ 1683#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */ 1684#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */ 1685#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */ 1686#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */ 1687#define PMAP_SPI 0x7000 /* SPI Port DMA */ 1688#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ 1689#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ 1690#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ 1691#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ 1692 1693/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ 1694#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ 1695#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ 1696#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ 1697#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ 1698 1699/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ 1700/* PPI_CONTROL Masks */ 1701#define PORT_EN 0x0001 /* PPI Port Enable */ 1702#define PORT_DIR 0x0002 /* PPI Port Direction */ 1703#define XFR_TYPE 0x000C /* PPI Transfer Type */ 1704#define PORT_CFG 0x0030 /* PPI Port Configuration */ 1705#define FLD_SEL 0x0040 /* PPI Active Field Select */ 1706#define PACK_EN 0x0080 /* PPI Packing Mode */ 1707#define DMA32 0x0100 /* PPI 32-bit DMA Enable */ 1708#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ 1709#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ 1710#define DLENGTH 0x3800 /* PPI Data Length */ 1711#define DLEN_8 0x0000 /* Data Length = 8 Bits */ 1712#define DLEN_10 0x0800 /* Data Length = 10 Bits */ 1713#define DLEN_11 0x1000 /* Data Length = 11 Bits */ 1714#define DLEN_12 0x1800 /* Data Length = 12 Bits */ 1715#define DLEN_13 0x2000 /* Data Length = 13 Bits */ 1716#define DLEN_14 0x2800 /* Data Length = 14 Bits */ 1717#define DLEN_15 0x3000 /* Data Length = 15 Bits */ 1718#define DLEN_16 0x3800 /* Data Length = 16 Bits */ 1719#define POLC 0x4000 /* PPI Clock Polarity */ 1720#define POLS 0x8000 /* PPI Frame Sync Polarity */ 1721 1722/* PPI_STATUS Masks */ 1723#define FLD 0x0400 /* Field Indicator */ 1724#define FT_ERR 0x0800 /* Frame Track Error */ 1725#define OVR 0x1000 /* FIFO Overflow Error */ 1726#define UNDR 0x2000 /* FIFO Underrun Error */ 1727#define ERR_DET 0x4000 /* Error Detected Indicator */ 1728#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1729 1730/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/ 1731/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 1732#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 1733#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 1734 1735/* TWI_PRESCALE Masks */ 1736#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 1737#define TWI_ENA 0x0080 /* TWI Enable */ 1738#define SCCB 0x0200 /* SCCB Compatibility Enable */ 1739 1740/* TWI_SLAVE_CTRL Masks */ 1741#define SEN 0x0001 /* Slave Enable */ 1742#define SADD_LEN 0x0002 /* Slave Address Length */ 1743#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1744#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ 1745#define GEN 0x0010 /* General Call Adrress Matching Enabled */ 1746 1747/* TWI_SLAVE_STAT Masks */ 1748#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1749#define GCALL 0x0002 /* General Call Indicator */ 1750 1751/* TWI_MASTER_CTRL Masks */ 1752#define MEN 0x0001 /* Master Mode Enable */ 1753#define MADD_LEN 0x0002 /* Master Address Length */ 1754#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 1755#define FAST 0x0008 /* Use Fast Mode Timing Specs */ 1756#define STOP 0x0010 /* Issue Stop Condition */ 1757#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 1758#define DCNT 0x3FC0 /* Data Bytes To Transfer */ 1759#define SDAOVR 0x4000 /* Serial Data Override */ 1760#define SCLOVR 0x8000 /* Serial Clock Override */ 1761 1762/* TWI_MASTER_STAT Masks */ 1763#define MPROG 0x0001 /* Master Transfer In Progress */ 1764#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 1765#define ANAK 0x0004 /* Address Not Acknowledged */ 1766#define DNAK 0x0008 /* Data Not Acknowledged */ 1767#define BUFRDERR 0x0010 /* Buffer Read Error */ 1768#define BUFWRERR 0x0020 /* Buffer Write Error */ 1769#define SDASEN 0x0040 /* Serial Data Sense */ 1770#define SCLSEN 0x0080 /* Serial Clock Sense */ 1771#define BUSBUSY 0x0100 /* Bus Busy Indicator */ 1772 1773/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ 1774#define SINIT 0x0001 /* Slave Transfer Initiated */ 1775#define SCOMP 0x0002 /* Slave Transfer Complete */ 1776#define SERR 0x0004 /* Slave Transfer Error */ 1777#define SOVF 0x0008 /* Slave Overflow */ 1778#define MCOMP 0x0010 /* Master Transfer Complete */ 1779#define MERR 0x0020 /* Master Transfer Error */ 1780#define XMTSERV 0x0040 /* Transmit FIFO Service */ 1781#define RCVSERV 0x0080 /* Receive FIFO Service */ 1782 1783/* TWI_FIFO_CTRL Masks */ 1784#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 1785#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 1786#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 1787#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 1788 1789/* TWI_FIFO_STAT Masks */ 1790#define XMTSTAT 0x0003 /* Transmit FIFO Status */ 1791#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 1792#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 1793#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 1794 1795#define RCVSTAT 0x000C /* Receive FIFO Status */ 1796#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 1797#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 1798#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 1799 1800/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ 1801/* CAN_CONTROL Masks */ 1802#define SRS 0x0001 /* Software Reset */ 1803#define DNM 0x0002 /* Device Net Mode */ 1804#define ABO 0x0004 /* Auto-Bus On Enable */ 1805#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ 1806#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ 1807#define SMR 0x0020 /* Sleep Mode Request */ 1808#define CSR 0x0040 /* CAN Suspend Mode Request */ 1809#define CCR 0x0080 /* CAN Configuration Mode Request */ 1810 1811/* CAN_STATUS Masks */ 1812#define WT 0x0001 /* TX Warning Flag */ 1813#define WR 0x0002 /* RX Warning Flag */ 1814#define EP 0x0004 /* Error Passive Mode */ 1815#define EBO 0x0008 /* Error Bus Off Mode */ 1816#define SMA 0x0020 /* Sleep Mode Acknowledge */ 1817#define CSA 0x0040 /* Suspend Mode Acknowledge */ 1818#define CCA 0x0080 /* Configuration Mode Acknowledge */ 1819#define MBPTR 0x1F00 /* Mailbox Pointer */ 1820#define TRM 0x4000 /* Transmit Mode */ 1821#define REC 0x8000 /* Receive Mode */ 1822 1823/* CAN_CLOCK Masks */ 1824#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ 1825 1826/* CAN_TIMING Masks */ 1827#define TSEG1 0x000F /* Time Segment 1 */ 1828#define TSEG2 0x0070 /* Time Segment 2 */ 1829#define SAM 0x0080 /* Sampling */ 1830#define SJW 0x0300 /* Synchronization Jump Width */ 1831 1832/* CAN_DEBUG Masks */ 1833#define DEC 0x0001 /* Disable CAN Error Counters */ 1834#define DRI 0x0002 /* Disable CAN RX Input */ 1835#define DTO 0x0004 /* Disable CAN TX Output */ 1836#define DIL 0x0008 /* Disable CAN Internal Loop */ 1837#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ 1838#define MRB 0x0020 /* Mode Read Back Enable */ 1839#define CDE 0x8000 /* CAN Debug Enable */ 1840 1841/* CAN_CEC Masks */ 1842#define RXECNT 0x00FF /* Receive Error Counter */ 1843#define TXECNT 0xFF00 /* Transmit Error Counter */ 1844 1845/* CAN_INTR Masks */ 1846#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ 1847#define MBRIF MBRIRQ /* legacy */ 1848#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ 1849#define MBTIF MBTIRQ /* legacy */ 1850#define GIRQ 0x0004 /* Global Interrupt */ 1851#define SMACK 0x0008 /* Sleep Mode Acknowledge */ 1852#define CANTX 0x0040 /* CAN TX Bus Value */ 1853#define CANRX 0x0080 /* CAN RX Bus Value */ 1854 1855/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ 1856#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ 1857#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ 1858#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ 1859#define BASEID 0x1FFC /* Base Identifier */ 1860#define IDE 0x2000 /* Identifier Extension */ 1861#define RTR 0x4000 /* Remote Frame Transmission Request */ 1862#define AME 0x8000 /* Acceptance Mask Enable */ 1863 1864/* CAN_MBxx_TIMESTAMP Masks */ 1865#define TSV 0xFFFF /* Timestamp */ 1866 1867/* CAN_MBxx_LENGTH Masks */ 1868#define DLC 0x000F /* Data Length Code */ 1869 1870/* CAN_AMxxH and CAN_AMxxL Masks */ 1871#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ 1872#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ 1873#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ 1874#define BASEID 0x1FFC /* Base Identifier */ 1875#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ 1876#define FMD 0x4000 /* Full Mask Data Field Enable */ 1877#define FDF 0x8000 /* Filter On Data Field Enable */ 1878 1879/* CAN_MC1 Masks */ 1880#define MC0 0x0001 /* Enable Mailbox 0 */ 1881#define MC1 0x0002 /* Enable Mailbox 1 */ 1882#define MC2 0x0004 /* Enable Mailbox 2 */ 1883#define MC3 0x0008 /* Enable Mailbox 3 */ 1884#define MC4 0x0010 /* Enable Mailbox 4 */ 1885#define MC5 0x0020 /* Enable Mailbox 5 */ 1886#define MC6 0x0040 /* Enable Mailbox 6 */ 1887#define MC7 0x0080 /* Enable Mailbox 7 */ 1888#define MC8 0x0100 /* Enable Mailbox 8 */ 1889#define MC9 0x0200 /* Enable Mailbox 9 */ 1890#define MC10 0x0400 /* Enable Mailbox 10 */ 1891#define MC11 0x0800 /* Enable Mailbox 11 */ 1892#define MC12 0x1000 /* Enable Mailbox 12 */ 1893#define MC13 0x2000 /* Enable Mailbox 13 */ 1894#define MC14 0x4000 /* Enable Mailbox 14 */ 1895#define MC15 0x8000 /* Enable Mailbox 15 */ 1896 1897/* CAN_MC2 Masks */ 1898#define MC16 0x0001 /* Enable Mailbox 16 */ 1899#define MC17 0x0002 /* Enable Mailbox 17 */ 1900#define MC18 0x0004 /* Enable Mailbox 18 */ 1901#define MC19 0x0008 /* Enable Mailbox 19 */ 1902#define MC20 0x0010 /* Enable Mailbox 20 */ 1903#define MC21 0x0020 /* Enable Mailbox 21 */ 1904#define MC22 0x0040 /* Enable Mailbox 22 */ 1905#define MC23 0x0080 /* Enable Mailbox 23 */ 1906#define MC24 0x0100 /* Enable Mailbox 24 */ 1907#define MC25 0x0200 /* Enable Mailbox 25 */ 1908#define MC26 0x0400 /* Enable Mailbox 26 */ 1909#define MC27 0x0800 /* Enable Mailbox 27 */ 1910#define MC28 0x1000 /* Enable Mailbox 28 */ 1911#define MC29 0x2000 /* Enable Mailbox 29 */ 1912#define MC30 0x4000 /* Enable Mailbox 30 */ 1913#define MC31 0x8000 /* Enable Mailbox 31 */ 1914 1915/* CAN_MD1 Masks */ 1916#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ 1917#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ 1918#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ 1919#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ 1920#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ 1921#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ 1922#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ 1923#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ 1924#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ 1925#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ 1926#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ 1927#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ 1928#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ 1929#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ 1930#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ 1931#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ 1932 1933/* CAN_MD2 Masks */ 1934#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ 1935#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ 1936#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ 1937#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ 1938#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ 1939#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ 1940#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ 1941#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ 1942#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ 1943#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ 1944#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ 1945#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ 1946#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ 1947#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ 1948#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ 1949#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ 1950 1951/* CAN_RMP1 Masks */ 1952#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ 1953#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ 1954#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ 1955#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ 1956#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ 1957#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ 1958#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ 1959#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ 1960#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ 1961#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ 1962#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ 1963#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ 1964#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ 1965#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ 1966#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ 1967#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ 1968 1969/* CAN_RMP2 Masks */ 1970#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ 1971#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ 1972#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ 1973#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ 1974#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ 1975#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ 1976#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ 1977#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ 1978#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ 1979#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ 1980#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ 1981#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ 1982#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ 1983#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ 1984#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ 1985#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ 1986 1987/* CAN_RML1 Masks */ 1988#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ 1989#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ 1990#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ 1991#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ 1992#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ 1993#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ 1994#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ 1995#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ 1996#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ 1997#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ 1998#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ 1999#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ 2000#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2001#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ 2002#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ 2003#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ 2004 2005/* CAN_RML2 Masks */ 2006#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ 2007#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ 2008#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ 2009#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ 2010#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ 2011#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ 2012#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ 2013#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ 2014#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ 2015#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ 2016#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ 2017#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ 2018#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ 2019#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ 2020#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ 2021#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ 2022 2023/* CAN_OPSS1 Masks */ 2024#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ 2025#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ 2026#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ 2027#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ 2028#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ 2029#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ 2030#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ 2031#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ 2032#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ 2033#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ 2034#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ 2035#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ 2036#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ 2037#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ 2038#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ 2039#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ 2040 2041/* CAN_OPSS2 Masks */ 2042#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ 2043#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ 2044#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ 2045#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ 2046#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ 2047#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ 2048#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ 2049#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ 2050#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ 2051#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ 2052#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ 2053#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ 2054#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ 2055#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ 2056#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ 2057#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ 2058 2059/* CAN_TRR1 Masks */ 2060#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ 2061#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ 2062#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ 2063#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ 2064#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ 2065#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ 2066#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ 2067#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ 2068#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ 2069#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ 2070#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ 2071#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ 2072#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ 2073#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ 2074#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ 2075#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ 2076 2077/* CAN_TRR2 Masks */ 2078#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ 2079#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ 2080#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ 2081#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ 2082#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ 2083#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ 2084#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ 2085#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ 2086#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ 2087#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ 2088#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ 2089#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ 2090#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ 2091#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ 2092#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ 2093#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ 2094 2095/* CAN_TRS1 Masks */ 2096#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ 2097#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ 2098#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ 2099#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ 2100#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ 2101#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ 2102#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ 2103#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ 2104#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ 2105#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ 2106#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ 2107#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ 2108#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ 2109#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ 2110#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ 2111#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ 2112 2113/* CAN_TRS2 Masks */ 2114#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ 2115#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ 2116#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ 2117#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ 2118#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ 2119#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ 2120#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ 2121#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ 2122#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ 2123#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ 2124#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ 2125#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ 2126#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ 2127#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ 2128#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ 2129#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ 2130 2131/* CAN_AA1 Masks */ 2132#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ 2133#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ 2134#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ 2135#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ 2136#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ 2137#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ 2138#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ 2139#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ 2140#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ 2141#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ 2142#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ 2143#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ 2144#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ 2145#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ 2146#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ 2147#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ 2148 2149/* CAN_AA2 Masks */ 2150#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ 2151#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ 2152#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ 2153#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ 2154#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ 2155#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ 2156#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ 2157#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ 2158#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ 2159#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ 2160#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ 2161#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ 2162#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ 2163#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ 2164#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ 2165#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ 2166 2167/* CAN_TA1 Masks */ 2168#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ 2169#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ 2170#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ 2171#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ 2172#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ 2173#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ 2174#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ 2175#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ 2176#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ 2177#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ 2178#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ 2179#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ 2180#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ 2181#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ 2182#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ 2183#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ 2184 2185/* CAN_TA2 Masks */ 2186#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ 2187#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ 2188#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ 2189#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ 2190#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ 2191#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ 2192#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ 2193#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ 2194#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ 2195#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ 2196#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ 2197#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ 2198#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ 2199#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ 2200#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ 2201#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ 2202 2203/* CAN_MBTD Masks */ 2204#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ 2205#define TDA 0x0040 /* Temporary Disable Acknowledge */ 2206#define TDR 0x0080 /* Temporary Disable Request */ 2207 2208/* CAN_RFH1 Masks */ 2209#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ 2210#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ 2211#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ 2212#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ 2213#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ 2214#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ 2215#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ 2216#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ 2217#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ 2218#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ 2219#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ 2220#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ 2221#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ 2222#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ 2223#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ 2224#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ 2225 2226/* CAN_RFH2 Masks */ 2227#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ 2228#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ 2229#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ 2230#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ 2231#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ 2232#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ 2233#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ 2234#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ 2235#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ 2236#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ 2237#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ 2238#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ 2239#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ 2240#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ 2241#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ 2242#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ 2243 2244/* CAN_MBTIF1 Masks */ 2245#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ 2246#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ 2247#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ 2248#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ 2249#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ 2250#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ 2251#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ 2252#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ 2253#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ 2254#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ 2255#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ 2256#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ 2257#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ 2258#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ 2259#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ 2260#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ 2261 2262/* CAN_MBTIF2 Masks */ 2263#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ 2264#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ 2265#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ 2266#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ 2267#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ 2268#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ 2269#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ 2270#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ 2271#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ 2272#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ 2273#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ 2274#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ 2275#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ 2276#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ 2277#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ 2278#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ 2279 2280/* CAN_MBRIF1 Masks */ 2281#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ 2282#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ 2283#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ 2284#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ 2285#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ 2286#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ 2287#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ 2288#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ 2289#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ 2290#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ 2291#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ 2292#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ 2293#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ 2294#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ 2295#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ 2296#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ 2297 2298/* CAN_MBRIF2 Masks */ 2299#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ 2300#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ 2301#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ 2302#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ 2303#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ 2304#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ 2305#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ 2306#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ 2307#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ 2308#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ 2309#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ 2310#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ 2311#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ 2312#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ 2313#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ 2314#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ 2315 2316/* CAN_MBIM1 Masks */ 2317#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ 2318#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ 2319#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ 2320#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ 2321#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ 2322#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ 2323#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ 2324#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ 2325#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ 2326#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ 2327#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ 2328#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ 2329#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ 2330#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ 2331#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ 2332#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ 2333 2334/* CAN_MBIM2 Masks */ 2335#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ 2336#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ 2337#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ 2338#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ 2339#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ 2340#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ 2341#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ 2342#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ 2343#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ 2344#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ 2345#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ 2346#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ 2347#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ 2348#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ 2349#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ 2350#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ 2351 2352/* CAN_GIM Masks */ 2353#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ 2354#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ 2355#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ 2356#define BOIM 0x0008 /* Enable Bus Off Interrupt */ 2357#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ 2358#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ 2359#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ 2360#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ 2361#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ 2362#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ 2363#define ADIM 0x0400 /* Enable Access Denied Interrupt */ 2364 2365/* CAN_GIS Masks */ 2366#define EWTIS 0x0001 /* TX Error Count IRQ Status */ 2367#define EWRIS 0x0002 /* RX Error Count IRQ Status */ 2368#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ 2369#define BOIS 0x0008 /* Bus Off IRQ Status */ 2370#define WUIS 0x0010 /* Wake-Up IRQ Status */ 2371#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ 2372#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ 2373#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ 2374#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ 2375#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ 2376#define ADIS 0x0400 /* Access Denied IRQ Status */ 2377 2378/* CAN_GIF Masks */ 2379#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ 2380#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ 2381#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ 2382#define BOIF 0x0008 /* Bus Off IRQ Flag */ 2383#define WUIF 0x0010 /* Wake-Up IRQ Flag */ 2384#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ 2385#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ 2386#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ 2387#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ 2388#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ 2389#define ADIF 0x0400 /* Access Denied IRQ Flag */ 2390 2391/* CAN_UCCNF Masks */ 2392#define UCCNF 0x000F /* Universal Counter Mode */ 2393#define UC_STAMP 0x0001 /* Timestamp Mode */ 2394#define UC_WDOG 0x0002 /* Watchdog Mode */ 2395#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ 2396#define UC_ERROR 0x0006 /* CAN Error Frame Count */ 2397#define UC_OVER 0x0007 /* CAN Overload Frame Count */ 2398#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ 2399#define UC_AA 0x0009 /* TX Abort Count */ 2400#define UC_TA 0x000A /* TX Successful Count */ 2401#define UC_REJECT 0x000B /* RX Message Rejected Count */ 2402#define UC_RML 0x000C /* RX Message Lost Count */ 2403#define UC_RX 0x000D /* Total Successful RX Messages Count */ 2404#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ 2405#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ 2406#define UCRC 0x0020 /* Universal Counter Reload/Clear */ 2407#define UCCT 0x0040 /* Universal Counter CAN Trigger */ 2408#define UCE 0x0080 /* Universal Counter Enable */ 2409 2410/* CAN_ESR Masks */ 2411#define ACKE 0x0004 /* Acknowledge Error */ 2412#define SER 0x0008 /* Stuff Error */ 2413#define CRCE 0x0010 /* CRC Error */ 2414#define SA0 0x0020 /* Stuck At Dominant Error */ 2415#define BEF 0x0040 /* Bit Error Flag */ 2416#define FER 0x0080 /* Form Error Flag */ 2417 2418/* CAN_EWR Masks */ 2419#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ 2420#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ 2421 2422/* ******************* PIN CONTROL REGISTER MASKS ************************/ 2423/* PORT_MUX Masks */ 2424#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ 2425#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */ 2426#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */ 2427 2428#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */ 2429#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */ 2430#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */ 2431#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ 2432 2433#define PFDE 0x0008 /* Port F DMA Request Enable */ 2434#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */ 2435#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */ 2436 2437#define PFTE 0x0010 /* Port F Timer Enable */ 2438#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ 2439#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */ 2440 2441#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */ 2442#define PFS6E_TIMER 0x0000 /* Enable TMR5 */ 2443#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */ 2444 2445#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */ 2446#define PFS5E_TIMER 0x0000 /* Enable TMR4 */ 2447#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */ 2448 2449#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */ 2450#define PFS4E_TIMER 0x0000 /* Enable TMR3 */ 2451#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */ 2452 2453#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */ 2454#define PFFE_TIMER 0x0000 /* Enable TMR2 */ 2455#define PFFE_PPI 0x0100 /* Enable PPI FS3 */ 2456 2457#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */ 2458#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */ 2459#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */ 2460 2461#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */ 2462#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */ 2463#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */ 2464 2465#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */ 2466#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ 2467#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ 2468 2469/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/ 2470/* HDMAx_CTL Masks */ 2471#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */ 2472#define REP 0x0002 /* HDMA Request Polarity */ 2473#define UTE 0x0004 /* Urgency Threshold Enable */ 2474#define OIE 0x0010 /* Overflow Interrupt Enable */ 2475#define BDIE 0x0020 /* Block Done Interrupt Enable */ 2476#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */ 2477#define DRQ 0x0300 /* HDMA Request Type */ 2478#define DRQ_NONE 0x0000 /* No Request */ 2479#define DRQ_SINGLE 0x0100 /* Channels Request Single */ 2480#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */ 2481#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */ 2482#define RBC 0x1000 /* Reload BCNT With IBCNT */ 2483#define PS 0x2000 /* HDMA Pin Status */ 2484#define OI 0x4000 /* Overflow Interrupt Generated */ 2485#define BDI 0x8000 /* Block Done Interrupt Generated */ 2486 2487/* entry addresses of the user-callable Boot ROM functions */ 2488 2489#define _BOOTROM_RESET 0xEF000000 2490#define _BOOTROM_FINAL_INIT 0xEF000002 2491#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 2492#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 2493#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 2494#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 2495#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 2496#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 2497#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 2498 2499/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 2500#define PGDE_UART PFDE_UART 2501#define PGDE_DMA PFDE_DMA 2502#define CKELOW SCKELOW 2503#endif /* _DEF_BF534_H */ 2504