LXR linux/arch/blackfin/mach-bf548/dma.c

   1/*
   2 * the simple DMA Implementation for Blackfin
   3 *
   4 * Copyright 2007-2009 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#include <linux/module.h>
  10
  11#include <asm/blackfin.h>
  12#include <asm/dma.h>
  13
  14struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
  15        (struct dma_register *) DMA0_NEXT_DESC_PTR,
  16        (struct dma_register *) DMA1_NEXT_DESC_PTR,
  17        (struct dma_register *) DMA2_NEXT_DESC_PTR,
  18        (struct dma_register *) DMA3_NEXT_DESC_PTR,
  19        (struct dma_register *) DMA4_NEXT_DESC_PTR,
  20        (struct dma_register *) DMA5_NEXT_DESC_PTR,
  21        (struct dma_register *) DMA6_NEXT_DESC_PTR,
  22        (struct dma_register *) DMA7_NEXT_DESC_PTR,
  23        (struct dma_register *) DMA8_NEXT_DESC_PTR,
  24        (struct dma_register *) DMA9_NEXT_DESC_PTR,
  25        (struct dma_register *) DMA10_NEXT_DESC_PTR,
  26        (struct dma_register *) DMA11_NEXT_DESC_PTR,
  27        (struct dma_register *) DMA12_NEXT_DESC_PTR,
  28        (struct dma_register *) DMA13_NEXT_DESC_PTR,
  29        (struct dma_register *) DMA14_NEXT_DESC_PTR,
  30        (struct dma_register *) DMA15_NEXT_DESC_PTR,
  31        (struct dma_register *) DMA16_NEXT_DESC_PTR,
  32        (struct dma_register *) DMA17_NEXT_DESC_PTR,
  33        (struct dma_register *) DMA18_NEXT_DESC_PTR,
  34        (struct dma_register *) DMA19_NEXT_DESC_PTR,
  35        (struct dma_register *) DMA20_NEXT_DESC_PTR,
  36        (struct dma_register *) DMA21_NEXT_DESC_PTR,
  37        (struct dma_register *) DMA22_NEXT_DESC_PTR,
  38        (struct dma_register *) DMA23_NEXT_DESC_PTR,
  39        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
  40        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
  41        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
  42        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
  43        (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
  44        (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
  45        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
  46        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
  47};
  48EXPORT_SYMBOL(dma_io_base_addr);
  49
  50int channel2irq(unsigned int channel)
  51{
  52        int ret_irq = -1;
  53
  54        switch (channel) {
  55        case CH_SPORT0_RX:
  56                ret_irq = IRQ_SPORT0_RX;
  57                break;
  58        case CH_SPORT0_TX:
  59                ret_irq = IRQ_SPORT0_TX;
  60                break;
  61        case CH_SPORT1_RX:
  62                ret_irq = IRQ_SPORT1_RX;
  63                break;
  64        case CH_SPORT1_TX:
  65                ret_irq = IRQ_SPORT1_TX;
  66        case CH_SPI0:
  67                ret_irq = IRQ_SPI0;
  68                break;
  69        case CH_SPI1:
  70                ret_irq = IRQ_SPI1;
  71                break;
  72        case CH_UART0_RX:
  73                ret_irq = IRQ_UART0_RX;
  74                break;
  75        case CH_UART0_TX:
  76                ret_irq = IRQ_UART0_TX;
  77                break;
  78        case CH_UART1_RX:
  79                ret_irq = IRQ_UART1_RX;
  80                break;
  81        case CH_UART1_TX:
  82                ret_irq = IRQ_UART1_TX;
  83                break;
  84        case CH_EPPI0:
  85                ret_irq = IRQ_EPPI0;
  86                break;
  87        case CH_EPPI1:
  88                ret_irq = IRQ_EPPI1;
  89                break;
  90        case CH_EPPI2:
  91                ret_irq = IRQ_EPPI2;
  92                break;
  93        case CH_PIXC_IMAGE:
  94                ret_irq = IRQ_PIXC_IN0;
  95                break;
  96        case CH_PIXC_OVERLAY:
  97                ret_irq = IRQ_PIXC_IN1;
  98                break;
  99        case CH_PIXC_OUTPUT:
 100                ret_irq = IRQ_PIXC_OUT;
 101                break;
 102        case CH_SPORT2_RX:
 103                ret_irq = IRQ_SPORT2_RX;
 104                break;
 105        case CH_SPORT2_TX:
 106                ret_irq = IRQ_SPORT2_TX;
 107                break;
 108        case CH_SPORT3_RX:
 109                ret_irq = IRQ_SPORT3_RX;
 110                break;
 111        case CH_SPORT3_TX:
 112                ret_irq = IRQ_SPORT3_TX;
 113                break;
 114        case CH_SDH:
 115                ret_irq = IRQ_SDH;
 116                break;
 117        case CH_SPI2:
 118                ret_irq = IRQ_SPI2;
 119                break;
 120        case CH_MEM_STREAM0_SRC:
 121        case CH_MEM_STREAM0_DEST:
 122                ret_irq = IRQ_MDMAS0;
 123                break;
 124        case CH_MEM_STREAM1_SRC:
 125        case CH_MEM_STREAM1_DEST:
 126                ret_irq = IRQ_MDMAS1;
 127                break;
 128        case CH_MEM_STREAM2_SRC:
 129        case CH_MEM_STREAM2_DEST:
 130                ret_irq = IRQ_MDMAS2;
 131                break;
 132        case CH_MEM_STREAM3_SRC:
 133        case CH_MEM_STREAM3_DEST:
 134                ret_irq = IRQ_MDMAS3;
 135                break;
 136        }
 137        return ret_irq;
 138}
 139