1#ifndef _ASM_ARCH_CRIS_IO_H 2#define _ASM_ARCH_CRIS_IO_H 3 4#include <linux/spinlock.h> 5#include <hwregs/reg_map.h> 6#include <hwregs/reg_rdwr.h> 7#include <hwregs/gio_defs.h> 8 9enum crisv32_io_dir 10{ 11 crisv32_io_dir_in = 0, 12 crisv32_io_dir_out = 1 13}; 14 15struct crisv32_ioport 16{ 17 volatile unsigned long *oe; 18 volatile unsigned long *data; 19 volatile unsigned long *data_in; 20 unsigned int pin_count; 21 spinlock_t lock; 22}; 23 24struct crisv32_iopin 25{ 26 struct crisv32_ioport* port; 27 int bit; 28}; 29 30extern struct crisv32_ioport crisv32_ioports[]; 31 32extern struct crisv32_iopin crisv32_led1_green; 33extern struct crisv32_iopin crisv32_led1_red; 34extern struct crisv32_iopin crisv32_led2_green; 35extern struct crisv32_iopin crisv32_led2_red; 36extern struct crisv32_iopin crisv32_led3_green; 37extern struct crisv32_iopin crisv32_led3_red; 38 39extern struct crisv32_iopin crisv32_led_net0_green; 40extern struct crisv32_iopin crisv32_led_net0_red; 41extern struct crisv32_iopin crisv32_led_net1_green; 42extern struct crisv32_iopin crisv32_led_net1_red; 43 44static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) 45{ 46 unsigned long flags; 47 spin_lock_irqsave(&iopin->port->lock, flags); 48 49 if (val) 50 *iopin->port->data |= iopin->bit; 51 else 52 *iopin->port->data &= ~iopin->bit; 53 54 spin_unlock_irqrestore(&iopin->port->lock, flags); 55} 56 57static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, 58 enum crisv32_io_dir dir) 59{ 60 unsigned long flags; 61 spin_lock_irqsave(&iopin->port->lock, flags); 62 63 if (dir == crisv32_io_dir_in) 64 *iopin->port->oe &= ~iopin->bit; 65 else 66 *iopin->port->oe |= iopin->bit; 67 68 spin_unlock_irqrestore(&iopin->port->lock, flags); 69} 70 71static inline int crisv32_io_rd(struct crisv32_iopin* iopin) 72{ 73 return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); 74} 75 76int crisv32_io_get(struct crisv32_iopin* iopin, 77 unsigned int port, unsigned int pin); 78int crisv32_io_get_name(struct crisv32_iopin* iopin, 79 const char *name); 80 81#define CRIS_LED_OFF 0x00 82#define CRIS_LED_GREEN 0x01 83#define CRIS_LED_RED 0x02 84#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) 85 86#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) 87#define CRIS_LED_NETWORK_GRP0_SET(x) \ 88 do { \ 89 CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ 90 CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ 91 } while (0) 92#else 93#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} 94#endif 95 96#define CRIS_LED_NETWORK_GRP0_SET_G(x) \ 97 crisv32_io_set(&crisv32_led_net0_green, !(x)); 98 99#define CRIS_LED_NETWORK_GRP0_SET_R(x) \ 100 crisv32_io_set(&crisv32_led_net0_red, !(x)); 101 102#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) 103#define CRIS_LED_NETWORK_GRP1_SET(x) \ 104 do { \ 105 CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ 106 CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ 107 } while (0) 108#else 109#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} 110#endif 111 112#define CRIS_LED_NETWORK_GRP1_SET_G(x) \ 113 crisv32_io_set(&crisv32_led_net1_green, !(x)); 114 115#define CRIS_LED_NETWORK_GRP1_SET_R(x) \ 116 crisv32_io_set(&crisv32_led_net1_red, !(x)); 117 118#define CRIS_LED_ACTIVE_SET(x) \ 119 do { \ 120 CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ 121 CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ 122 } while (0) 123 124#define CRIS_LED_ACTIVE_SET_G(x) \ 125 crisv32_io_set(&crisv32_led2_green, !(x)); 126#define CRIS_LED_ACTIVE_SET_R(x) \ 127 crisv32_io_set(&crisv32_led2_red, !(x)); 128#define CRIS_LED_DISK_WRITE(x) \ 129 do{\ 130 crisv32_io_set(&crisv32_led3_green, !(x)); \ 131 crisv32_io_set(&crisv32_led3_red, !(x)); \ 132 }while(0) 133#define CRIS_LED_DISK_READ(x) \ 134 crisv32_io_set(&crisv32_led3_green, !(x)); 135 136#endif 137