LXR linux/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu

   1#ifndef __iop_sw_mpu_defs_h
   2#define __iop_sw_mpu_defs_h
   3
   4/*
   5 * This file is autogenerated from
   6 *   file:           iop_sw_mpu.r
   7 * 
   8 *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
   9 * Any changes here will be lost.
  10 *
  11 * -*- buffer-read-only: t -*-
  12 */
  13/* Main access macros */
  14#ifndef REG_RD
  15#define REG_RD( scope, inst, reg ) \
  16  REG_READ( reg_##scope##_##reg, \
  17            (inst) + REG_RD_ADDR_##scope##_##reg )
  18#endif
  19
  20#ifndef REG_WR
  21#define REG_WR( scope, inst, reg, val ) \
  22  REG_WRITE( reg_##scope##_##reg, \
  23             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  24#endif
  25
  26#ifndef REG_RD_VECT
  27#define REG_RD_VECT( scope, inst, reg, index ) \
  28  REG_READ( reg_##scope##_##reg, \
  29            (inst) + REG_RD_ADDR_##scope##_##reg + \
  30            (index) * STRIDE_##scope##_##reg )
  31#endif
  32
  33#ifndef REG_WR_VECT
  34#define REG_WR_VECT( scope, inst, reg, index, val ) \
  35  REG_WRITE( reg_##scope##_##reg, \
  36             (inst) + REG_WR_ADDR_##scope##_##reg + \
  37             (index) * STRIDE_##scope##_##reg, (val) )
  38#endif
  39
  40#ifndef REG_RD_INT
  41#define REG_RD_INT( scope, inst, reg ) \
  42  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  43#endif
  44
  45#ifndef REG_WR_INT
  46#define REG_WR_INT( scope, inst, reg, val ) \
  47  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  48#endif
  49
  50#ifndef REG_RD_INT_VECT
  51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  52  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  53            (index) * STRIDE_##scope##_##reg )
  54#endif
  55
  56#ifndef REG_WR_INT_VECT
  57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  58  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  59             (index) * STRIDE_##scope##_##reg, (val) )
  60#endif
  61
  62#ifndef REG_TYPE_CONV
  63#define REG_TYPE_CONV( type, orgtype, val ) \
  64  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  65#endif
  66
  67#ifndef reg_page_size
  68#define reg_page_size 8192
  69#endif
  70
  71#ifndef REG_ADDR
  72#define REG_ADDR( scope, inst, reg ) \
  73  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  74#endif
  75
  76#ifndef REG_ADDR_VECT
  77#define REG_ADDR_VECT( scope, inst, reg, index ) \
  78  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  79    (index) * STRIDE_##scope##_##reg )
  80#endif
  81
  82/* C-code for register scope iop_sw_mpu */
  83
  84/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
  85typedef struct {
  86  unsigned int cfg : 2;
  87  unsigned int dummy1 : 30;
  88} reg_iop_sw_mpu_rw_sw_cfg_owner;
  89#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
  90#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
  91
  92/* Register r_spu_trace, scope iop_sw_mpu, type r */
  93typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
  94#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
  95
  96/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
  97typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
  98#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
  99
 100/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
 101typedef struct {
 102  unsigned int keep_owner : 1;
 103  unsigned int cmd        : 2;
 104  unsigned int size       : 3;
 105  unsigned int wr_spu_mem : 1;
 106  unsigned int dummy1     : 25;
 107} reg_iop_sw_mpu_rw_mc_ctrl;
 108#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
 109#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
 110
 111/* Register rw_mc_data, scope iop_sw_mpu, type rw */
 112typedef struct {
 113  unsigned int val : 32;
 114} reg_iop_sw_mpu_rw_mc_data;
 115#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
 116#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
 117
 118/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
 119typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
 120#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
 121#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
 122
 123/* Register rs_mc_data, scope iop_sw_mpu, type rs */
 124typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
 125#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
 126
 127/* Register r_mc_data, scope iop_sw_mpu, type r */
 128typedef unsigned int reg_iop_sw_mpu_r_mc_data;
 129#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
 130
 131/* Register r_mc_stat, scope iop_sw_mpu, type r */
 132typedef struct {
 133  unsigned int busy_cpu     : 1;
 134  unsigned int busy_mpu     : 1;
 135  unsigned int busy_spu     : 1;
 136  unsigned int owned_by_cpu : 1;
 137  unsigned int owned_by_mpu : 1;
 138  unsigned int owned_by_spu : 1;
 139  unsigned int dummy1       : 26;
 140} reg_iop_sw_mpu_r_mc_stat;
 141#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
 142
 143/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
 144typedef struct {
 145  unsigned int byte0 : 8;
 146  unsigned int byte1 : 8;
 147  unsigned int byte2 : 8;
 148  unsigned int byte3 : 8;
 149} reg_iop_sw_mpu_rw_bus_clr_mask;
 150#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
 151#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
 152
 153/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
 154typedef struct {
 155  unsigned int byte0 : 8;
 156  unsigned int byte1 : 8;
 157  unsigned int byte2 : 8;
 158  unsigned int byte3 : 8;
 159} reg_iop_sw_mpu_rw_bus_set_mask;
 160#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
 161#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
 162
 163/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
 164typedef struct {
 165  unsigned int byte0 : 1;
 166  unsigned int byte1 : 1;
 167  unsigned int byte2 : 1;
 168  unsigned int byte3 : 1;
 169  unsigned int dummy1 : 28;
 170} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
 171#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
 172#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
 173
 174/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
 175typedef struct {
 176  unsigned int byte0 : 1;
 177  unsigned int byte1 : 1;
 178  unsigned int byte2 : 1;
 179  unsigned int byte3 : 1;
 180  unsigned int dummy1 : 28;
 181} reg_iop_sw_mpu_rw_bus_oe_set_mask;
 182#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
 183#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
 184
 185/* Register r_bus_in, scope iop_sw_mpu, type r */
 186typedef unsigned int reg_iop_sw_mpu_r_bus_in;
 187#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
 188
 189/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
 190typedef struct {
 191  unsigned int val : 32;
 192} reg_iop_sw_mpu_rw_gio_clr_mask;
 193#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
 194#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
 195
 196/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
 197typedef struct {
 198  unsigned int val : 32;
 199} reg_iop_sw_mpu_rw_gio_set_mask;
 200#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
 201#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
 202
 203/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
 204typedef struct {
 205  unsigned int val : 32;
 206} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
 207#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
 208#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
 209
 210/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
 211typedef struct {
 212  unsigned int val : 32;
 213} reg_iop_sw_mpu_rw_gio_oe_set_mask;
 214#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
 215#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
 216
 217/* Register r_gio_in, scope iop_sw_mpu, type r */
 218typedef unsigned int reg_iop_sw_mpu_r_gio_in;
 219#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
 220
 221/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
 222typedef struct {
 223  unsigned int intr0  : 1;
 224  unsigned int intr1  : 1;
 225  unsigned int intr2  : 1;
 226  unsigned int intr3  : 1;
 227  unsigned int intr4  : 1;
 228  unsigned int intr5  : 1;
 229  unsigned int intr6  : 1;
 230  unsigned int intr7  : 1;
 231  unsigned int intr8  : 1;
 232  unsigned int intr9  : 1;
 233  unsigned int intr10 : 1;
 234  unsigned int intr11 : 1;
 235  unsigned int intr12 : 1;
 236  unsigned int intr13 : 1;
 237  unsigned int intr14 : 1;
 238  unsigned int intr15 : 1;
 239  unsigned int intr16 : 1;
 240  unsigned int intr17 : 1;
 241  unsigned int intr18 : 1;
 242  unsigned int intr19 : 1;
 243  unsigned int intr20 : 1;
 244  unsigned int intr21 : 1;
 245  unsigned int intr22 : 1;
 246  unsigned int intr23 : 1;
 247  unsigned int intr24 : 1;
 248  unsigned int intr25 : 1;
 249  unsigned int intr26 : 1;
 250  unsigned int intr27 : 1;
 251  unsigned int intr28 : 1;
 252  unsigned int intr29 : 1;
 253  unsigned int intr30 : 1;
 254  unsigned int intr31 : 1;
 255} reg_iop_sw_mpu_rw_cpu_intr;
 256#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
 257#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
 258
 259/* Register r_cpu_intr, scope iop_sw_mpu, type r */
 260typedef struct {
 261  unsigned int intr0  : 1;
 262  unsigned int intr1  : 1;
 263  unsigned int intr2  : 1;
 264  unsigned int intr3  : 1;
 265  unsigned int intr4  : 1;
 266  unsigned int intr5  : 1;
 267  unsigned int intr6  : 1;
 268  unsigned int intr7  : 1;
 269  unsigned int intr8  : 1;
 270  unsigned int intr9  : 1;
 271  unsigned int intr10 : 1;
 272  unsigned int intr11 : 1;
 273  unsigned int intr12 : 1;
 274  unsigned int intr13 : 1;
 275  unsigned int intr14 : 1;
 276  unsigned int intr15 : 1;
 277  unsigned int intr16 : 1;
 278  unsigned int intr17 : 1;
 279  unsigned int intr18 : 1;
 280  unsigned int intr19 : 1;
 281  unsigned int intr20 : 1;
 282  unsigned int intr21 : 1;
 283  unsigned int intr22 : 1;
 284  unsigned int intr23 : 1;
 285  unsigned int intr24 : 1;
 286  unsigned int intr25 : 1;
 287  unsigned int intr26 : 1;
 288  unsigned int intr27 : 1;
 289  unsigned int intr28 : 1;
 290  unsigned int intr29 : 1;
 291  unsigned int intr30 : 1;
 292  unsigned int intr31 : 1;
 293} reg_iop_sw_mpu_r_cpu_intr;
 294#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
 295
 296/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
 297typedef struct {
 298  unsigned int spu_intr0      : 1;
 299  unsigned int trigger_grp0   : 1;
 300  unsigned int timer_grp0     : 1;
 301  unsigned int fifo_out       : 1;
 302  unsigned int spu_intr1      : 1;
 303  unsigned int trigger_grp1   : 1;
 304  unsigned int timer_grp1     : 1;
 305  unsigned int fifo_in        : 1;
 306  unsigned int spu_intr2      : 1;
 307  unsigned int trigger_grp2   : 1;
 308  unsigned int fifo_out_extra : 1;
 309  unsigned int dmc_out        : 1;
 310  unsigned int spu_intr3      : 1;
 311  unsigned int trigger_grp3   : 1;
 312  unsigned int fifo_in_extra  : 1;
 313  unsigned int dmc_in         : 1;
 314  unsigned int dummy1         : 16;
 315} reg_iop_sw_mpu_rw_intr_grp0_mask;
 316#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
 317#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
 318
 319/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
 320typedef struct {
 321  unsigned int spu_intr0 : 1;
 322  unsigned int dummy1    : 3;
 323  unsigned int spu_intr1 : 1;
 324  unsigned int dummy2    : 3;
 325  unsigned int spu_intr2 : 1;
 326  unsigned int dummy3    : 3;
 327  unsigned int spu_intr3 : 1;
 328  unsigned int dummy4    : 19;
 329} reg_iop_sw_mpu_rw_ack_intr_grp0;
 330#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
 331#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
 332
 333/* Register r_intr_grp0, scope iop_sw_mpu, type r */
 334typedef struct {
 335  unsigned int spu_intr0      : 1;
 336  unsigned int trigger_grp0   : 1;
 337  unsigned int timer_grp0     : 1;
 338  unsigned int fifo_out       : 1;
 339  unsigned int spu_intr1      : 1;
 340  unsigned int trigger_grp1   : 1;
 341  unsigned int timer_grp1     : 1;
 342  unsigned int fifo_in        : 1;
 343  unsigned int spu_intr2      : 1;
 344  unsigned int trigger_grp2   : 1;
 345  unsigned int fifo_out_extra : 1;
 346  unsigned int dmc_out        : 1;
 347  unsigned int spu_intr3      : 1;
 348  unsigned int trigger_grp3   : 1;
 349  unsigned int fifo_in_extra  : 1;
 350  unsigned int dmc_in         : 1;
 351  unsigned int dummy1         : 16;
 352} reg_iop_sw_mpu_r_intr_grp0;
 353#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
 354
 355/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
 356typedef struct {
 357  unsigned int spu_intr0      : 1;
 358  unsigned int trigger_grp0   : 1;
 359  unsigned int timer_grp0     : 1;
 360  unsigned int fifo_out       : 1;
 361  unsigned int spu_intr1      : 1;
 362  unsigned int trigger_grp1   : 1;
 363  unsigned int timer_grp1     : 1;
 364  unsigned int fifo_in        : 1;
 365  unsigned int spu_intr2      : 1;
 366  unsigned int trigger_grp2   : 1;
 367  unsigned int fifo_out_extra : 1;
 368  unsigned int dmc_out        : 1;
 369  unsigned int spu_intr3      : 1;
 370  unsigned int trigger_grp3   : 1;
 371  unsigned int fifo_in_extra  : 1;
 372  unsigned int dmc_in         : 1;
 373  unsigned int dummy1         : 16;
 374} reg_iop_sw_mpu_r_masked_intr_grp0;
 375#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
 376
 377/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
 378typedef struct {
 379  unsigned int spu_intr4      : 1;
 380  unsigned int trigger_grp4   : 1;
 381  unsigned int fifo_out_extra : 1;
 382  unsigned int dmc_out        : 1;
 383  unsigned int spu_intr5      : 1;
 384  unsigned int trigger_grp5   : 1;
 385  unsigned int fifo_in_extra  : 1;
 386  unsigned int dmc_in         : 1;
 387  unsigned int spu_intr6      : 1;
 388  unsigned int trigger_grp6   : 1;
 389  unsigned int timer_grp0     : 1;
 390  unsigned int fifo_out       : 1;
 391  unsigned int spu_intr7      : 1;
 392  unsigned int trigger_grp7   : 1;
 393  unsigned int timer_grp1     : 1;
 394  unsigned int fifo_in        : 1;
 395  unsigned int dummy1         : 16;
 396} reg_iop_sw_mpu_rw_intr_grp1_mask;
 397#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
 398#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
 399
 400/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
 401typedef struct {
 402  unsigned int spu_intr4 : 1;
 403  unsigned int dummy1    : 3;
 404  unsigned int spu_intr5 : 1;
 405  unsigned int dummy2    : 3;
 406  unsigned int spu_intr6 : 1;
 407  unsigned int dummy3    : 3;
 408  unsigned int spu_intr7 : 1;
 409  unsigned int dummy4    : 19;
 410} reg_iop_sw_mpu_rw_ack_intr_grp1;
 411#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
 412#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
 413
 414/* Register r_intr_grp1, scope iop_sw_mpu, type r */
 415typedef struct {
 416  unsigned int spu_intr4      : 1;
 417  unsigned int trigger_grp4   : 1;
 418  unsigned int fifo_out_extra : 1;
 419  unsigned int dmc_out        : 1;
 420  unsigned int spu_intr5      : 1;
 421  unsigned int trigger_grp5   : 1;
 422  unsigned int fifo_in_extra  : 1;
 423  unsigned int dmc_in         : 1;
 424  unsigned int spu_intr6      : 1;
 425  unsigned int trigger_grp6   : 1;
 426  unsigned int timer_grp0     : 1;
 427  unsigned int fifo_out       : 1;
 428  unsigned int spu_intr7      : 1;
 429  unsigned int trigger_grp7   : 1;
 430  unsigned int timer_grp1     : 1;
 431  unsigned int fifo_in        : 1;
 432  unsigned int dummy1         : 16;
 433} reg_iop_sw_mpu_r_intr_grp1;
 434#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
 435
 436/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
 437typedef struct {
 438  unsigned int spu_intr4      : 1;
 439  unsigned int trigger_grp4   : 1;
 440  unsigned int fifo_out_extra : 1;
 441  unsigned int dmc_out        : 1;
 442  unsigned int spu_intr5      : 1;
 443  unsigned int trigger_grp5   : 1;
 444  unsigned int fifo_in_extra  : 1;
 445  unsigned int dmc_in         : 1;
 446  unsigned int spu_intr6      : 1;
 447  unsigned int trigger_grp6   : 1;
 448  unsigned int timer_grp0     : 1;
 449  unsigned int fifo_out       : 1;
 450  unsigned int spu_intr7      : 1;
 451  unsigned int trigger_grp7   : 1;
 452  unsigned int timer_grp1     : 1;
 453  unsigned int fifo_in        : 1;
 454  unsigned int dummy1         : 16;
 455} reg_iop_sw_mpu_r_masked_intr_grp1;
 456#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
 457
 458/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
 459typedef struct {
 460  unsigned int spu_intr8      : 1;
 461  unsigned int trigger_grp0   : 1;
 462  unsigned int timer_grp0     : 1;
 463  unsigned int fifo_out       : 1;
 464  unsigned int spu_intr9      : 1;
 465  unsigned int trigger_grp1   : 1;
 466  unsigned int timer_grp1     : 1;
 467  unsigned int fifo_in        : 1;
 468  unsigned int spu_intr10     : 1;
 469  unsigned int trigger_grp2   : 1;
 470  unsigned int fifo_out_extra : 1;
 471  unsigned int dmc_out        : 1;
 472  unsigned int spu_intr11     : 1;
 473  unsigned int trigger_grp3   : 1;
 474  unsigned int fifo_in_extra  : 1;
 475  unsigned int dmc_in         : 1;
 476  unsigned int dummy1         : 16;
 477} reg_iop_sw_mpu_rw_intr_grp2_mask;
 478#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
 479#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
 480
 481/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
 482typedef struct {
 483  unsigned int spu_intr8  : 1;
 484  unsigned int dummy1     : 3;
 485  unsigned int spu_intr9  : 1;
 486  unsigned int dummy2     : 3;
 487  unsigned int spu_intr10 : 1;
 488  unsigned int dummy3     : 3;
 489  unsigned int spu_intr11 : 1;
 490  unsigned int dummy4     : 19;
 491} reg_iop_sw_mpu_rw_ack_intr_grp2;
 492#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
 493#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
 494
 495/* Register r_intr_grp2, scope iop_sw_mpu, type r */
 496typedef struct {
 497  unsigned int spu_intr8      : 1;
 498  unsigned int trigger_grp0   : 1;
 499  unsigned int timer_grp0     : 1;
 500  unsigned int fifo_out       : 1;
 501  unsigned int spu_intr9      : 1;
 502  unsigned int trigger_grp1   : 1;
 503  unsigned int timer_grp1     : 1;
 504  unsigned int fifo_in        : 1;
 505  unsigned int spu_intr10     : 1;
 506  unsigned int trigger_grp2   : 1;
 507  unsigned int fifo_out_extra : 1;
 508  unsigned int dmc_out        : 1;
 509  unsigned int spu_intr11     : 1;
 510  unsigned int trigger_grp3   : 1;
 511  unsigned int fifo_in_extra  : 1;
 512  unsigned int dmc_in         : 1;
 513  unsigned int dummy1         : 16;
 514} reg_iop_sw_mpu_r_intr_grp2;
 515#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
 516
 517/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
 518typedef struct {
 519  unsigned int spu_intr8      : 1;
 520  unsigned int trigger_grp0   : 1;
 521  unsigned int timer_grp0     : 1;
 522  unsigned int fifo_out       : 1;
 523  unsigned int spu_intr9      : 1;
 524  unsigned int trigger_grp1   : 1;
 525  unsigned int timer_grp1     : 1;
 526  unsigned int fifo_in        : 1;
 527  unsigned int spu_intr10     : 1;
 528  unsigned int trigger_grp2   : 1;
 529  unsigned int fifo_out_extra : 1;
 530  unsigned int dmc_out        : 1;
 531  unsigned int spu_intr11     : 1;
 532  unsigned int trigger_grp3   : 1;
 533  unsigned int fifo_in_extra  : 1;
 534  unsigned int dmc_in         : 1;
 535  unsigned int dummy1         : 16;
 536} reg_iop_sw_mpu_r_masked_intr_grp2;
 537#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
 538
 539/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
 540typedef struct {
 541  unsigned int spu_intr12     : 1;
 542  unsigned int trigger_grp4   : 1;
 543  unsigned int fifo_out_extra : 1;
 544  unsigned int dmc_out        : 1;
 545  unsigned int spu_intr13     : 1;
 546  unsigned int trigger_grp5   : 1;
 547  unsigned int fifo_in_extra  : 1;
 548  unsigned int dmc_in         : 1;
 549  unsigned int spu_intr14     : 1;
 550  unsigned int trigger_grp6   : 1;
 551  unsigned int timer_grp0     : 1;
 552  unsigned int fifo_out       : 1;
 553  unsigned int spu_intr15     : 1;
 554  unsigned int trigger_grp7   : 1;
 555  unsigned int timer_grp1     : 1;
 556  unsigned int fifo_in        : 1;
 557  unsigned int dummy1         : 16;
 558} reg_iop_sw_mpu_rw_intr_grp3_mask;
 559#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
 560#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
 561
 562/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
 563typedef struct {
 564  unsigned int spu_intr12 : 1;
 565  unsigned int dummy1     : 3;
 566  unsigned int spu_intr13 : 1;
 567  unsigned int dummy2     : 3;
 568  unsigned int spu_intr14 : 1;
 569  unsigned int dummy3     : 3;
 570  unsigned int spu_intr15 : 1;
 571  unsigned int dummy4     : 19;
 572} reg_iop_sw_mpu_rw_ack_intr_grp3;
 573#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
 574#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
 575
 576/* Register r_intr_grp3, scope iop_sw_mpu, type r */
 577typedef struct {
 578  unsigned int spu_intr12     : 1;
 579  unsigned int trigger_grp4   : 1;
 580  unsigned int fifo_out_extra : 1;
 581  unsigned int dmc_out        : 1;
 582  unsigned int spu_intr13     : 1;
 583  unsigned int trigger_grp5   : 1;
 584  unsigned int fifo_in_extra  : 1;
 585  unsigned int dmc_in         : 1;
 586  unsigned int spu_intr14     : 1;
 587  unsigned int trigger_grp6   : 1;
 588  unsigned int timer_grp0     : 1;
 589  unsigned int fifo_out       : 1;
 590  unsigned int spu_intr15     : 1;
 591  unsigned int trigger_grp7   : 1;
 592  unsigned int timer_grp1     : 1;
 593  unsigned int fifo_in        : 1;
 594  unsigned int dummy1         : 16;
 595} reg_iop_sw_mpu_r_intr_grp3;
 596#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
 597
 598/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
 599typedef struct {
 600  unsigned int spu_intr12     : 1;
 601  unsigned int trigger_grp4   : 1;
 602  unsigned int fifo_out_extra : 1;
 603  unsigned int dmc_out        : 1;
 604  unsigned int spu_intr13     : 1;
 605  unsigned int trigger_grp5   : 1;
 606  unsigned int fifo_in_extra  : 1;
 607  unsigned int dmc_in         : 1;
 608  unsigned int spu_intr14     : 1;
 609  unsigned int trigger_grp6   : 1;
 610  unsigned int timer_grp0     : 1;
 611  unsigned int fifo_out       : 1;
 612  unsigned int spu_intr15     : 1;
 613  unsigned int trigger_grp7   : 1;
 614  unsigned int timer_grp1     : 1;
 615  unsigned int fifo_in        : 1;
 616  unsigned int dummy1         : 16;
 617} reg_iop_sw_mpu_r_masked_intr_grp3;
 618#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
 619
 620
 621/* Constants */
 622enum {
 623  regk_iop_sw_mpu_copy                     = 0x00000000,
 624  regk_iop_sw_mpu_cpu                      = 0x00000000,
 625  regk_iop_sw_mpu_mpu                      = 0x00000001,
 626  regk_iop_sw_mpu_no                       = 0x00000000,
 627  regk_iop_sw_mpu_nop                      = 0x00000000,
 628  regk_iop_sw_mpu_rd                       = 0x00000002,
 629  regk_iop_sw_mpu_reg_copy                 = 0x00000001,
 630  regk_iop_sw_mpu_rw_bus_clr_mask_default  = 0x00000000,
 631  regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
 632  regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
 633  regk_iop_sw_mpu_rw_bus_set_mask_default  = 0x00000000,
 634  regk_iop_sw_mpu_rw_gio_clr_mask_default  = 0x00000000,
 635  regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
 636  regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
 637  regk_iop_sw_mpu_rw_gio_set_mask_default  = 0x00000000,
 638  regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
 639  regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
 640  regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
 641  regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
 642  regk_iop_sw_mpu_rw_sw_cfg_owner_default  = 0x00000000,
 643  regk_iop_sw_mpu_set                      = 0x00000001,
 644  regk_iop_sw_mpu_spu                      = 0x00000002,
 645  regk_iop_sw_mpu_wr                       = 0x00000003,
 646  regk_iop_sw_mpu_yes                      = 0x00000001
 647};
 648#endif /* __iop_sw_mpu_defs_h */
 649