LXR linux/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache

   1#ifndef __l2cache_defs_h
   2#define __l2cache_defs_h
   3
   4/*
   5 * This file is autogenerated from
   6 *   file:           l2cache.r
   7 * 
   8 *   by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
   9 * Any changes here will be lost.
  10 *
  11 * -*- buffer-read-only: t -*-
  12 */
  13/* Main access macros */
  14#ifndef REG_RD
  15#define REG_RD( scope, inst, reg ) \
  16  REG_READ( reg_##scope##_##reg, \
  17            (inst) + REG_RD_ADDR_##scope##_##reg )
  18#endif
  19
  20#ifndef REG_WR
  21#define REG_WR( scope, inst, reg, val ) \
  22  REG_WRITE( reg_##scope##_##reg, \
  23             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  24#endif
  25
  26#ifndef REG_RD_VECT
  27#define REG_RD_VECT( scope, inst, reg, index ) \
  28  REG_READ( reg_##scope##_##reg, \
  29            (inst) + REG_RD_ADDR_##scope##_##reg + \
  30            (index) * STRIDE_##scope##_##reg )
  31#endif
  32
  33#ifndef REG_WR_VECT
  34#define REG_WR_VECT( scope, inst, reg, index, val ) \
  35  REG_WRITE( reg_##scope##_##reg, \
  36             (inst) + REG_WR_ADDR_##scope##_##reg + \
  37             (index) * STRIDE_##scope##_##reg, (val) )
  38#endif
  39
  40#ifndef REG_RD_INT
  41#define REG_RD_INT( scope, inst, reg ) \
  42  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  43#endif
  44
  45#ifndef REG_WR_INT
  46#define REG_WR_INT( scope, inst, reg, val ) \
  47  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  48#endif
  49
  50#ifndef REG_RD_INT_VECT
  51#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  52  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  53            (index) * STRIDE_##scope##_##reg )
  54#endif
  55
  56#ifndef REG_WR_INT_VECT
  57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  58  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  59             (index) * STRIDE_##scope##_##reg, (val) )
  60#endif
  61
  62#ifndef REG_TYPE_CONV
  63#define REG_TYPE_CONV( type, orgtype, val ) \
  64  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  65#endif
  66
  67#ifndef reg_page_size
  68#define reg_page_size 8192
  69#endif
  70
  71#ifndef REG_ADDR
  72#define REG_ADDR( scope, inst, reg ) \
  73  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  74#endif
  75
  76#ifndef REG_ADDR_VECT
  77#define REG_ADDR_VECT( scope, inst, reg, index ) \
  78  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  79    (index) * STRIDE_##scope##_##reg )
  80#endif
  81
  82/* C-code for register scope l2cache */
  83
  84/* Register rw_cfg, scope l2cache, type rw */
  85typedef struct {
  86  unsigned int en : 1;
  87  unsigned int dummy1 : 31;
  88} reg_l2cache_rw_cfg;
  89#define REG_RD_ADDR_l2cache_rw_cfg 0
  90#define REG_WR_ADDR_l2cache_rw_cfg 0
  91
  92/* Register rw_ctrl, scope l2cache, type rw */
  93typedef struct {
  94  unsigned int dummy1 : 7;
  95  unsigned int cbase : 9;
  96  unsigned int dummy2 : 4;
  97  unsigned int csize : 10;
  98  unsigned int dummy3 : 2;
  99} reg_l2cache_rw_ctrl;
 100#define REG_RD_ADDR_l2cache_rw_ctrl 4
 101#define REG_WR_ADDR_l2cache_rw_ctrl 4
 102
 103/* Register rw_idxop, scope l2cache, type rw */
 104typedef struct {
 105  unsigned int idx : 10;
 106  unsigned int dummy1 : 14;
 107  unsigned int way : 3;
 108  unsigned int dummy2 : 2;
 109  unsigned int cmd : 3;
 110} reg_l2cache_rw_idxop;
 111#define REG_RD_ADDR_l2cache_rw_idxop 8
 112#define REG_WR_ADDR_l2cache_rw_idxop 8
 113
 114/* Register rw_addrop_addr, scope l2cache, type rw */
 115typedef struct {
 116  unsigned int addr : 32;
 117} reg_l2cache_rw_addrop_addr;
 118#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
 119#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
 120
 121/* Register rw_addrop_ctrl, scope l2cache, type rw */
 122typedef struct {
 123  unsigned int size : 16;
 124  unsigned int dummy1 : 13;
 125  unsigned int cmd  : 3;
 126} reg_l2cache_rw_addrop_ctrl;
 127#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
 128#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
 129
 130
 131/* Constants */
 132enum {
 133  regk_l2cache_flush                       = 0x00000001,
 134  regk_l2cache_no                          = 0x00000000,
 135  regk_l2cache_rw_addrop_addr_default      = 0x00000000,
 136  regk_l2cache_rw_addrop_ctrl_default      = 0x00000000,
 137  regk_l2cache_rw_cfg_default              = 0x00000000,
 138  regk_l2cache_rw_ctrl_default             = 0x00000000,
 139  regk_l2cache_rw_idxop_default            = 0x00000000,
 140  regk_l2cache_yes                         = 0x00000001
 141};
 142#endif /* __l2cache_defs_h */
 143