1#ifndef _ASM_IA64_PGTABLE_H
2#define _ASM_IA64_PGTABLE_H
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16#include <asm/mman.h>
17#include <asm/page.h>
18#include <asm/processor.h>
19#include <asm/system.h>
20#include <asm/types.h>
21
22#define IA64_MAX_PHYS_BITS 50
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28
29#define _PAGE_P_BIT 0
30#define _PAGE_A_BIT 5
31#define _PAGE_D_BIT 6
32
33#define _PAGE_P (1 << _PAGE_P_BIT)
34#define _PAGE_MA_WB (0x0 << 2)
35#define _PAGE_MA_UC (0x4 << 2)
36#define _PAGE_MA_UCE (0x5 << 2)
37#define _PAGE_MA_WC (0x6 << 2)
38#define _PAGE_MA_NAT (0x7 << 2)
39#define _PAGE_MA_MASK (0x7 << 2)
40#define _PAGE_PL_0 (0 << 7)
41#define _PAGE_PL_1 (1 << 7)
42#define _PAGE_PL_2 (2 << 7)
43#define _PAGE_PL_3 (3 << 7)
44#define _PAGE_PL_MASK (3 << 7)
45#define _PAGE_AR_R (0 << 9)
46#define _PAGE_AR_RX (1 << 9)
47#define _PAGE_AR_RW (2 << 9)
48#define _PAGE_AR_RWX (3 << 9)
49#define _PAGE_AR_R_RW (4 << 9)
50#define _PAGE_AR_RX_RWX (5 << 9)
51#define _PAGE_AR_RWX_RW (6 << 9)
52#define _PAGE_AR_X_RX (7 << 9)
53#define _PAGE_AR_MASK (7 << 9)
54#define _PAGE_AR_SHIFT 9
55#define _PAGE_A (1 << _PAGE_A_BIT)
56#define _PAGE_D (1 << _PAGE_D_BIT)
57#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
58#define _PAGE_ED (__IA64_UL(1) << 52)
59#define _PAGE_PROTNONE (__IA64_UL(1) << 63)
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61
62#define _PAGE_FILE (1 << 1)
63
64#define _PFN_MASK _PAGE_PPN_MASK
65
66#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
67
68#define _PAGE_SIZE_4K 12
69#define _PAGE_SIZE_8K 13
70#define _PAGE_SIZE_16K 14
71#define _PAGE_SIZE_64K 16
72#define _PAGE_SIZE_256K 18
73#define _PAGE_SIZE_1M 20
74#define _PAGE_SIZE_4M 22
75#define _PAGE_SIZE_16M 24
76#define _PAGE_SIZE_64M 26
77#define _PAGE_SIZE_256M 28
78#define _PAGE_SIZE_1G 30
79#define _PAGE_SIZE_4G 32
80
81#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
82#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
83#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
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87
88#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
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92
93#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
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100
101#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
102#define PMD_SIZE (1UL << PMD_SHIFT)
103#define PMD_MASK (~(PMD_SIZE-1))
104#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
105
106#ifdef CONFIG_PGTABLE_4
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113#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
114#define PUD_SIZE (1UL << PUD_SHIFT)
115#define PUD_MASK (~(PUD_SIZE-1))
116#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
117#endif
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123
124#ifdef CONFIG_PGTABLE_4
125#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
126#else
127#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
128#endif
129#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
130#define PGDIR_MASK (~(PGDIR_SIZE-1))
131#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
132#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
133#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8)
134#define FIRST_USER_ADDRESS 0
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141#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
142#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
143#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
144#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
145#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
146#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
147#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
148#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
149#define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \
150 _PAGE_MA_UC)
151
152# ifndef __ASSEMBLY__
153
154#include <linux/sched.h>
155#include <linux/bitops.h>
156#include <asm/cacheflush.h>
157#include <asm/mmu_context.h>
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168#define __P000 PAGE_NONE
169#define __P001 PAGE_READONLY
170#define __P010 PAGE_READONLY
171#define __P011 PAGE_READONLY
172#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
173#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
174#define __P110 PAGE_COPY_EXEC
175#define __P111 PAGE_COPY_EXEC
176
177#define __S000 PAGE_NONE
178#define __S001 PAGE_READONLY
179#define __S010 PAGE_SHARED
180#define __S011 PAGE_SHARED
181#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
182#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
183#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
184#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
185
186#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
187#ifdef CONFIG_PGTABLE_4
188#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
189#endif
190#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
191#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
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200static inline long
201ia64_phys_addr_valid (unsigned long addr)
202{
203 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
204}
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219#define kern_addr_valid(addr) (1)
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228#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
229#ifdef CONFIG_VIRTUAL_MEM_MAP
230# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
231# define VMALLOC_END vmalloc_end
232 extern unsigned long vmalloc_end;
233#else
234#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
235
236# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
237# define vmemmap ((struct page *)VMALLOC_END)
238#else
239# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
240#endif
241#endif
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243
244#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
245#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
246
247#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
248#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE)
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253
254#define pfn_pte(pfn, pgprot) \
255({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
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257
258#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
259
260#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
261
262
263#define mk_pte_phys(physpage, pgprot) \
264({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
265
266#define pte_modify(_pte, newprot) \
267 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
268
269#define pte_none(pte) (!pte_val(pte))
270#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
271#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
272
273#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
274
275#define pmd_none(pmd) (!pmd_val(pmd))
276#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
277#define pmd_present(pmd) (pmd_val(pmd) != 0UL)
278#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
279#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
280#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
281
282#define pud_none(pud) (!pud_val(pud))
283#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
284#define pud_present(pud) (pud_val(pud) != 0UL)
285#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
286#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
287#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET))
288
289#ifdef CONFIG_PGTABLE_4
290#define pgd_none(pgd) (!pgd_val(pgd))
291#define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
292#define pgd_present(pgd) (pgd_val(pgd) != 0UL)
293#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
294#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
295#define pgd_page(pgd) virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
296#endif
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301#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
302#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
303#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
304#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
305#define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
306#define pte_special(pte) 0
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312#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
313#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
314#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
315#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
316#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
317#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
318#define pte_mkhuge(pte) (__pte(pte_val(pte)))
319#define pte_mkspecial(pte) (pte)
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330#define pte_present_exec_user(pte)\
331 ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
332 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
333
334extern void __ia64_sync_icache_dcache(pte_t pteval);
335static inline void set_pte(pte_t *ptep, pte_t pteval)
336{
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339
340
341 if (pte_present_exec_user(pteval) &&
342 (!pte_present(*ptep) ||
343 pte_pfn(*ptep) != pte_pfn(pteval)))
344
345 __ia64_sync_icache_dcache(pteval);
346 *ptep = pteval;
347}
348
349#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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357#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
358#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
359#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
360
361struct file;
362extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
363 unsigned long size, pgprot_t vma_prot);
364#define __HAVE_PHYS_MEM_ACCESS_PROT
365
366static inline unsigned long
367pgd_index (unsigned long address)
368{
369 unsigned long region = address >> 61;
370 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
371
372 return (region << (PAGE_SHIFT - 6)) | l1index;
373}
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376
377static inline pgd_t*
378pgd_offset (const struct mm_struct *mm, unsigned long address)
379{
380 return mm->pgd + pgd_index(address);
381}
382
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384
385#define pgd_offset_k(addr) \
386 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
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391#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
392
393#ifdef CONFIG_PGTABLE_4
394
395#define pud_offset(dir,addr) \
396 ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
397#endif
398
399
400#define pmd_offset(dir,addr) \
401 ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
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407#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
408#define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
409#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
410#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
411#define pte_unmap(pte) do { } while (0)
412#define pte_unmap_nested(pte) do { } while (0)
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414
415
416static inline int
417ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
418{
419#ifdef CONFIG_SMP
420 if (!pte_young(*ptep))
421 return 0;
422 return test_and_clear_bit(_PAGE_A_BIT, ptep);
423#else
424 pte_t pte = *ptep;
425 if (!pte_young(pte))
426 return 0;
427 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
428 return 1;
429#endif
430}
431
432static inline pte_t
433ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
434{
435#ifdef CONFIG_SMP
436 return __pte(xchg((long *) ptep, 0));
437#else
438 pte_t pte = *ptep;
439 pte_clear(mm, addr, ptep);
440 return pte;
441#endif
442}
443
444static inline void
445ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
446{
447#ifdef CONFIG_SMP
448 unsigned long new, old;
449
450 do {
451 old = pte_val(*ptep);
452 new = pte_val(pte_wrprotect(__pte (old)));
453 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
454#else
455 pte_t old_pte = *ptep;
456 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
457#endif
458}
459
460static inline int
461pte_same (pte_t a, pte_t b)
462{
463 return pte_val(a) == pte_val(b);
464}
465
466#define update_mmu_cache(vma, address, pte) do { } while (0)
467
468extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
469extern void paging_init (void);
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490#define __swp_type(entry) (((entry).val >> 2) & 0x7f)
491#define __swp_offset(entry) (((entry).val << 1) >> 10)
492#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
493#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
494#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
495
496#define PTE_FILE_MAX_BITS 61
497#define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
498#define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
499
500#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
501 remap_pfn_range(vma, vaddr, pfn, size, prot)
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507extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
508extern struct page *zero_page_memmap_ptr;
509#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
510
511
512#define HAVE_ARCH_UNMAPPED_AREA
513
514#ifdef CONFIG_HUGETLB_PAGE
515#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
516#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
517#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
518#endif
519
520
521#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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544#ifdef CONFIG_SMP
545# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
546({ \
547 int __changed = !pte_same(*(__ptep), __entry); \
548 if (__changed && __safely_writable) { \
549 set_pte(__ptep, __entry); \
550 flush_tlb_page(__vma, __addr); \
551 } \
552 __changed; \
553})
554#else
555# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
556({ \
557 int __changed = !pte_same(*(__ptep), __entry); \
558 if (__changed) { \
559 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \
560 flush_tlb_page(__vma, __addr); \
561 } \
562 __changed; \
563})
564#endif
565
566# ifdef CONFIG_VIRTUAL_MEM_MAP
567
568# define __HAVE_ARCH_MEMMAP_INIT
569 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
570 unsigned long start_pfn);
571# endif
572# endif
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579#if defined(CONFIG_IA64_GRANULE_64MB)
580# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
581#elif defined(CONFIG_IA64_GRANULE_16MB)
582# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
583#endif
584#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
585
586
587
588#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
589#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
590
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593
594#define pgtable_cache_init() do { } while (0)
595
596
597#define FIXADDR_USER_START GATE_ADDR
598#ifdef HAVE_BUGGY_SEGREL
599# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
600#else
601# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
602#endif
603
604#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
605#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
606#define __HAVE_ARCH_PTEP_SET_WRPROTECT
607#define __HAVE_ARCH_PTE_SAME
608#define __HAVE_ARCH_PGD_OFFSET_GATE
609
610
611#ifndef CONFIG_PGTABLE_4
612#include <asm-generic/pgtable-nopud.h>
613#endif
614#include <asm-generic/pgtable.h>
615
616#endif
617