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83#include <linux/acpi.h>
84#include <linux/init.h>
85#include <linux/irq.h>
86#include <linux/kernel.h>
87#include <linux/list.h>
88#include <linux/pci.h>
89#include <linux/smp.h>
90#include <linux/string.h>
91#include <linux/bootmem.h>
92
93#include <asm/delay.h>
94#include <asm/hw_irq.h>
95#include <asm/io.h>
96#include <asm/iosapic.h>
97#include <asm/machvec.h>
98#include <asm/processor.h>
99#include <asm/ptrace.h>
100#include <asm/system.h>
101
102#undef DEBUG_INTERRUPT_ROUTING
103
104#ifdef DEBUG_INTERRUPT_ROUTING
105#define DBG(fmt...) printk(fmt)
106#else
107#define DBG(fmt...)
108#endif
109
110#define NR_PREALLOCATE_RTE_ENTRIES \
111 (PAGE_SIZE / sizeof(struct iosapic_rte_info))
112#define RTE_PREALLOCATED (1)
113
114static DEFINE_SPINLOCK(iosapic_lock);
115
116
117
118
119
120
121#define NO_REF_RTE 0
122
123static struct iosapic {
124 char __iomem *addr;
125 unsigned int gsi_base;
126 unsigned short num_rte;
127 int rtes_inuse;
128#ifdef CONFIG_NUMA
129 unsigned short node;
130#endif
131 spinlock_t lock;
132} iosapic_lists[NR_IOSAPICS];
133
134struct iosapic_rte_info {
135 struct list_head rte_list;
136 char rte_index;
137 int refcnt;
138 unsigned int flags;
139 struct iosapic *iosapic;
140} ____cacheline_aligned;
141
142static struct iosapic_intr_info {
143 struct list_head rtes;
144
145 int count;
146 u32 low32;
147
148 unsigned int dest;
149 unsigned char dmode : 3;
150 unsigned char polarity: 1;
151
152 unsigned char trigger : 1;
153} iosapic_intr_info[NR_IRQS];
154
155static unsigned char pcat_compat __devinitdata;
156
157static int iosapic_kmalloc_ok;
158static LIST_HEAD(free_rte_list);
159
160static inline void
161iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
162{
163 unsigned long flags;
164
165 spin_lock_irqsave(&iosapic->lock, flags);
166 __iosapic_write(iosapic->addr, reg, val);
167 spin_unlock_irqrestore(&iosapic->lock, flags);
168}
169
170
171
172
173static inline int
174find_iosapic (unsigned int gsi)
175{
176 int i;
177
178 for (i = 0; i < NR_IOSAPICS; i++) {
179 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
180 iosapic_lists[i].num_rte)
181 return i;
182 }
183
184 return -1;
185}
186
187static inline int __gsi_to_irq(unsigned int gsi)
188{
189 int irq;
190 struct iosapic_intr_info *info;
191 struct iosapic_rte_info *rte;
192
193 for (irq = 0; irq < NR_IRQS; irq++) {
194 info = &iosapic_intr_info[irq];
195 list_for_each_entry(rte, &info->rtes, rte_list)
196 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
197 return irq;
198 }
199 return -1;
200}
201
202int
203gsi_to_irq (unsigned int gsi)
204{
205 unsigned long flags;
206 int irq;
207
208 spin_lock_irqsave(&iosapic_lock, flags);
209 irq = __gsi_to_irq(gsi);
210 spin_unlock_irqrestore(&iosapic_lock, flags);
211 return irq;
212}
213
214static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
215{
216 struct iosapic_rte_info *rte;
217
218 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
219 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
220 return rte;
221 return NULL;
222}
223
224static void
225set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
226{
227 unsigned long pol, trigger, dmode;
228 u32 low32, high32;
229 int rte_index;
230 char redir;
231 struct iosapic_rte_info *rte;
232 ia64_vector vector = irq_to_vector(irq);
233
234 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
235
236 rte = find_rte(irq, gsi);
237 if (!rte)
238 return;
239
240 rte_index = rte->rte_index;
241 pol = iosapic_intr_info[irq].polarity;
242 trigger = iosapic_intr_info[irq].trigger;
243 dmode = iosapic_intr_info[irq].dmode;
244
245 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
246
247#ifdef CONFIG_SMP
248 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
249#endif
250
251 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
252 (trigger << IOSAPIC_TRIGGER_SHIFT) |
253 (dmode << IOSAPIC_DELIVERY_SHIFT) |
254 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
255 vector);
256
257
258 high32 = (dest << IOSAPIC_DEST_SHIFT);
259
260 iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
261 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
262 iosapic_intr_info[irq].low32 = low32;
263 iosapic_intr_info[irq].dest = dest;
264}
265
266static void
267nop (unsigned int irq)
268{
269
270}
271
272
273#ifdef CONFIG_KEXEC
274void
275kexec_disable_iosapic(void)
276{
277 struct iosapic_intr_info *info;
278 struct iosapic_rte_info *rte;
279 ia64_vector vec;
280 int irq;
281
282 for (irq = 0; irq < NR_IRQS; irq++) {
283 info = &iosapic_intr_info[irq];
284 vec = irq_to_vector(irq);
285 list_for_each_entry(rte, &info->rtes,
286 rte_list) {
287 iosapic_write(rte->iosapic,
288 IOSAPIC_RTE_LOW(rte->rte_index),
289 IOSAPIC_MASK|vec);
290 iosapic_eoi(rte->iosapic->addr, vec);
291 }
292 }
293}
294#endif
295
296static void
297mask_irq (unsigned int irq)
298{
299 u32 low32;
300 int rte_index;
301 struct iosapic_rte_info *rte;
302
303 if (!iosapic_intr_info[irq].count)
304 return;
305
306
307 low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
308 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
309 rte_index = rte->rte_index;
310 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
311 }
312}
313
314static void
315unmask_irq (unsigned int irq)
316{
317 u32 low32;
318 int rte_index;
319 struct iosapic_rte_info *rte;
320
321 if (!iosapic_intr_info[irq].count)
322 return;
323
324 low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
325 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
326 rte_index = rte->rte_index;
327 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
328 }
329}
330
331
332static int
333iosapic_set_affinity(unsigned int irq, const struct cpumask *mask)
334{
335#ifdef CONFIG_SMP
336 u32 high32, low32;
337 int cpu, dest, rte_index;
338 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
339 struct iosapic_rte_info *rte;
340 struct iosapic *iosapic;
341
342 irq &= (~IA64_IRQ_REDIRECTED);
343
344 cpu = cpumask_first_and(cpu_online_mask, mask);
345 if (cpu >= nr_cpu_ids)
346 return -1;
347
348 if (irq_prepare_move(irq, cpu))
349 return -1;
350
351 dest = cpu_physical_id(cpu);
352
353 if (!iosapic_intr_info[irq].count)
354 return -1;
355
356 set_irq_affinity_info(irq, dest, redir);
357
358
359 high32 = dest << IOSAPIC_DEST_SHIFT;
360
361 low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
362 if (redir)
363
364 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
365 else
366
367 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
368 low32 &= IOSAPIC_VECTOR_MASK;
369 low32 |= irq_to_vector(irq);
370
371 iosapic_intr_info[irq].low32 = low32;
372 iosapic_intr_info[irq].dest = dest;
373 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
374 iosapic = rte->iosapic;
375 rte_index = rte->rte_index;
376 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
377 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
378 }
379
380#endif
381 return 0;
382}
383
384
385
386
387
388static unsigned int
389iosapic_startup_level_irq (unsigned int irq)
390{
391 unmask_irq(irq);
392 return 0;
393}
394
395static void
396iosapic_end_level_irq (unsigned int irq)
397{
398 ia64_vector vec = irq_to_vector(irq);
399 struct iosapic_rte_info *rte;
400 int do_unmask_irq = 0;
401
402 irq_complete_move(irq);
403 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
404 do_unmask_irq = 1;
405 mask_irq(irq);
406 }
407
408 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
409 iosapic_eoi(rte->iosapic->addr, vec);
410
411 if (unlikely(do_unmask_irq)) {
412 move_masked_irq(irq);
413 unmask_irq(irq);
414 }
415}
416
417#define iosapic_shutdown_level_irq mask_irq
418#define iosapic_enable_level_irq unmask_irq
419#define iosapic_disable_level_irq mask_irq
420#define iosapic_ack_level_irq nop
421
422static struct irq_chip irq_type_iosapic_level = {
423 .name = "IO-SAPIC-level",
424 .startup = iosapic_startup_level_irq,
425 .shutdown = iosapic_shutdown_level_irq,
426 .enable = iosapic_enable_level_irq,
427 .disable = iosapic_disable_level_irq,
428 .ack = iosapic_ack_level_irq,
429 .end = iosapic_end_level_irq,
430 .mask = mask_irq,
431 .unmask = unmask_irq,
432 .set_affinity = iosapic_set_affinity
433};
434
435
436
437
438
439static unsigned int
440iosapic_startup_edge_irq (unsigned int irq)
441{
442 unmask_irq(irq);
443
444
445
446
447
448 return 0;
449}
450
451static void
452iosapic_ack_edge_irq (unsigned int irq)
453{
454 struct irq_desc *idesc = irq_desc + irq;
455
456 irq_complete_move(irq);
457 move_native_irq(irq);
458
459
460
461
462
463 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
464 (IRQ_PENDING|IRQ_DISABLED))
465 mask_irq(irq);
466}
467
468#define iosapic_enable_edge_irq unmask_irq
469#define iosapic_disable_edge_irq nop
470#define iosapic_end_edge_irq nop
471
472static struct irq_chip irq_type_iosapic_edge = {
473 .name = "IO-SAPIC-edge",
474 .startup = iosapic_startup_edge_irq,
475 .shutdown = iosapic_disable_edge_irq,
476 .enable = iosapic_enable_edge_irq,
477 .disable = iosapic_disable_edge_irq,
478 .ack = iosapic_ack_edge_irq,
479 .end = iosapic_end_edge_irq,
480 .mask = mask_irq,
481 .unmask = unmask_irq,
482 .set_affinity = iosapic_set_affinity
483};
484
485static unsigned int
486iosapic_version (char __iomem *addr)
487{
488
489
490
491
492
493
494
495
496
497 return __iosapic_read(addr, IOSAPIC_VERSION);
498}
499
500static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
501{
502 int i, irq = -ENOSPC, min_count = -1;
503 struct iosapic_intr_info *info;
504
505
506
507
508
509 if (trigger == IOSAPIC_EDGE)
510 return -EINVAL;
511
512 for (i = 0; i < NR_IRQS; i++) {
513 info = &iosapic_intr_info[i];
514 if (info->trigger == trigger && info->polarity == pol &&
515 (info->dmode == IOSAPIC_FIXED ||
516 info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
517 can_request_irq(i, IRQF_SHARED)) {
518 if (min_count == -1 || info->count < min_count) {
519 irq = i;
520 min_count = info->count;
521 }
522 }
523 }
524 return irq;
525}
526
527
528
529
530
531static void __init
532iosapic_reassign_vector (int irq)
533{
534 int new_irq;
535
536 if (iosapic_intr_info[irq].count) {
537 new_irq = create_irq();
538 if (new_irq < 0)
539 panic("%s: out of interrupt vectors!\n", __func__);
540 printk(KERN_INFO "Reassigning vector %d to %d\n",
541 irq_to_vector(irq), irq_to_vector(new_irq));
542 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
543 sizeof(struct iosapic_intr_info));
544 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
545 list_move(iosapic_intr_info[irq].rtes.next,
546 &iosapic_intr_info[new_irq].rtes);
547 memset(&iosapic_intr_info[irq], 0,
548 sizeof(struct iosapic_intr_info));
549 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
550 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
551 }
552}
553
554static struct iosapic_rte_info * __init_refok iosapic_alloc_rte (void)
555{
556 int i;
557 struct iosapic_rte_info *rte;
558 int preallocated = 0;
559
560 if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
561 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
562 NR_PREALLOCATE_RTE_ENTRIES);
563 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
564 list_add(&rte->rte_list, &free_rte_list);
565 }
566
567 if (!list_empty(&free_rte_list)) {
568 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
569 rte_list);
570 list_del(&rte->rte_list);
571 preallocated++;
572 } else {
573 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
574 if (!rte)
575 return NULL;
576 }
577
578 memset(rte, 0, sizeof(struct iosapic_rte_info));
579 if (preallocated)
580 rte->flags |= RTE_PREALLOCATED;
581
582 return rte;
583}
584
585static inline int irq_is_shared (int irq)
586{
587 return (iosapic_intr_info[irq].count > 1);
588}
589
590struct irq_chip*
591ia64_native_iosapic_get_irq_chip(unsigned long trigger)
592{
593 if (trigger == IOSAPIC_EDGE)
594 return &irq_type_iosapic_edge;
595 else
596 return &irq_type_iosapic_level;
597}
598
599static int
600register_intr (unsigned int gsi, int irq, unsigned char delivery,
601 unsigned long polarity, unsigned long trigger)
602{
603 struct irq_desc *idesc;
604 struct irq_chip *irq_type;
605 int index;
606 struct iosapic_rte_info *rte;
607
608 index = find_iosapic(gsi);
609 if (index < 0) {
610 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
611 __func__, gsi);
612 return -ENODEV;
613 }
614
615 rte = find_rte(irq, gsi);
616 if (!rte) {
617 rte = iosapic_alloc_rte();
618 if (!rte) {
619 printk(KERN_WARNING "%s: cannot allocate memory\n",
620 __func__);
621 return -ENOMEM;
622 }
623
624 rte->iosapic = &iosapic_lists[index];
625 rte->rte_index = gsi - rte->iosapic->gsi_base;
626 rte->refcnt++;
627 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
628 iosapic_intr_info[irq].count++;
629 iosapic_lists[index].rtes_inuse++;
630 }
631 else if (rte->refcnt == NO_REF_RTE) {
632 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
633 if (info->count > 0 &&
634 (info->trigger != trigger || info->polarity != polarity)){
635 printk (KERN_WARNING
636 "%s: cannot override the interrupt\n",
637 __func__);
638 return -EINVAL;
639 }
640 rte->refcnt++;
641 iosapic_intr_info[irq].count++;
642 iosapic_lists[index].rtes_inuse++;
643 }
644
645 iosapic_intr_info[irq].polarity = polarity;
646 iosapic_intr_info[irq].dmode = delivery;
647 iosapic_intr_info[irq].trigger = trigger;
648
649 irq_type = iosapic_get_irq_chip(trigger);
650
651 idesc = irq_desc + irq;
652 if (irq_type != NULL && idesc->chip != irq_type) {
653 if (idesc->chip != &no_irq_chip)
654 printk(KERN_WARNING
655 "%s: changing vector %d from %s to %s\n",
656 __func__, irq_to_vector(irq),
657 idesc->chip->name, irq_type->name);
658 idesc->chip = irq_type;
659 }
660 return 0;
661}
662
663static unsigned int
664get_target_cpu (unsigned int gsi, int irq)
665{
666#ifdef CONFIG_SMP
667 static int cpu = -1;
668 extern int cpe_vector;
669 cpumask_t domain = irq_to_domain(irq);
670
671
672
673
674
675 if (iosapic_intr_info[irq].count)
676 return iosapic_intr_info[irq].dest;
677
678
679
680
681
682 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
683 return cpu_physical_id(smp_processor_id());
684
685
686
687
688
689 if (!cpu_online(smp_processor_id()))
690 return cpu_physical_id(smp_processor_id());
691
692#ifdef CONFIG_ACPI
693 if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
694 return get_cpei_target_cpu();
695#endif
696
697#ifdef CONFIG_NUMA
698 {
699 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
700 const struct cpumask *cpu_mask;
701
702 iosapic_index = find_iosapic(gsi);
703 if (iosapic_index < 0 ||
704 iosapic_lists[iosapic_index].node == MAX_NUMNODES)
705 goto skip_numa_setup;
706
707 cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node);
708 num_cpus = 0;
709 for_each_cpu_and(numa_cpu, cpu_mask, &domain) {
710 if (cpu_online(numa_cpu))
711 num_cpus++;
712 }
713
714 if (!num_cpus)
715 goto skip_numa_setup;
716
717
718 cpu_index = irq % num_cpus;
719
720 for_each_cpu_and(numa_cpu, cpu_mask, &domain)
721 if (cpu_online(numa_cpu) && i++ >= cpu_index)
722 break;
723
724 if (numa_cpu < nr_cpu_ids)
725 return cpu_physical_id(numa_cpu);
726 }
727skip_numa_setup:
728#endif
729
730
731
732
733
734 do {
735 if (++cpu >= nr_cpu_ids)
736 cpu = 0;
737 } while (!cpu_online(cpu) || !cpu_isset(cpu, domain));
738
739 return cpu_physical_id(cpu);
740#else
741 return cpu_physical_id(smp_processor_id());
742#endif
743}
744
745static inline unsigned char choose_dmode(void)
746{
747#ifdef CONFIG_SMP
748 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
749 return IOSAPIC_LOWEST_PRIORITY;
750#endif
751 return IOSAPIC_FIXED;
752}
753
754
755
756
757
758
759int
760iosapic_register_intr (unsigned int gsi,
761 unsigned long polarity, unsigned long trigger)
762{
763 int irq, mask = 1, err;
764 unsigned int dest;
765 unsigned long flags;
766 struct iosapic_rte_info *rte;
767 u32 low32;
768 unsigned char dmode;
769
770
771
772
773
774
775 spin_lock_irqsave(&iosapic_lock, flags);
776 irq = __gsi_to_irq(gsi);
777 if (irq > 0) {
778 rte = find_rte(irq, gsi);
779 if(iosapic_intr_info[irq].count == 0) {
780 assign_irq_vector(irq);
781 dynamic_irq_init(irq);
782 } else if (rte->refcnt != NO_REF_RTE) {
783 rte->refcnt++;
784 goto unlock_iosapic_lock;
785 }
786 } else
787 irq = create_irq();
788
789
790 if (irq < 0) {
791 irq = iosapic_find_sharable_irq(trigger, polarity);
792 if (irq < 0)
793 goto unlock_iosapic_lock;
794 }
795
796 spin_lock(&irq_desc[irq].lock);
797 dest = get_target_cpu(gsi, irq);
798 dmode = choose_dmode();
799 err = register_intr(gsi, irq, dmode, polarity, trigger);
800 if (err < 0) {
801 spin_unlock(&irq_desc[irq].lock);
802 irq = err;
803 goto unlock_iosapic_lock;
804 }
805
806
807
808
809
810 low32 = iosapic_intr_info[irq].low32;
811 if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
812 mask = 0;
813 set_rte(gsi, irq, dest, mask);
814
815 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
816 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
817 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
818 cpu_logical_id(dest), dest, irq_to_vector(irq));
819
820 spin_unlock(&irq_desc[irq].lock);
821 unlock_iosapic_lock:
822 spin_unlock_irqrestore(&iosapic_lock, flags);
823 return irq;
824}
825
826void
827iosapic_unregister_intr (unsigned int gsi)
828{
829 unsigned long flags;
830 int irq, index;
831 struct irq_desc *idesc;
832 u32 low32;
833 unsigned long trigger, polarity;
834 unsigned int dest;
835 struct iosapic_rte_info *rte;
836
837
838
839
840
841
842 irq = gsi_to_irq(gsi);
843 if (irq < 0) {
844 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
845 gsi);
846 WARN_ON(1);
847 return;
848 }
849
850 spin_lock_irqsave(&iosapic_lock, flags);
851 if ((rte = find_rte(irq, gsi)) == NULL) {
852 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
853 gsi);
854 WARN_ON(1);
855 goto out;
856 }
857
858 if (--rte->refcnt > 0)
859 goto out;
860
861 idesc = irq_desc + irq;
862 rte->refcnt = NO_REF_RTE;
863
864
865 low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
866 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
867
868 iosapic_intr_info[irq].count--;
869 index = find_iosapic(gsi);
870 iosapic_lists[index].rtes_inuse--;
871 WARN_ON(iosapic_lists[index].rtes_inuse < 0);
872
873 trigger = iosapic_intr_info[irq].trigger;
874 polarity = iosapic_intr_info[irq].polarity;
875 dest = iosapic_intr_info[irq].dest;
876 printk(KERN_INFO
877 "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
878 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
879 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
880 cpu_logical_id(dest), dest, irq_to_vector(irq));
881
882 if (iosapic_intr_info[irq].count == 0) {
883#ifdef CONFIG_SMP
884
885 cpumask_setall(idesc->affinity);
886#endif
887
888 iosapic_intr_info[irq].dest = 0;
889 iosapic_intr_info[irq].dmode = 0;
890 iosapic_intr_info[irq].polarity = 0;
891 iosapic_intr_info[irq].trigger = 0;
892 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
893
894
895 destroy_and_reserve_irq(irq);
896 }
897 out:
898 spin_unlock_irqrestore(&iosapic_lock, flags);
899}
900
901
902
903
904int __init
905iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
906 int iosapic_vector, u16 eid, u16 id,
907 unsigned long polarity, unsigned long trigger)
908{
909 static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
910 unsigned char delivery;
911 int irq, vector, mask = 0;
912 unsigned int dest = ((id << 8) | eid) & 0xffff;
913
914 switch (int_type) {
915 case ACPI_INTERRUPT_PMI:
916 irq = vector = iosapic_vector;
917 bind_irq_vector(irq, vector, CPU_MASK_ALL);
918
919
920
921
922 iosapic_reassign_vector(irq);
923 delivery = IOSAPIC_PMI;
924 break;
925 case ACPI_INTERRUPT_INIT:
926 irq = create_irq();
927 if (irq < 0)
928 panic("%s: out of interrupt vectors!\n", __func__);
929 vector = irq_to_vector(irq);
930 delivery = IOSAPIC_INIT;
931 break;
932 case ACPI_INTERRUPT_CPEI:
933 irq = vector = IA64_CPE_VECTOR;
934 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
935 delivery = IOSAPIC_FIXED;
936 mask = 1;
937 break;
938 default:
939 printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__,
940 int_type);
941 return -1;
942 }
943
944 register_intr(gsi, irq, delivery, polarity, trigger);
945
946 printk(KERN_INFO
947 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
948 " vector %d\n",
949 int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
950 int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
951 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
952 cpu_logical_id(dest), dest, vector);
953
954 set_rte(gsi, irq, dest, mask);
955 return vector;
956}
957
958
959
960
961void __devinit
962iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
963 unsigned long polarity,
964 unsigned long trigger)
965{
966 int vector, irq;
967 unsigned int dest = cpu_physical_id(smp_processor_id());
968 unsigned char dmode;
969
970 irq = vector = isa_irq_to_vector(isa_irq);
971 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
972 dmode = choose_dmode();
973 register_intr(gsi, irq, dmode, polarity, trigger);
974
975 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
976 isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
977 polarity == IOSAPIC_POL_HIGH ? "high" : "low",
978 cpu_logical_id(dest), dest, vector);
979
980 set_rte(gsi, irq, dest, 1);
981}
982
983void __init
984ia64_native_iosapic_pcat_compat_init(void)
985{
986 if (pcat_compat) {
987
988
989
990
991 printk(KERN_INFO
992 "%s: Disabling PC-AT compatible 8259 interrupts\n",
993 __func__);
994 outb(0xff, 0xA1);
995 outb(0xff, 0x21);
996 }
997}
998
999void __init
1000iosapic_system_init (int system_pcat_compat)
1001{
1002 int irq;
1003
1004 for (irq = 0; irq < NR_IRQS; ++irq) {
1005 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
1006
1007 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
1008
1009 iosapic_intr_info[irq].count = 0;
1010 }
1011
1012 pcat_compat = system_pcat_compat;
1013 if (pcat_compat)
1014 iosapic_pcat_compat_init();
1015}
1016
1017static inline int
1018iosapic_alloc (void)
1019{
1020 int index;
1021
1022 for (index = 0; index < NR_IOSAPICS; index++)
1023 if (!iosapic_lists[index].addr)
1024 return index;
1025
1026 printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__);
1027 return -1;
1028}
1029
1030static inline void
1031iosapic_free (int index)
1032{
1033 memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1034}
1035
1036static inline int
1037iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1038{
1039 int index;
1040 unsigned int gsi_end, base, end;
1041
1042
1043 gsi_end = gsi_base + ((ver >> 16) & 0xff);
1044 for (index = 0; index < NR_IOSAPICS; index++) {
1045 if (!iosapic_lists[index].addr)
1046 continue;
1047
1048 base = iosapic_lists[index].gsi_base;
1049 end = base + iosapic_lists[index].num_rte - 1;
1050
1051 if (gsi_end < base || end < gsi_base)
1052 continue;
1053
1054 return -EBUSY;
1055 }
1056 return 0;
1057}
1058
1059int __devinit
1060iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1061{
1062 int num_rte, err, index;
1063 unsigned int isa_irq, ver;
1064 char __iomem *addr;
1065 unsigned long flags;
1066
1067 spin_lock_irqsave(&iosapic_lock, flags);
1068 index = find_iosapic(gsi_base);
1069 if (index >= 0) {
1070 spin_unlock_irqrestore(&iosapic_lock, flags);
1071 return -EBUSY;
1072 }
1073
1074 addr = ioremap(phys_addr, 0);
1075 if (addr == NULL) {
1076 spin_unlock_irqrestore(&iosapic_lock, flags);
1077 return -ENOMEM;
1078 }
1079 ver = iosapic_version(addr);
1080 if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1081 iounmap(addr);
1082 spin_unlock_irqrestore(&iosapic_lock, flags);
1083 return err;
1084 }
1085
1086
1087
1088
1089
1090
1091 num_rte = ((ver >> 16) & 0xff) + 1;
1092
1093 index = iosapic_alloc();
1094 iosapic_lists[index].addr = addr;
1095 iosapic_lists[index].gsi_base = gsi_base;
1096 iosapic_lists[index].num_rte = num_rte;
1097#ifdef CONFIG_NUMA
1098 iosapic_lists[index].node = MAX_NUMNODES;
1099#endif
1100 spin_lock_init(&iosapic_lists[index].lock);
1101 spin_unlock_irqrestore(&iosapic_lock, flags);
1102
1103 if ((gsi_base == 0) && pcat_compat) {
1104
1105
1106
1107
1108
1109 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1110 iosapic_override_isa_irq(isa_irq, isa_irq,
1111 IOSAPIC_POL_HIGH,
1112 IOSAPIC_EDGE);
1113 }
1114 return 0;
1115}
1116
1117#ifdef CONFIG_HOTPLUG
1118int
1119iosapic_remove (unsigned int gsi_base)
1120{
1121 int index, err = 0;
1122 unsigned long flags;
1123
1124 spin_lock_irqsave(&iosapic_lock, flags);
1125 index = find_iosapic(gsi_base);
1126 if (index < 0) {
1127 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1128 __func__, gsi_base);
1129 goto out;
1130 }
1131
1132 if (iosapic_lists[index].rtes_inuse) {
1133 err = -EBUSY;
1134 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1135 __func__, gsi_base);
1136 goto out;
1137 }
1138
1139 iounmap(iosapic_lists[index].addr);
1140 iosapic_free(index);
1141 out:
1142 spin_unlock_irqrestore(&iosapic_lock, flags);
1143 return err;
1144}
1145#endif
1146
1147#ifdef CONFIG_NUMA
1148void __devinit
1149map_iosapic_to_node(unsigned int gsi_base, int node)
1150{
1151 int index;
1152
1153 index = find_iosapic(gsi_base);
1154 if (index < 0) {
1155 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1156 __func__, gsi_base);
1157 return;
1158 }
1159 iosapic_lists[index].node = node;
1160 return;
1161}
1162#endif
1163
1164static int __init iosapic_enable_kmalloc (void)
1165{
1166 iosapic_kmalloc_ok = 1;
1167 return 0;
1168}
1169core_initcall (iosapic_enable_kmalloc);
1170