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11#include <linux/signal.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/string.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18#include <linux/mman.h>
19#include <linux/mm.h>
20#include <linux/smp.h>
21#include <linux/interrupt.h>
22#include <linux/init.h>
23#include <linux/tty.h>
24#include <linux/vt_kern.h>
25#include <linux/highmem.h>
26#include <linux/module.h>
27
28#include <asm/m32r.h>
29#include <asm/system.h>
30#include <asm/uaccess.h>
31#include <asm/hardirq.h>
32#include <asm/mmu_context.h>
33#include <asm/tlbflush.h>
34
35extern void die(const char *, struct pt_regs *, long);
36
37#ifndef CONFIG_SMP
38asmlinkage unsigned int tlb_entry_i_dat;
39asmlinkage unsigned int tlb_entry_d_dat;
40#define tlb_entry_i tlb_entry_i_dat
41#define tlb_entry_d tlb_entry_d_dat
42#else
43unsigned int tlb_entry_i_dat[NR_CPUS];
44unsigned int tlb_entry_d_dat[NR_CPUS];
45#define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
46#define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
47#endif
48
49extern void init_tlb(void);
50
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69
70#define ACE_PROTECTION 1
71#define ACE_WRITE 2
72#define ACE_USERMODE 4
73#define ACE_INSTRUCTION 8
74
75asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
76 unsigned long address)
77{
78 struct task_struct *tsk;
79 struct mm_struct *mm;
80 struct vm_area_struct * vma;
81 unsigned long page, addr;
82 int write;
83 int fault;
84 siginfo_t info;
85
86
87
88
89 if (regs->psw & M32R_PSW_BIE)
90 local_irq_enable();
91
92 tsk = current;
93
94 info.si_code = SEGV_MAPERR;
95
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107
108
109 if (address >= TASK_SIZE && !(error_code & ACE_USERMODE))
110 goto vmalloc_fault;
111
112 mm = tsk->mm;
113
114
115
116
117
118 if (in_atomic() || !mm)
119 goto bad_area_nosemaphore;
120
121
122
123
124
125
126
127
128
129
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131
132
133
134
135
136 if (!down_read_trylock(&mm->mmap_sem)) {
137 if ((error_code & ACE_USERMODE) == 0 &&
138 !search_exception_tables(regs->psw))
139 goto bad_area_nosemaphore;
140 down_read(&mm->mmap_sem);
141 }
142
143 vma = find_vma(mm, address);
144 if (!vma)
145 goto bad_area;
146 if (vma->vm_start <= address)
147 goto good_area;
148 if (!(vma->vm_flags & VM_GROWSDOWN))
149 goto bad_area;
150
151 if (error_code & ACE_USERMODE) {
152
153
154
155
156
157
158 if (address + 4 < regs->spu)
159 goto bad_area;
160 }
161
162 if (expand_stack(vma, address))
163 goto bad_area;
164
165
166
167
168good_area:
169 info.si_code = SEGV_ACCERR;
170 write = 0;
171 switch (error_code & (ACE_WRITE|ACE_PROTECTION)) {
172 default:
173
174 case ACE_WRITE:
175 if (!(vma->vm_flags & VM_WRITE))
176 goto bad_area;
177 write++;
178 break;
179 case ACE_PROTECTION:
180 case 0:
181 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
182 goto bad_area;
183 }
184
185
186
187
188 if ((error_code & ACE_INSTRUCTION) && !(vma->vm_flags & VM_EXEC))
189 goto bad_area;
190
191survive:
192
193
194
195
196
197 addr = (address & PAGE_MASK);
198 set_thread_fault_code(error_code);
199 fault = handle_mm_fault(mm, vma, addr, write ? FAULT_FLAG_WRITE : 0);
200 if (unlikely(fault & VM_FAULT_ERROR)) {
201 if (fault & VM_FAULT_OOM)
202 goto out_of_memory;
203 else if (fault & VM_FAULT_SIGBUS)
204 goto do_sigbus;
205 BUG();
206 }
207 if (fault & VM_FAULT_MAJOR)
208 tsk->maj_flt++;
209 else
210 tsk->min_flt++;
211 set_thread_fault_code(0);
212 up_read(&mm->mmap_sem);
213 return;
214
215
216
217
218
219bad_area:
220 up_read(&mm->mmap_sem);
221
222bad_area_nosemaphore:
223
224 if (error_code & ACE_USERMODE) {
225 tsk->thread.address = address;
226 tsk->thread.error_code = error_code | (address >= TASK_SIZE);
227 tsk->thread.trap_no = 14;
228 info.si_signo = SIGSEGV;
229 info.si_errno = 0;
230
231 info.si_addr = (void __user *)address;
232 force_sig_info(SIGSEGV, &info, tsk);
233 return;
234 }
235
236no_context:
237
238 if (fixup_exception(regs))
239 return;
240
241
242
243
244
245
246 bust_spinlocks(1);
247
248 if (address < PAGE_SIZE)
249 printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
250 else
251 printk(KERN_ALERT "Unable to handle kernel paging request");
252 printk(" at virtual address %08lx\n",address);
253 printk(KERN_ALERT " printing bpc:\n");
254 printk("%08lx\n", regs->bpc);
255 page = *(unsigned long *)MPTB;
256 page = ((unsigned long *) page)[address >> PGDIR_SHIFT];
257 printk(KERN_ALERT "*pde = %08lx\n", page);
258 if (page & _PAGE_PRESENT) {
259 page &= PAGE_MASK;
260 address &= 0x003ff000;
261 page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
262 printk(KERN_ALERT "*pte = %08lx\n", page);
263 }
264 die("Oops", regs, error_code);
265 bust_spinlocks(0);
266 do_exit(SIGKILL);
267
268
269
270
271
272out_of_memory:
273 up_read(&mm->mmap_sem);
274 if (is_global_init(tsk)) {
275 yield();
276 down_read(&mm->mmap_sem);
277 goto survive;
278 }
279 printk("VM: killing process %s\n", tsk->comm);
280 if (error_code & ACE_USERMODE)
281 do_group_exit(SIGKILL);
282 goto no_context;
283
284do_sigbus:
285 up_read(&mm->mmap_sem);
286
287
288 if (!(error_code & ACE_USERMODE))
289 goto no_context;
290
291 tsk->thread.address = address;
292 tsk->thread.error_code = error_code;
293 tsk->thread.trap_no = 14;
294 info.si_signo = SIGBUS;
295 info.si_errno = 0;
296 info.si_code = BUS_ADRERR;
297 info.si_addr = (void __user *)address;
298 force_sig_info(SIGBUS, &info, tsk);
299 return;
300
301vmalloc_fault:
302 {
303
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305
306
307
308
309
310 int offset = pgd_index(address);
311 pgd_t *pgd, *pgd_k;
312 pmd_t *pmd, *pmd_k;
313 pte_t *pte_k;
314
315 pgd = (pgd_t *)*(unsigned long *)MPTB;
316 pgd = offset + (pgd_t *)pgd;
317 pgd_k = init_mm.pgd + offset;
318
319 if (!pgd_present(*pgd_k))
320 goto no_context;
321
322
323
324
325
326
327 pmd = pmd_offset(pgd, address);
328 pmd_k = pmd_offset(pgd_k, address);
329 if (!pmd_present(*pmd_k))
330 goto no_context;
331 set_pmd(pmd, *pmd_k);
332
333 pte_k = pte_offset_kernel(pmd_k, address);
334 if (!pte_present(*pte_k))
335 goto no_context;
336
337 addr = (address & PAGE_MASK);
338 set_thread_fault_code(error_code);
339 update_mmu_cache(NULL, addr, *pte_k);
340 set_thread_fault_code(0);
341 return;
342 }
343}
344
345
346
347
348#define TLB_MASK (NR_TLB_ENTRIES - 1)
349#define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
350#define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
351void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
352 pte_t pte)
353{
354 volatile unsigned long *entry1, *entry2;
355 unsigned long pte_data, flags;
356 unsigned int *entry_dat;
357 int inst = get_thread_fault_code() & ACE_INSTRUCTION;
358 int i;
359
360
361 if (vma && current->active_mm != vma->vm_mm)
362 return;
363
364 local_irq_save(flags);
365
366 vaddr = (vaddr & PAGE_MASK) | get_asid();
367
368 pte_data = pte_val(pte);
369
370#ifdef CONFIG_CHIP_OPSP
371 entry1 = (unsigned long *)ITLB_BASE;
372 for (i = 0; i < NR_TLB_ENTRIES; i++) {
373 if (*entry1++ == vaddr) {
374 set_tlb_data(entry1, pte_data);
375 break;
376 }
377 entry1++;
378 }
379 entry2 = (unsigned long *)DTLB_BASE;
380 for (i = 0; i < NR_TLB_ENTRIES; i++) {
381 if (*entry2++ == vaddr) {
382 set_tlb_data(entry2, pte_data);
383 break;
384 }
385 entry2++;
386 }
387#else
388
389
390
391
392
393 __asm__ __volatile__ (
394 "seth %0, #high(%4) \n\t"
395 "st %2, @(%5, %0) \n\t"
396 "ldi %1, #1 \n\t"
397 "st %1, @(%6, %0) \n\t"
398 "add3 r4, %0, %7 \n\t"
399 ".fillinsn \n"
400 "1: \n\t"
401 "ld %1, @(%6, %0) \n\t"
402 "bnez %1, 1b \n\t"
403 "ld %0, @r4+ \n\t"
404 "ld %1, @r4 \n\t"
405 "st %3, @+%0 \n\t"
406 "st %3, @+%1 \n\t"
407 : "=&r" (entry1), "=&r" (entry2)
408 : "r" (vaddr), "r" (pte_data), "i" (MMU_REG_BASE),
409 "i" (MSVA_offset), "i" (MTOP_offset), "i" (MIDXI_offset)
410 : "r4", "memory"
411 );
412#endif
413
414 if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END))
415 goto notfound;
416
417found:
418 local_irq_restore(flags);
419
420 return;
421
422
423notfound:
424
425
426
427
428
429 if (!inst) {
430 entry2 = (unsigned long *)DTLB_BASE;
431 entry_dat = &tlb_entry_d;
432 } else {
433 entry2 = (unsigned long *)ITLB_BASE;
434 entry_dat = &tlb_entry_i;
435 }
436 entry1 = entry2 + (((*entry_dat - 1) & TLB_MASK) << 1);
437
438 for (i = 0 ; i < NR_TLB_ENTRIES ; i++) {
439 if (!(entry1[1] & 2))
440 break;
441
442 if (entry1 != entry2)
443 entry1 -= 2;
444 else
445 entry1 += TLB_MASK << 1;
446 }
447
448 if (i >= NR_TLB_ENTRIES) {
449 entry1 = entry2 + (*entry_dat << 1);
450 *entry_dat = (*entry_dat + 1) & TLB_MASK;
451 }
452 *entry1++ = vaddr;
453 set_tlb_data(entry1, pte_data);
454
455 goto found;
456}
457
458
459
460
461void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
462{
463 if (vma->vm_mm && mm_context(vma->vm_mm) != NO_CONTEXT) {
464 unsigned long flags;
465
466 local_irq_save(flags);
467 page &= PAGE_MASK;
468 page |= (mm_context(vma->vm_mm) & MMU_CONTEXT_ASID_MASK);
469 __flush_tlb_page(page);
470 local_irq_restore(flags);
471 }
472}
473
474
475
476
477void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
478 unsigned long end)
479{
480 struct mm_struct *mm;
481
482 mm = vma->vm_mm;
483 if (mm_context(mm) != NO_CONTEXT) {
484 unsigned long flags;
485 int size;
486
487 local_irq_save(flags);
488 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
489 if (size > (NR_TLB_ENTRIES / 4)) {
490 mm_context(mm) = NO_CONTEXT;
491 if (mm == current->mm)
492 activate_context(mm);
493 } else {
494 unsigned long asid;
495
496 asid = mm_context(mm) & MMU_CONTEXT_ASID_MASK;
497 start &= PAGE_MASK;
498 end += (PAGE_SIZE - 1);
499 end &= PAGE_MASK;
500
501 start |= asid;
502 end |= asid;
503 while (start < end) {
504 __flush_tlb_page(start);
505 start += PAGE_SIZE;
506 }
507 }
508 local_irq_restore(flags);
509 }
510}
511
512
513
514
515void local_flush_tlb_mm(struct mm_struct *mm)
516{
517
518
519 if (mm_context(mm) != NO_CONTEXT) {
520 unsigned long flags;
521
522 local_irq_save(flags);
523 mm_context(mm) = NO_CONTEXT;
524 if (mm == current->mm)
525 activate_context(mm);
526 local_irq_restore(flags);
527 }
528}
529
530
531
532
533void local_flush_tlb_all(void)
534{
535 unsigned long flags;
536
537 local_irq_save(flags);
538 __flush_tlb_all();
539 local_irq_restore(flags);
540}
541
542
543
544
545void __init init_mmu(void)
546{
547 tlb_entry_i = 0;
548 tlb_entry_d = 0;
549 mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
550 set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
551 *(volatile unsigned long *)MPTB = (unsigned long)swapper_pg_dir;
552}
553