LXR linux/arch/m68k/include/asm/apollodma.h

   1/*
   2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3 * Written by Hennus Bergman, 1992.
   4 * High DMA channel support & info by Hannu Savolainen
   5 * and John Boyd, Nov. 1992.
   6 */
   7
   8#ifndef _ASM_APOLLO_DMA_H
   9#define _ASM_APOLLO_DMA_H
  10
  11#include <asm/apollohw.h>               /* need byte IO */
  12#include <linux/spinlock.h>             /* And spinlocks */
  13#include <linux/delay.h>
  14
  15
  16#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
  17#define dma_inb(addr)      (*((volatile unsigned char *)(addr+IO_BASE)))
  18
  19/*
  20 * NOTES about DMA transfers:
  21 *
  22 *  controller 1: channels 0-3, byte operations, ports 00-1F
  23 *  controller 2: channels 4-7, word operations, ports C0-DF
  24 *
  25 *  - ALL registers are 8 bits only, regardless of transfer size
  26 *  - channel 4 is not used - cascades 1 into 2.
  27 *  - channels 0-3 are byte - addresses/counts are for physical bytes
  28 *  - channels 5-7 are word - addresses/counts are for physical words
  29 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  30 *  - transfer count loaded to registers is 1 less than actual count
  31 *  - controller 2 offsets are all even (2x offsets for controller 1)
  32 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  33 *  - page registers for 0-3 use bit 0, represent 64K pages
  34 *
  35 * DMA transfers are limited to the lower 16MB of _physical_ memory.
  36 * Note that addresses loaded into registers must be _physical_ addresses,
  37 * not logical addresses (which may differ if paging is active).
  38 *
  39 *  Address mapping for channels 0-3:
  40 *
  41 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  42 *    |  ...  |   |  ... |   |  ... |
  43 *    |  ...  |   |  ... |   |  ... |
  44 *    |  ...  |   |  ... |   |  ... |
  45 *   P7  ...  P0  A7 ... A0  A7 ... A0
  46 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  47 *
  48 *  Address mapping for channels 5-7:
  49 *
  50 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  51 *    |  ...  |   \   \   ... \  \  \  ... \  \
  52 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  53 *    |  ...  |     \   \   ... \  \  \  ... \
  54 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  55 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  56 *
  57 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  58 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  59 * the hardware level, so odd-byte transfers aren't possible).
  60 *
  61 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  62 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  63 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  64 *
  65 */
  66
  67#define MAX_DMA_CHANNELS        8
  68
  69/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS      (PAGE_OFFSET+0x1000000)
  70
  71/* 8237 DMA controllers */
  72#define IO_DMA1_BASE    0x10C00 /* 8 bit slave DMA, channels 0..3 */
  73#define IO_DMA2_BASE    0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
  74
  75/* DMA controller registers */
  76#define DMA1_CMD_REG            (IO_DMA1_BASE+0x08) /* command register (w) */
  77#define DMA1_STAT_REG           (IO_DMA1_BASE+0x08) /* status register (r) */
  78#define DMA1_REQ_REG            (IO_DMA1_BASE+0x09) /* request register (w) */
  79#define DMA1_MASK_REG           (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
  80#define DMA1_MODE_REG           (IO_DMA1_BASE+0x0B) /* mode register (w) */
  81#define DMA1_CLEAR_FF_REG       (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
  82#define DMA1_TEMP_REG           (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
  83#define DMA1_RESET_REG          (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
  84#define DMA1_CLR_MASK_REG       (IO_DMA1_BASE+0x0E) /* Clear Mask */
  85#define DMA1_MASK_ALL_REG       (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
  86
  87#define DMA2_CMD_REG            (IO_DMA2_BASE+0x10) /* command register (w) */
  88#define DMA2_STAT_REG           (IO_DMA2_BASE+0x10) /* status register (r) */
  89#define DMA2_REQ_REG            (IO_DMA2_BASE+0x12) /* request register (w) */
  90#define DMA2_MASK_REG           (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
  91#define DMA2_MODE_REG           (IO_DMA2_BASE+0x16) /* mode register (w) */
  92#define DMA2_CLEAR_FF_REG       (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
  93#define DMA2_TEMP_REG           (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
  94#define DMA2_RESET_REG          (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
  95#define DMA2_CLR_MASK_REG       (IO_DMA2_BASE+0x1C) /* Clear Mask */
  96#define DMA2_MASK_ALL_REG       (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
  97
  98#define DMA_ADDR_0              (IO_DMA1_BASE+0x00) /* DMA address registers */
  99#define DMA_ADDR_1              (IO_DMA1_BASE+0x02)
 100#define DMA_ADDR_2              (IO_DMA1_BASE+0x04)
 101#define DMA_ADDR_3              (IO_DMA1_BASE+0x06)
 102#define DMA_ADDR_4              (IO_DMA2_BASE+0x00)
 103#define DMA_ADDR_5              (IO_DMA2_BASE+0x04)
 104#define DMA_ADDR_6              (IO_DMA2_BASE+0x08)
 105#define DMA_ADDR_7              (IO_DMA2_BASE+0x0C)
 106
 107#define DMA_CNT_0               (IO_DMA1_BASE+0x01)   /* DMA count registers */
 108#define DMA_CNT_1               (IO_DMA1_BASE+0x03)
 109#define DMA_CNT_2               (IO_DMA1_BASE+0x05)
 110#define DMA_CNT_3               (IO_DMA1_BASE+0x07)
 111#define DMA_CNT_4               (IO_DMA2_BASE+0x02)
 112#define DMA_CNT_5               (IO_DMA2_BASE+0x06)
 113#define DMA_CNT_6               (IO_DMA2_BASE+0x0A)
 114#define DMA_CNT_7               (IO_DMA2_BASE+0x0E)
 115
 116#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 117#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 118#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 119
 120#define DMA_AUTOINIT    0x10
 121
 122#define DMA_8BIT 0
 123#define DMA_16BIT 1
 124#define DMA_BUSMASTER 2
 125
 126extern spinlock_t  dma_spin_lock;
 127
 128static __inline__ unsigned long claim_dma_lock(void)
 129{
 130        unsigned long flags;
 131        spin_lock_irqsave(&dma_spin_lock, flags);
 132        return flags;
 133}
 134
 135static __inline__ void release_dma_lock(unsigned long flags)
 136{
 137        spin_unlock_irqrestore(&dma_spin_lock, flags);
 138}
 139
 140/* enable/disable a specific DMA channel */
 141static __inline__ void enable_dma(unsigned int dmanr)
 142{
 143        if (dmanr<=3)
 144                dma_outb(dmanr,  DMA1_MASK_REG);
 145        else
 146                dma_outb(dmanr & 3,  DMA2_MASK_REG);
 147}
 148
 149static __inline__ void disable_dma(unsigned int dmanr)
 150{
 151        if (dmanr<=3)
 152                dma_outb(dmanr | 4,  DMA1_MASK_REG);
 153        else
 154                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 155}
 156
 157/* Clear the 'DMA Pointer Flip Flop'.
 158 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 159 * Use this once to initialize the FF to a known state.
 160 * After that, keep track of it. :-)
 161 * --- In order to do that, the DMA routines below should ---
 162 * --- only be used while holding the DMA lock ! ---
 163 */
 164static __inline__ void clear_dma_ff(unsigned int dmanr)
 165{
 166        if (dmanr<=3)
 167                dma_outb(0,  DMA1_CLEAR_FF_REG);
 168        else
 169                dma_outb(0,  DMA2_CLEAR_FF_REG);
 170}
 171
 172/* set mode (above) for a specific DMA channel */
 173static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 174{
 175        if (dmanr<=3)
 176                dma_outb(mode | dmanr,  DMA1_MODE_REG);
 177        else
 178                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 179}
 180
 181/* Set transfer address & page bits for specific DMA channel.
 182 * Assumes dma flipflop is clear.
 183 */
 184static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 185{
 186        if (dmanr <= 3)  {
 187            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 188            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 189        }  else  {
 190            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 191            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 192        }
 193}
 194
 195
 196/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 197 * a specific DMA channel.
 198 * You must ensure the parameters are valid.
 199 * NOTE: from a manual: "the number of transfers is one more
 200 * than the initial word count"! This is taken into account.
 201 * Assumes dma flip-flop is clear.
 202 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 203 */
 204static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 205{
 206        count--;
 207        if (dmanr <= 3)  {
 208            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 209            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 210        } else {
 211            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 212            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 213        }
 214}
 215
 216
 217/* Get DMA residue count. After a DMA transfer, this
 218 * should return zero. Reading this while a DMA transfer is
 219 * still in progress will return unpredictable results.
 220 * If called before the channel has been used, it may return 1.
 221 * Otherwise, it returns the number of _bytes_ left to transfer.
 222 *
 223 * Assumes DMA flip-flop is clear.
 224 */
 225static __inline__ int get_dma_residue(unsigned int dmanr)
 226{
 227        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 228                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 229
 230        /* using short to get 16-bit wrap around */
 231        unsigned short count;
 232
 233        count = 1 + dma_inb(io_port);
 234        count += dma_inb(io_port) << 8;
 235
 236        return (dmanr<=3)? count : (count<<1);
 237}
 238
 239
 240/* These are in kernel/dma.c: */
 241extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 242extern void free_dma(unsigned int dmanr);       /* release it again */
 243
 244/* These are in arch/m68k/apollo/dma.c: */
 245extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
 246extern void dma_unmap_page(unsigned short dma_addr);
 247
 248#endif /* _ASM_APOLLO_DMA_H */
 249