1/* 2** linux/atarihw.h -- This header defines some macros and pointers for 3** the various Atari custom hardware registers. 4** 5** Copyright 1994 by Björn Brauel 6** 7** 5/1/94 Roman Hodek: 8** Added definitions for TT specific chips. 9** 10** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>: 11** Finally added definitions for the matrix/codec and the DSP56001 host 12** interface. 13** 14** This file is subject to the terms and conditions of the GNU General Public 15** License. See the file COPYING in the main directory of this archive 16** for more details. 17** 18*/ 19 20#ifndef _LINUX_ATARIHW_H_ 21#define _LINUX_ATARIHW_H_ 22 23#include <linux/types.h> 24#include <asm/bootinfo.h> 25#include <asm/raw_io.h> 26 27extern u_long atari_mch_cookie; 28extern u_long atari_mch_type; 29extern u_long atari_switches; 30extern int atari_rtc_year_offset; 31extern int atari_dont_touch_floppy_select; 32 33/* convenience macros for testing machine type */ 34#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) 35#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 36 (atari_mch_cookie & 0xffff) == 0) 37#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 38 (atari_mch_cookie & 0xffff) == 0x10) 39#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) 40#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) 41#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) 42#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) 43 44/* values for atari_switches */ 45#define ATARI_SWITCH_IKBD 0x01 46#define ATARI_SWITCH_MIDI 0x02 47#define ATARI_SWITCH_SND6 0x04 48#define ATARI_SWITCH_SND7 0x08 49#define ATARI_SWITCH_OVSC_SHIFT 16 50#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) 51#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) 52#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) 53#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) 54#define ATARI_SWITCH_OVSC_MASK 0xffff0000 55 56/* 57 * Define several Hardware-Chips for indication so that for the ATARI we do 58 * no longer decide whether it is a Falcon or other machine . It's just 59 * important what hardware the machine uses 60 */ 61 62/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ 63 64#define ATARIHW_DECLARE(name) unsigned name : 1 65#define ATARIHW_SET(name) (atari_hw_present.name = 1) 66#define ATARIHW_PRESENT(name) (atari_hw_present.name) 67 68struct atari_hw_present { 69 /* video hardware */ 70 ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ 71 ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ 72 ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ 73 ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ 74 /* sound hardware */ 75 ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ 76 ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ 77 ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ 78 /* disk storage interfaces */ 79 ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ 80 ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ 81 ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ 82 ATARIHW_DECLARE(IDE); /* IDE Interface */ 83 ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ 84 /* other I/O hardware */ 85 ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari 86 without it... but who knows?) */ 87 ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ 88 ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ 89 ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ 90 ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe 91 and Falcon */ 92 ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ 93 /* DMA */ 94 ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ 95 ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ 96 ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ 97 ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ 98 /* real time clocks */ 99 ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ 100 ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ 101 /* supporting hardware */ 102 ATARIHW_DECLARE(SCU); /* System Control Unit */ 103 ATARIHW_DECLARE(BLITTER); /* Blitter */ 104 ATARIHW_DECLARE(VME); /* VME Bus */ 105 ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ 106}; 107 108extern struct atari_hw_present atari_hw_present; 109 110 111/* Reading the MFP port register gives a machine independent delay, since the 112 * MFP always has a 8 MHz clock. This avoids problems with the varying length 113 * of nops on various machines. Somebody claimed that the tstb takes 600 ns. 114 */ 115#define MFPDELAY() \ 116 __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" ); 117 118/* Do cache push/invalidate for DMA read/write. This function obeys the 119 * snooping on some machines (Medusa) and processors: The Medusa itself can 120 * snoop, but only the '040 can source data from its cache to DMA writes i.e., 121 * reads from memory). Both '040 and '060 invalidate cache entries on snooped 122 * DMA reads (i.e., writes to memory). 123 */ 124 125 126#define atari_readb raw_inb 127#define atari_writeb raw_outb 128 129#define atari_inb_p raw_inb 130#define atari_outb_p raw_outb 131 132 133 134#include <linux/mm.h> 135#include <asm/cacheflush.h> 136 137static inline void dma_cache_maintenance( unsigned long paddr, 138 unsigned long len, 139 int writeflag ) 140 141{ 142 if (writeflag) { 143 if (!MACH_IS_MEDUSA || CPU_IS_060) 144 cache_push( paddr, len ); 145 } 146 else { 147 if (!MACH_IS_MEDUSA) 148 cache_clear( paddr, len ); 149 } 150} 151 152 153/* 154** Shifter 155 */ 156#define ST_LOW 0 157#define ST_MID 1 158#define ST_HIGH 2 159#define TT_LOW 7 160#define TT_MID 4 161#define TT_HIGH 6 162 163#define SHF_BAS (0xffff8200) 164struct SHIFTER 165 { 166 u_char pad1; 167 u_char bas_hi; 168 u_char pad2; 169 u_char bas_md; 170 u_char pad3; 171 u_char volatile vcounthi; 172 u_char pad4; 173 u_char volatile vcountmid; 174 u_char pad5; 175 u_char volatile vcountlow; 176 u_char volatile syncmode; 177 u_char pad6; 178 u_char pad7; 179 u_char bas_lo; 180 }; 181# define shifter ((*(volatile struct SHIFTER *)SHF_BAS)) 182 183#define SHF_FBAS (0xffff820e) 184struct SHIFTER_F030 185 { 186 u_short off_next; 187 u_short scn_width; 188 }; 189# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) 190 191 192#define SHF_TBAS (0xffff8200) 193struct SHIFTER_TT { 194 u_char char_dummy0; 195 u_char bas_hi; /* video mem base addr, high and mid byte */ 196 u_char char_dummy1; 197 u_char bas_md; 198 u_char char_dummy2; 199 u_char vcount_hi; /* pointer to currently displayed byte */ 200 u_char char_dummy3; 201 u_char vcount_md; 202 u_char char_dummy4; 203 u_char vcount_lo; 204 u_short st_sync; /* ST compatible sync mode register, unused */ 205 u_char char_dummy5; 206 u_char bas_lo; /* video mem addr, low byte */ 207 u_char char_dummy6[2+3*16]; 208 /* $ffff8240: */ 209 u_short color_reg[16]; /* 16 color registers */ 210 u_char st_shiftmode; /* ST compatible shift mode register, unused */ 211 u_char char_dummy7; 212 u_short tt_shiftmode; /* TT shift mode register */ 213 214 215}; 216#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) 217 218/* values for shifter_tt->tt_shiftmode */ 219#define TT_SHIFTER_STLOW 0x0000 220#define TT_SHIFTER_STMID 0x0100 221#define TT_SHIFTER_STHIGH 0x0200 222#define TT_SHIFTER_TTLOW 0x0700 223#define TT_SHIFTER_TTMID 0x0400 224#define TT_SHIFTER_TTHIGH 0x0600 225#define TT_SHIFTER_MODEMASK 0x0700 226#define TT_SHIFTER_NUMMODE 0x0008 227#define TT_SHIFTER_PALETTE_MASK 0x000f 228#define TT_SHIFTER_GRAYMODE 0x1000 229 230/* 256 TT palette registers */ 231#define TT_PALETTE_BASE (0xffff8400) 232#define tt_palette ((volatile u_short *)TT_PALETTE_BASE) 233 234#define TT_PALETTE_RED_MASK 0x0f00 235#define TT_PALETTE_GREEN_MASK 0x00f0 236#define TT_PALETTE_BLUE_MASK 0x000f 237 238/* 239** Falcon030 VIDEL Video Controller 240** for description see File 'linux\tools\atari\hardware.txt 241 */ 242#define f030_col ((u_long *) 0xffff9800) 243#define f030_xreg ((u_short*) 0xffff8282) 244#define f030_yreg ((u_short*) 0xffff82a2) 245#define f030_creg ((u_short*) 0xffff82c0) 246#define f030_sreg ((u_short*) 0xffff8260) 247#define f030_mreg ((u_short*) 0xffff820a) 248#define f030_linewidth ((u_short*) 0xffff820e) 249#define f030_hscroll ((u_char*) 0xffff8265) 250 251#define VIDEL_BAS (0xffff8260) 252struct VIDEL { 253 u_short st_shift; 254 u_short pad1; 255 u_char xoffset_s; 256 u_char xoffset; 257 u_short f_shift; 258 u_char pad2[0x1a]; 259 u_short hht; 260 u_short hbb; 261 u_short hbe; 262 u_short hdb; 263 u_short hde; 264 u_short hss; 265 u_char pad3[0x14]; 266 u_short vft; 267 u_short vbb; 268 u_short vbe; 269 u_short vdb; 270 u_short vde; 271 u_short vss; 272 u_char pad4[0x12]; 273 u_short control; 274 u_short mode; 275}; 276#define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) 277 278/* 279** DMA/WD1772 Disk Controller 280 */ 281 282#define FWD_BAS (0xffff8604) 283struct DMA_WD 284 { 285 u_short fdc_acces_seccount; 286 u_short dma_mode_status; 287 u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ 288 u_char dma_hi; 289 u_char char_dummy2; 290 u_char dma_md; 291 u_char char_dummy3; 292 u_char dma_lo; 293 u_short fdc_speed; 294 }; 295# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) 296/* alias */ 297#define st_dma dma_wd 298/* The two highest bytes of an extended DMA as a short; this is a must 299 * for the Medusa. 300 */ 301#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) 302 303/* 304** YM2149 Sound Chip 305** access in bytes 306 */ 307 308#define YM_BAS (0xffff8800) 309struct SOUND_YM 310 { 311 u_char rd_data_reg_sel; 312 u_char char_dummy1; 313 u_char wd_data; 314 }; 315#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) 316 317/* TT SCSI DMA */ 318 319#define TT_SCSI_DMA_BAS (0xffff8700) 320struct TT_DMA { 321 u_char char_dummy0; 322 u_char dma_addr_hi; 323 u_char char_dummy1; 324 u_char dma_addr_hmd; 325 u_char char_dummy2; 326 u_char dma_addr_lmd; 327 u_char char_dummy3; 328 u_char dma_addr_lo; 329 u_char char_dummy4; 330 u_char dma_cnt_hi; 331 u_char char_dummy5; 332 u_char dma_cnt_hmd; 333 u_char char_dummy6; 334 u_char dma_cnt_lmd; 335 u_char char_dummy7; 336 u_char dma_cnt_lo; 337 u_long dma_restdata; 338 u_short dma_ctrl; 339}; 340#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) 341 342/* TT SCSI Controller 5380 */ 343 344#define TT_5380_BAS (0xffff8781) 345struct TT_5380 { 346 u_char scsi_data; 347 u_char char_dummy1; 348 u_char scsi_icr; 349 u_char char_dummy2; 350 u_char scsi_mode; 351 u_char char_dummy3; 352 u_char scsi_tcr; 353 u_char char_dummy4; 354 u_char scsi_idstat; 355 u_char char_dummy5; 356 u_char scsi_dmastat; 357 u_char char_dummy6; 358 u_char scsi_targrcv; 359 u_char char_dummy7; 360 u_char scsi_inircv; 361}; 362#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) 363#define tt_scsi_regp ((volatile char *)TT_5380_BAS) 364 365 366/* 367** Falcon DMA Sound Subsystem 368 */ 369 370#define MATRIX_BASE (0xffff8930) 371struct MATRIX 372{ 373 u_short source; 374 u_short destination; 375 u_char external_frequency_divider; 376 u_char internal_frequency_divider; 377}; 378#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) 379 380#define CODEC_BASE (0xffff8936) 381struct CODEC 382{ 383 u_char tracks; 384 u_char input_source; 385#define CODEC_SOURCE_ADC 1 386#define CODEC_SOURCE_MATRIX 2 387 u_char adc_source; 388#define ADC_SOURCE_RIGHT_PSG 1 389#define ADC_SOURCE_LEFT_PSG 2 390 u_char gain; 391#define CODEC_GAIN_RIGHT 0x0f 392#define CODEC_GAIN_LEFT 0xf0 393 u_char attenuation; 394#define CODEC_ATTENUATION_RIGHT 0x0f 395#define CODEC_ATTENUATION_LEFT 0xf0 396 u_char unused1; 397 u_char status; 398#define CODEC_OVERFLOW_RIGHT 1 399#define CODEC_OVERFLOW_LEFT 2 400 u_char unused2, unused3, unused4, unused5; 401 u_char gpio_directions; 402#define GPIO_IN 0 403#define GPIO_OUT 1 404 u_char unused6; 405 u_char gpio_data; 406}; 407#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) 408 409/* 410** Falcon Blitter 411*/ 412 413#define BLT_BAS (0xffff8a00) 414 415struct BLITTER 416 { 417 u_short halftone[16]; 418 u_short src_x_inc; 419 u_short src_y_inc; 420 u_long src_address; 421 u_short endmask1; 422 u_short endmask2; 423 u_short endmask3; 424 u_short dst_x_inc; 425 u_short dst_y_inc; 426 u_long dst_address; 427 u_short wd_per_line; 428 u_short ln_per_bb; 429 u_short hlf_op_reg; 430 u_short log_op_reg; 431 u_short lin_nm_reg; 432 u_short skew_reg; 433 }; 434# define blitter ((*(volatile struct BLITTER *)BLT_BAS)) 435 436 437/* 438** SCC Z8530 439 */ 440 441#define SCC_BAS (0xffff8c81) 442struct SCC 443 { 444 u_char cha_a_ctrl; 445 u_char char_dummy1; 446 u_char cha_a_data; 447 u_char char_dummy2; 448 u_char cha_b_ctrl; 449 u_char char_dummy3; 450 u_char cha_b_data; 451 }; 452# define scc ((*(volatile struct SCC*)SCC_BAS)) 453 454/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ 455# define st_escc ((*(volatile struct SCC*)0xfffffa31)) 456# define st_escc_dsr ((*(volatile char *)0xfffffa39)) 457 458/* TT SCC DMA Controller (same chip as SCSI DMA) */ 459 460#define TT_SCC_DMA_BAS (0xffff8c00) 461#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) 462 463/* 464** VIDEL Palette Register 465 */ 466 467#define FPL_BAS (0xffff9800) 468struct VIDEL_PALETTE 469 { 470 u_long reg[256]; 471 }; 472# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) 473 474 475/* 476** Falcon DSP Host Interface 477 */ 478 479#define DSP56K_HOST_INTERFACE_BASE (0xffffa200) 480struct DSP56K_HOST_INTERFACE { 481 u_char icr; 482#define DSP56K_ICR_RREQ 0x01 483#define DSP56K_ICR_TREQ 0x02 484#define DSP56K_ICR_HF0 0x08 485#define DSP56K_ICR_HF1 0x10 486#define DSP56K_ICR_HM0 0x20 487#define DSP56K_ICR_HM1 0x40 488#define DSP56K_ICR_INIT 0x80 489 490 u_char cvr; 491#define DSP56K_CVR_HV_MASK 0x1f 492#define DSP56K_CVR_HC 0x80 493 494 u_char isr; 495#define DSP56K_ISR_RXDF 0x01 496#define DSP56K_ISR_TXDE 0x02 497#define DSP56K_ISR_TRDY 0x04 498#define DSP56K_ISR_HF2 0x08 499#define DSP56K_ISR_HF3 0x10 500#define DSP56K_ISR_DMA 0x40 501#define DSP56K_ISR_HREQ 0x80 502 503 u_char ivr; 504 505 union { 506 u_char b[4]; 507 u_short w[2]; 508 u_long l; 509 } data; 510}; 511#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) 512 513/* 514** MFP 68901 515 */ 516 517#define MFP_BAS (0xfffffa01) 518struct MFP 519 { 520 u_char par_dt_reg; 521 u_char char_dummy1; 522 u_char active_edge; 523 u_char char_dummy2; 524 u_char data_dir; 525 u_char char_dummy3; 526 u_char int_en_a; 527 u_char char_dummy4; 528 u_char int_en_b; 529 u_char char_dummy5; 530 u_char int_pn_a; 531 u_char char_dummy6; 532 u_char int_pn_b; 533 u_char char_dummy7; 534 u_char int_sv_a; 535 u_char char_dummy8; 536 u_char int_sv_b; 537 u_char char_dummy9; 538 u_char int_mk_a; 539 u_char char_dummy10; 540 u_char int_mk_b; 541 u_char char_dummy11; 542 u_char vec_adr; 543 u_char char_dummy12; 544 u_char tim_ct_a; 545 u_char char_dummy13; 546 u_char tim_ct_b; 547 u_char char_dummy14; 548 u_char tim_ct_cd; 549 u_char char_dummy15; 550 u_char tim_dt_a; 551 u_char char_dummy16; 552 u_char tim_dt_b; 553 u_char char_dummy17; 554 u_char tim_dt_c; 555 u_char char_dummy18; 556 u_char tim_dt_d; 557 u_char char_dummy19; 558 u_char sync_char; 559 u_char char_dummy20; 560 u_char usart_ctr; 561 u_char char_dummy21; 562 u_char rcv_stat; 563 u_char char_dummy22; 564 u_char trn_stat; 565 u_char char_dummy23; 566 u_char usart_dta; 567 }; 568# define st_mfp ((*(volatile struct MFP*)MFP_BAS)) 569 570/* TT's second MFP */ 571 572#define TT_MFP_BAS (0xfffffa81) 573# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) 574 575 576/* TT System Control Unit */ 577 578#define TT_SCU_BAS (0xffff8e01) 579struct TT_SCU { 580 u_char sys_mask; 581 u_char char_dummy1; 582 u_char sys_stat; 583 u_char char_dummy2; 584 u_char softint; 585 u_char char_dummy3; 586 u_char vmeint; 587 u_char char_dummy4; 588 u_char gp_reg1; 589 u_char char_dummy5; 590 u_char gp_reg2; 591 u_char char_dummy6; 592 u_char vme_mask; 593 u_char char_dummy7; 594 u_char vme_stat; 595}; 596#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) 597 598/* TT real time clock */ 599 600#define TT_RTC_BAS (0xffff8961) 601struct TT_RTC { 602 u_char regsel; 603 u_char dummy; 604 u_char data; 605}; 606#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) 607 608 609/* 610** ACIA 6850 611 */ 612/* constants for the ACIA registers */ 613 614/* baudrate selection and reset (Baudrate = clock/factor) */ 615#define ACIA_DIV1 0 616#define ACIA_DIV16 1 617#define ACIA_DIV64 2 618#define ACIA_RESET 3 619 620/* character format */ 621#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ 622#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ 623#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ 624#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ 625#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ 626#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ 627#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ 628#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ 629 630/* transmit control */ 631#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ 632#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ 633#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ 634#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ 635 636/* receive control */ 637#define ACIA_RID (0<<7) /* RxINT disabled */ 638#define ACIA_RIE (1<<7) /* RxINT enabled */ 639 640/* status fields of the ACIA */ 641#define ACIA_RDRF 1 /* Receive Data Register Full */ 642#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ 643#define ACIA_DCD (1<<2) /* Data Carrier Detect */ 644#define ACIA_CTS (1<<3) /* Clear To Send */ 645#define ACIA_FE (1<<4) /* Framing Error */ 646#define ACIA_OVRN (1<<5) /* Receiver Overrun */ 647#define ACIA_PE (1<<6) /* Parity Error */ 648#define ACIA_IRQ (1<<7) /* Interrupt Request */ 649 650#define ACIA_BAS (0xfffffc00) 651struct ACIA 652 { 653 u_char key_ctrl; 654 u_char char_dummy1; 655 u_char key_data; 656 u_char char_dummy2; 657 u_char mid_ctrl; 658 u_char char_dummy3; 659 u_char mid_data; 660 }; 661# define acia ((*(volatile struct ACIA*)ACIA_BAS)) 662 663#define TT_DMASND_BAS (0xffff8900) 664struct TT_DMASND { 665 u_char int_ctrl; /* Falcon: Interrupt control */ 666 u_char ctrl; 667 u_char pad2; 668 u_char bas_hi; 669 u_char pad3; 670 u_char bas_mid; 671 u_char pad4; 672 u_char bas_low; 673 u_char pad5; 674 u_char addr_hi; 675 u_char pad6; 676 u_char addr_mid; 677 u_char pad7; 678 u_char addr_low; 679 u_char pad8; 680 u_char end_hi; 681 u_char pad9; 682 u_char end_mid; 683 u_char pad10; 684 u_char end_low; 685 u_char pad11[12]; 686 u_char track_select; /* Falcon */ 687 u_char mode; 688 u_char pad12[14]; 689 /* Falcon only: */ 690 u_short cbar_src; 691 u_short cbar_dst; 692 u_char ext_div; 693 u_char int_div; 694 u_char rec_track_select; 695 u_char dac_src; 696 u_char adc_src; 697 u_char input_gain; 698 u_short output_atten; 699}; 700# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) 701 702#define DMASND_MFP_INT_REPLAY 0x01 703#define DMASND_MFP_INT_RECORD 0x02 704#define DMASND_TIMERA_INT_REPLAY 0x04 705#define DMASND_TIMERA_INT_RECORD 0x08 706 707#define DMASND_CTRL_OFF 0x00 708#define DMASND_CTRL_ON 0x01 709#define DMASND_CTRL_REPEAT 0x02 710#define DMASND_CTRL_RECORD_ON 0x10 711#define DMASND_CTRL_RECORD_OFF 0x00 712#define DMASND_CTRL_RECORD_REPEAT 0x20 713#define DMASND_CTRL_SELECT_REPLAY 0x00 714#define DMASND_CTRL_SELECT_RECORD 0x80 715#define DMASND_MODE_MONO 0x80 716#define DMASND_MODE_STEREO 0x00 717#define DMASND_MODE_8BIT 0x00 718#define DMASND_MODE_16BIT 0x40 /* Falcon only */ 719#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ 720#define DMASND_MODE_12KHZ 0x01 721#define DMASND_MODE_25KHZ 0x02 722#define DMASND_MODE_50KHZ 0x03 723 724 725#define DMASNDSetBase(bufstart) \ 726 do { \ 727 tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ 728 tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ 729 tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ 730 } while( 0 ) 731 732#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ 733 (tt_dmasnd.addr_mid << 8) + \ 734 (tt_dmasnd.addr_low)) 735 736#define DMASNDSetEnd(bufend) \ 737 do { \ 738 tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ 739 tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ 740 tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ 741 } while( 0 ) 742 743 744#define TT_MICROWIRE_BAS (0xffff8922) 745struct TT_MICROWIRE { 746 u_short data; 747 u_short mask; 748}; 749# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) 750 751#define MW_LM1992_ADDR 0x0400 752 753#define MW_LM1992_VOLUME(dB) \ 754 (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) 755#define MW_LM1992_BALLEFT(dB) \ 756 (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 757#define MW_LM1992_BALRIGHT(dB) \ 758 (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 759#define MW_LM1992_TREBLE(dB) \ 760 (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 761#define MW_LM1992_BASS(dB) \ 762 (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 763 764#define MW_LM1992_PSG_LOW 0x000 765#define MW_LM1992_PSG_HIGH 0x001 766#define MW_LM1992_PSG_OFF 0x002 767 768#define MSTE_RTC_BAS (0xfffffc21) 769 770struct MSTE_RTC { 771 u_char sec_ones; 772 u_char dummy1; 773 u_char sec_tens; 774 u_char dummy2; 775 u_char min_ones; 776 u_char dummy3; 777 u_char min_tens; 778 u_char dummy4; 779 u_char hr_ones; 780 u_char dummy5; 781 u_char hr_tens; 782 u_char dummy6; 783 u_char weekday; 784 u_char dummy7; 785 u_char day_ones; 786 u_char dummy8; 787 u_char day_tens; 788 u_char dummy9; 789 u_char mon_ones; 790 u_char dummy10; 791 u_char mon_tens; 792 u_char dummy11; 793 u_char year_ones; 794 u_char dummy12; 795 u_char year_tens; 796 u_char dummy13; 797 u_char mode; 798 u_char dummy14; 799 u_char test; 800 u_char dummy15; 801 u_char reset; 802}; 803 804#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) 805 806#endif /* linux/atarihw.h */ 807 808