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11#include <linux/init.h>
12#include <linux/irq.h>
13#include <asm/page.h>
14#include <linux/io.h>
15#include <linux/bug.h>
16
17#include <asm/prom.h>
18#include <asm/irq.h>
19
20#ifdef CONFIG_SELFMOD_INTC
21#include <asm/selfmod.h>
22#define INTC_BASE BARRIER_BASE_ADDR
23#else
24static unsigned int intc_baseaddr;
25#define INTC_BASE intc_baseaddr
26#endif
27
28unsigned int nr_irq;
29
30
31#define ISR 0x00
32#define IPR 0x04
33#define IER 0x08
34#define IAR 0x0c
35#define SIE 0x10
36#define CIE 0x14
37#define IVR 0x18
38#define MER 0x1c
39
40#define MER_ME (1<<0)
41#define MER_HIE (1<<1)
42
43static void intc_enable_or_unmask(unsigned int irq)
44{
45 pr_debug("enable_or_unmask: %d\n", irq);
46 out_be32(INTC_BASE + SIE, 1 << irq);
47}
48
49static void intc_disable_or_mask(unsigned int irq)
50{
51 pr_debug("disable: %d\n", irq);
52 out_be32(INTC_BASE + CIE, 1 << irq);
53}
54
55static void intc_ack(unsigned int irq)
56{
57 pr_debug("ack: %d\n", irq);
58 out_be32(INTC_BASE + IAR, 1 << irq);
59}
60
61static void intc_mask_ack(unsigned int irq)
62{
63 unsigned long mask = 1 << irq;
64 pr_debug("disable_and_ack: %d\n", irq);
65 out_be32(INTC_BASE + CIE, mask);
66 out_be32(INTC_BASE + IAR, mask);
67}
68
69static void intc_end(unsigned int irq)
70{
71 unsigned long mask = 1 << irq;
72 pr_debug("end: %d\n", irq);
73 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
74 out_be32(INTC_BASE + SIE, mask);
75
76 if (irq_desc[irq].status & IRQ_LEVEL)
77 out_be32(INTC_BASE + IAR, mask);
78 }
79}
80
81static struct irq_chip intc_dev = {
82 .name = "Xilinx INTC",
83 .unmask = intc_enable_or_unmask,
84 .mask = intc_disable_or_mask,
85 .ack = intc_ack,
86 .mask_ack = intc_mask_ack,
87 .end = intc_end,
88};
89
90unsigned int get_irq(struct pt_regs *regs)
91{
92 int irq;
93
94
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96
97
98
99 irq = in_be32(INTC_BASE + IVR);
100 pr_debug("get_irq: %d\n", irq);
101
102 return irq;
103}
104
105void __init init_IRQ(void)
106{
107 u32 i, j, intr_type;
108 struct device_node *intc = NULL;
109#ifdef CONFIG_SELFMOD_INTC
110 unsigned int intc_baseaddr = 0;
111 static int arr_func[] = {
112 (int)&get_irq,
113 (int)&intc_enable_or_unmask,
114 (int)&intc_disable_or_mask,
115 (int)&intc_mask_ack,
116 (int)&intc_ack,
117 (int)&intc_end,
118 0
119 };
120#endif
121 static char *intc_list[] = {
122 "xlnx,xps-intc-1.00.a",
123 "xlnx,opb-intc-1.00.c",
124 "xlnx,opb-intc-1.00.b",
125 "xlnx,opb-intc-1.00.a",
126 NULL
127 };
128
129 for (j = 0; intc_list[j] != NULL; j++) {
130 intc = of_find_compatible_node(NULL, NULL, intc_list[j]);
131 if (intc)
132 break;
133 }
134 BUG_ON(!intc);
135
136 intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);
137 intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
138 nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL);
139
140 intr_type =
141 *(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL);
142 if (intr_type >= (1 << (nr_irq + 1)))
143 printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
144
145#ifdef CONFIG_SELFMOD_INTC
146 selfmod_function((int *) arr_func, intc_baseaddr);
147#endif
148 printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
149 intc_list[j], intc_baseaddr, nr_irq, intr_type);
150
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154
155 out_be32(intc_baseaddr + IER, 0);
156
157
158 out_be32(intc_baseaddr + IAR, 0xffffffff);
159
160
161 out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
162
163 for (i = 0; i < nr_irq; ++i) {
164 if (intr_type & (0x00000001 << i)) {
165 set_irq_chip_and_handler_name(i, &intc_dev,
166 handle_edge_irq, intc_dev.name);
167 irq_desc[i].status &= ~IRQ_LEVEL;
168 } else {
169 set_irq_chip_and_handler_name(i, &intc_dev,
170 handle_level_irq, intc_dev.name);
171 irq_desc[i].status |= IRQ_LEVEL;
172 }
173 }
174}
175