linux/arch/mips/alchemy/devboards/pb1100/board_setup.c
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   1/*
   2 * Copyright 2002, 2008 MontaVista Software Inc.
   3 * Author: MontaVista Software, Inc. <source@mvista.com>
   4 *
   5 *  This program is free software; you can redistribute  it and/or modify it
   6 *  under  the terms of  the GNU General  Public License as published by the
   7 *  Free Software Foundation;  either version 2 of the  License, or (at your
   8 *  option) any later version.
   9 *
  10 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20 *
  21 *  You should have received a copy of the  GNU General Public License along
  22 *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23 *  675 Mass Ave, Cambridge, MA 02139, USA.
  24 */
  25
  26#include <linux/gpio.h>
  27#include <linux/init.h>
  28#include <linux/delay.h>
  29#include <linux/interrupt.h>
  30
  31#include <asm/mach-au1x00/au1000.h>
  32#include <asm/mach-pb1x00/pb1100.h>
  33
  34#include <prom.h>
  35
  36
  37struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
  38        { AU1000_GPIO_9,  IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */
  39        { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */
  40        { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */
  41        { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */
  42};
  43
  44
  45const char *get_system_type(void)
  46{
  47        return "Alchemy Pb1100";
  48}
  49
  50void board_reset(void)
  51{
  52        /* Hit BCSR.RST_VDDI[SOFT_RESET] */
  53        au_writel(0x00000000, PB1100_RST_VDDI);
  54}
  55
  56void __init board_init_irq(void)
  57{
  58        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
  59}
  60
  61void __init board_setup(void)
  62{
  63        volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
  64        char *argptr;
  65
  66        argptr = prom_getcmdline();
  67#ifdef CONFIG_SERIAL_8250_CONSOLE
  68        argptr = strstr(argptr, "console=");
  69        if (argptr == NULL) {
  70                argptr = prom_getcmdline();
  71                strcat(argptr, " console=ttyS0,115200");
  72        }
  73#endif
  74
  75#ifdef CONFIG_FB_AU1100
  76        argptr = strstr(argptr, "video=");
  77        if (argptr == NULL) {
  78                argptr = prom_getcmdline();
  79                /* default panel */
  80                /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
  81        }
  82#endif
  83
  84#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
  85        /* au1000 does not support vra, au1500 and au1100 do */
  86        strcat(argptr, " au1000_audio=vra");
  87        argptr = prom_getcmdline();
  88#endif
  89
  90        /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  91        au_writel(8, SYS_AUXPLL);
  92        alchemy_gpio1_input_enable();
  93        udelay(100);
  94
  95#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  96        {
  97                u32 pin_func, sys_freqctrl, sys_clksrc;
  98
  99                /* Configure pins GPIO[14:9] as GPIO */
 100                pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
 101
 102                /* Zero and disable FREQ2 */
 103                sys_freqctrl = au_readl(SYS_FREQCTRL0);
 104                sys_freqctrl &= ~0xFFF00000;
 105                au_writel(sys_freqctrl, SYS_FREQCTRL0);
 106
 107                /* Zero and disable USBH/USBD/IrDA clock */
 108                sys_clksrc = au_readl(SYS_CLKSRC);
 109                sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
 110                au_writel(sys_clksrc, SYS_CLKSRC);
 111
 112                sys_freqctrl = au_readl(SYS_FREQCTRL0);
 113                sys_freqctrl &= ~0xFFF00000;
 114
 115                sys_clksrc = au_readl(SYS_CLKSRC);
 116                sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
 117
 118                /* FREQ2 = aux / 2 = 48 MHz */
 119                sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
 120                                SYS_FC_FE2 | SYS_FC_FS2;
 121                au_writel(sys_freqctrl, SYS_FREQCTRL0);
 122
 123                /*
 124                 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
 125                 */
 126                sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
 127                au_writel(sys_clksrc, SYS_CLKSRC);
 128
 129                /* Setup the static bus controller */
 130                au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
 131                au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
 132                au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
 133
 134                /*
 135                 * Get USB Functionality pin state (device vs host drive pins).
 136                 */
 137                pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
 138                /* 2nd USB port is USB host. */
 139                pin_func |= SYS_PF_USB;
 140                au_writel(pin_func, SYS_PINFUNC);
 141        }
 142#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 143
 144        /* Enable sys bus clock divider when IDLE state or no bus activity. */
 145        au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 146
 147        /* Enable the RTC if not already enabled. */
 148        if (!(readb(base + 0x28) & 0x20)) {
 149                writeb(readb(base + 0x28) | 0x20, base + 0x28);
 150                au_sync();
 151        }
 152        /* Put the clock in BCD mode. */
 153        if (readb(base + 0x2C) & 0x4) { /* reg B */
 154                writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
 155                au_sync();
 156        }
 157}
 158