1/* 2 * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory 3 * Engine) 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * Copyright (C) 2000 Harald Koerfgen 10 */ 11 12#ifndef __ASM_CRIME_H__ 13#define __ASM_CRIME_H__ 14 15/* 16 * Address map 17 */ 18#define CRIME_BASE 0x14000000 /* physical */ 19 20struct sgi_crime { 21 volatile unsigned long id; 22#define CRIME_ID_MASK 0xff 23#define CRIME_ID_IDBITS 0xf0 24#define CRIME_ID_IDVALUE 0xa0 25#define CRIME_ID_REV 0x0f 26#define CRIME_REV_PETTY 0x00 27#define CRIME_REV_11 0x11 28#define CRIME_REV_13 0x13 29#define CRIME_REV_14 0x14 30 31 volatile unsigned long control; 32#define CRIME_CONTROL_MASK 0x3fff 33#define CRIME_CONTROL_TRITON_SYSADC 0x2000 34#define CRIME_CONTROL_CRIME_SYSADC 0x1000 35#define CRIME_CONTROL_HARD_RESET 0x0800 36#define CRIME_CONTROL_SOFT_RESET 0x0400 37#define CRIME_CONTROL_DOG_ENA 0x0200 38#define CRIME_CONTROL_ENDIANESS 0x0100 39#define CRIME_CONTROL_ENDIAN_BIG 0x0100 40#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000 41#define CRIME_CONTROL_CQUEUE_HWM 0x000f 42#define CRIME_CONTROL_CQUEUE_SHFT 0 43#define CRIME_CONTROL_WBUF_HWM 0x00f0 44#define CRIME_CONTROL_WBUF_SHFT 8 45 46 volatile unsigned long istat; 47 volatile unsigned long imask; 48 volatile unsigned long soft_int; 49 volatile unsigned long hard_int; 50#define MACE_VID_IN1_INT BIT(0) 51#define MACE_VID_IN2_INT BIT(1) 52#define MACE_VID_OUT_INT BIT(2) 53#define MACE_ETHERNET_INT BIT(3) 54#define MACE_SUPERIO_INT BIT(4) 55#define MACE_MISC_INT BIT(5) 56#define MACE_AUDIO_INT BIT(6) 57#define MACE_PCI_BRIDGE_INT BIT(7) 58#define MACEPCI_SCSI0_INT BIT(8) 59#define MACEPCI_SCSI1_INT BIT(9) 60#define MACEPCI_SLOT0_INT BIT(10) 61#define MACEPCI_SLOT1_INT BIT(11) 62#define MACEPCI_SLOT2_INT BIT(12) 63#define MACEPCI_SHARED0_INT BIT(13) 64#define MACEPCI_SHARED1_INT BIT(14) 65#define MACEPCI_SHARED2_INT BIT(15) 66#define CRIME_GBE0_INT BIT(16) 67#define CRIME_GBE1_INT BIT(17) 68#define CRIME_GBE2_INT BIT(18) 69#define CRIME_GBE3_INT BIT(19) 70#define CRIME_CPUERR_INT BIT(20) 71#define CRIME_MEMERR_INT BIT(21) 72#define CRIME_RE_EMPTY_E_INT BIT(22) 73#define CRIME_RE_FULL_E_INT BIT(23) 74#define CRIME_RE_IDLE_E_INT BIT(24) 75#define CRIME_RE_EMPTY_L_INT BIT(25) 76#define CRIME_RE_FULL_L_INT BIT(26) 77#define CRIME_RE_IDLE_L_INT BIT(27) 78#define CRIME_SOFT0_INT BIT(28) 79#define CRIME_SOFT1_INT BIT(29) 80#define CRIME_SOFT2_INT BIT(30) 81#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT 82#define CRIME_VICE_INT BIT(31) 83/* Masks for deciding who handles the interrupt */ 84#define CRIME_MACE_INT_MASK 0x8f 85#define CRIME_MACEISA_INT_MASK 0x70 86#define CRIME_MACEPCI_INT_MASK 0xff00 87#define CRIME_CRIME_INT_MASK 0xffff0000 88 89 volatile unsigned long watchdog; 90#define CRIME_DOG_POWER_ON_RESET 0x00010000 91#define CRIME_DOG_WARM_RESET 0x00080000 92#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET) 93#define CRIME_DOG_VALUE 0x00007fff 94 95 volatile unsigned long timer; 96#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */ 97#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */ 98 99 volatile unsigned long cpu_error_addr; 100#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff 101 102 volatile unsigned long cpu_error_stat; 103#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */ 104#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4 105#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2 106#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1 107 108 unsigned long _pad0[54]; 109 110 volatile unsigned long mc_ctrl; 111 volatile unsigned long bank_ctrl[8]; 112#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */ 113#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f 114#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100 115#define CRIME_MAXBANKS 8 116 117 volatile unsigned long mem_ref_counter; 118#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */ 119 120 volatile unsigned long mem_error_stat; 121#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ 122#define CRIME_MEM_ERROR_MACE_ID 0x0000007f 123#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 124#define CRIME_MEM_ERROR_RE_ID 0x00007f00 125#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000 126#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000 127#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000 128#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000 129#define CRIME_MEM_ERROR_RESERVED 0x00080000 130#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000 131#define CRIME_MEM_ERROR_HARD_ERR 0x00200000 132#define CRIME_MEM_ERROR_MULTIPLE 0x00400000 133#define CRIME_MEM_ERROR_ECC 0x01800000 134#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000 135#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000 136#define CRIME_MEM_ERROR_INV 0x0e000000 137#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000 138#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 139#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 140 141 volatile unsigned long mem_error_addr; 142#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff 143 144 volatile unsigned long mem_ecc_syn; 145#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff 146 147 volatile unsigned long mem_ecc_chk; 148#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff 149 150 volatile unsigned long mem_ecc_repl; 151#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff 152}; 153 154extern struct sgi_crime __iomem *crime; 155 156#define CRIME_HI_MEM_BASE 0x40000000 /* this is where whole 1G of RAM is mapped */ 157 158#endif /* __ASM_CRIME_H__ */ 159