LXR linux/arch/mips/include/asm/mach-pb1x00/pb1200.h

   1/*
   2 * AMD Alchemy Pb1200 Referrence Board
   3 * Board Registers defines.
   4 *
   5 * ########################################################################
   6 *
   7 *  This program is free software; you can distribute it and/or modify it
   8 *  under the terms of the GNU General Public License (Version 2) as
   9 *  published by the Free Software Foundation.
  10 *
  11 *  This program is distributed in the hope it will be useful, but WITHOUT
  12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 *  for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License along
  17 *  with this program; if not, write to the Free Software Foundation, Inc.,
  18 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19 *
  20 * ########################################################################
  21 *
  22 *
  23 */
  24#ifndef __ASM_PB1200_H
  25#define __ASM_PB1200_H
  26
  27#include <linux/types.h>
  28#include <asm/mach-au1x00/au1xxx_psc.h>
  29
  30#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
  31#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
  32#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
  33#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
  34
  35/*
  36 * SPI and SMB are muxed on the Pb1200 board.
  37 * Refer to board documentation.
  38 */
  39#define SPI_PSC_BASE            PSC0_BASE_ADDR
  40#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
  41/*
  42 * AC97 and I2S are muxed on the Pb1200 board.
  43 * Refer to board documentation.
  44 */
  45#define AC97_PSC_BASE       PSC1_BASE_ADDR
  46#define I2S_PSC_BASE            PSC1_BASE_ADDR
  47
  48#define BCSR_KSEG1_ADDR 0xAD800000
  49
  50typedef volatile struct
  51{
  52        /*00*/  u16 whoami;
  53                u16 reserved0;
  54        /*04*/  u16 status;
  55                u16 reserved1;
  56        /*08*/  u16 switches;
  57                u16 reserved2;
  58        /*0C*/  u16 resets;
  59                u16 reserved3;
  60
  61        /*10*/  u16 pcmcia;
  62                u16 reserved4;
  63        /*14*/  u16 board;
  64                u16 reserved5;
  65        /*18*/  u16 disk_leds;
  66                u16 reserved6;
  67        /*1C*/  u16 system;
  68                u16 reserved7;
  69
  70        /*20*/  u16 intclr;
  71                u16 reserved8;
  72        /*24*/  u16 intset;
  73                u16 reserved9;
  74        /*28*/  u16 intclr_mask;
  75                u16 reserved10;
  76        /*2C*/  u16 intset_mask;
  77                u16 reserved11;
  78
  79        /*30*/  u16 sig_status;
  80                u16 reserved12;
  81        /*34*/  u16 int_status;
  82                u16 reserved13;
  83        /*38*/  u16 reserved14;
  84                u16 reserved15;
  85        /*3C*/  u16 reserved16;
  86                u16 reserved17;
  87
  88} BCSR;
  89
  90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
  91
  92/*
  93 * Register bit definitions for the BCSRs
  94 */
  95#define BCSR_WHOAMI_DCID        0x000F
  96#define BCSR_WHOAMI_CPLD        0x00F0
  97#define BCSR_WHOAMI_BOARD       0x0F00
  98
  99#define BCSR_STATUS_PCMCIA0VS   0x0003
 100#define BCSR_STATUS_PCMCIA1VS   0x000C
 101#define BCSR_STATUS_SWAPBOOT    0x0040
 102#define BCSR_STATUS_FLASHBUSY   0x0100
 103#define BCSR_STATUS_IDECBLID    0x0200
 104#define BCSR_STATUS_SD0WP       0x0400
 105#define BCSR_STATUS_SD1WP       0x0800
 106#define BCSR_STATUS_U0RXD       0x1000
 107#define BCSR_STATUS_U1RXD       0x2000
 108
 109#define BCSR_SWITCHES_OCTAL     0x00FF
 110#define BCSR_SWITCHES_DIP_1     0x0080
 111#define BCSR_SWITCHES_DIP_2     0x0040
 112#define BCSR_SWITCHES_DIP_3     0x0020
 113#define BCSR_SWITCHES_DIP_4     0x0010
 114#define BCSR_SWITCHES_DIP_5     0x0008
 115#define BCSR_SWITCHES_DIP_6     0x0004
 116#define BCSR_SWITCHES_DIP_7     0x0002
 117#define BCSR_SWITCHES_DIP_8     0x0001
 118#define BCSR_SWITCHES_ROTARY    0x0F00
 119
 120#define BCSR_RESETS_ETH         0x0001
 121#define BCSR_RESETS_CAMERA      0x0002
 122#define BCSR_RESETS_DC          0x0004
 123#define BCSR_RESETS_IDE         0x0008
 124/* not resets but in the same register */
 125#define BCSR_RESETS_WSCFSM      0x0800
 126#define BCSR_RESETS_PCS0MUX     0x1000
 127#define BCSR_RESETS_PCS1MUX     0x2000
 128#define BCSR_RESETS_SPISEL      0x4000
 129#define BCSR_RESETS_SD1MUX      0x8000
 130
 131#define BCSR_PCMCIA_PC0VPP      0x0003
 132#define BCSR_PCMCIA_PC0VCC      0x000C
 133#define BCSR_PCMCIA_PC0DRVEN    0x0010
 134#define BCSR_PCMCIA_PC0RST      0x0080
 135#define BCSR_PCMCIA_PC1VPP      0x0300
 136#define BCSR_PCMCIA_PC1VCC      0x0C00
 137#define BCSR_PCMCIA_PC1DRVEN    0x1000
 138#define BCSR_PCMCIA_PC1RST      0x8000
 139
 140#define BCSR_BOARD_LCDVEE       0x0001
 141#define BCSR_BOARD_LCDVDD       0x0002
 142#define BCSR_BOARD_LCDBL        0x0004
 143#define BCSR_BOARD_CAMSNAP      0x0010
 144#define BCSR_BOARD_CAMPWR       0x0020
 145#define BCSR_BOARD_SD0PWR       0x0040
 146#define BCSR_BOARD_SD1PWR       0x0080
 147
 148#define BCSR_LEDS_DECIMALS      0x00FF
 149#define BCSR_LEDS_LED0          0x0100
 150#define BCSR_LEDS_LED1          0x0200
 151#define BCSR_LEDS_LED2          0x0400
 152#define BCSR_LEDS_LED3          0x0800
 153
 154#define BCSR_SYSTEM_VDDI        0x001F
 155#define BCSR_SYSTEM_POWEROFF    0x4000
 156#define BCSR_SYSTEM_RESET       0x8000
 157
 158/* Bit positions for the different interrupt sources */
 159#define BCSR_INT_IDE            0x0001
 160#define BCSR_INT_ETH            0x0002
 161#define BCSR_INT_PC0            0x0004
 162#define BCSR_INT_PC0STSCHG      0x0008
 163#define BCSR_INT_PC1            0x0010
 164#define BCSR_INT_PC1STSCHG      0x0020
 165#define BCSR_INT_DC             0x0040
 166#define BCSR_INT_FLASHBUSY      0x0080
 167#define BCSR_INT_PC0INSERT      0x0100
 168#define BCSR_INT_PC0EJECT       0x0200
 169#define BCSR_INT_PC1INSERT      0x0400
 170#define BCSR_INT_PC1EJECT       0x0800
 171#define BCSR_INT_SD0INSERT      0x1000
 172#define BCSR_INT_SD0EJECT       0x2000
 173#define BCSR_INT_SD1INSERT      0x4000
 174#define BCSR_INT_SD1EJECT       0x8000
 175
 176#define SMC91C111_PHYS_ADDR     0x0D000300
 177#define SMC91C111_INT           PB1200_ETH_INT
 178
 179#define IDE_PHYS_ADDR           0x0C800000
 180#define IDE_REG_SHIFT           5
 181#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
 182#define IDE_INT                 PB1200_IDE_INT
 183#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
 184#define IDE_RQSIZE              128
 185
 186#define NAND_PHYS_ADDR  0x1C000000
 187
 188/*
 189 * Timing values as described in databook, * ns value stripped of
 190 * lower 2 bits.
 191 * These defines are here rather than an Au1200 generic file because
 192 * the parts chosen on another board may be different and may require
 193 * different timings.
 194 */
 195#define NAND_T_H                (18 >> 2)
 196#define NAND_T_PUL              (30 >> 2)
 197#define NAND_T_SU               (30 >> 2)
 198#define NAND_T_WH               (30 >> 2)
 199
 200/* Bitfield shift amounts */
 201#define NAND_T_H_SHIFT          0
 202#define NAND_T_PUL_SHIFT        4
 203#define NAND_T_SU_SHIFT         8
 204#define NAND_T_WH_SHIFT         12
 205
 206#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
 207                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
 208                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
 209                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
 210
 211/*
 212 * External Interrupts for Pb1200 as of 8/6/2004.
 213 * Bit positions in the CPLD registers can be calculated by taking
 214 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
 215 *
 216 *   Example: IDE bis pos is  = 64 - 64
 217 *            ETH bit pos is  = 65 - 64
 218 */
 219enum external_pb1200_ints {
 220        PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
 221
 222        PB1200_IDE_INT          = PB1200_INT_BEGIN,
 223        PB1200_ETH_INT,
 224        PB1200_PC0_INT,
 225        PB1200_PC0_STSCHG_INT,
 226        PB1200_PC1_INT,
 227        PB1200_PC1_STSCHG_INT,
 228        PB1200_DC_INT,
 229        PB1200_FLASHBUSY_INT,
 230        PB1200_PC0_INSERT_INT,
 231        PB1200_PC0_EJECT_INT,
 232        PB1200_PC1_INSERT_INT,
 233        PB1200_PC1_EJECT_INT,
 234        PB1200_SD0_INSERT_INT,
 235        PB1200_SD0_EJECT_INT,
 236        PB1200_SD1_INSERT_INT,
 237        PB1200_SD1_EJECT_INT,
 238
 239        PB1200_INT_END          = PB1200_INT_BEGIN + 15
 240};
 241
 242/*
 243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
 244 */
 245#define PCMCIA_MAX_SOCK  1
 246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
 247
 248/* VPP/VCC */
 249#define SET_VCC_VPP(VCC, VPP, SLOT) \
 250        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
 251
 252#define BOARD_PC0_INT   PB1200_PC0_INT
 253#define BOARD_PC1_INT   PB1200_PC1_INT
 254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
 255
 256/* NAND chip select */
 257#define NAND_CS 1
 258
 259#endif /* __ASM_PB1200_H */
 260