LXR linux/arch/mips/include/asm/mach-rc32434/gpio.h

   1/*
   2 * Copyright 2002 Integrated Device Technology, Inc.
   3 *      All rights reserved.
   4 *
   5 * GPIO register definition.
   6 *
   7 * Author : ryan.holmQVist@idt.com
   8 * Date   : 20011005
   9 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
  10 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
  11 */
  12
  13#ifndef _RC32434_GPIO_H_
  14#define _RC32434_GPIO_H_
  15
  16#include <linux/types.h>
  17#include <asm-generic/gpio.h>
  18
  19#define NR_BUILTIN_GPIO         32
  20
  21#define gpio_get_value  __gpio_get_value
  22#define gpio_set_value  __gpio_set_value
  23#define gpio_cansleep   __gpio_cansleep
  24
  25#define gpio_to_irq(gpio)       (8 + 4 * 32 + gpio)
  26#define irq_to_gpio(irq)        (irq - (8 + 4 * 32))
  27
  28struct rb532_gpio_reg {
  29        u32   gpiofunc;   /* GPIO Function Register
  30                           * gpiofunc[x]==0 bit = gpio
  31                           * func[x]==1  bit = altfunc
  32                           */
  33        u32   gpiocfg;    /* GPIO Configuration Register
  34                           * gpiocfg[x]==0 bit = input
  35                           * gpiocfg[x]==1 bit = output
  36                           */
  37        u32   gpiod;      /* GPIO Data Register
  38                           * gpiod[x] read/write gpio pinX status
  39                           */
  40        u32   gpioilevel; /* GPIO Interrupt Status Register
  41                           * interrupt level (see gpioistat)
  42                           */
  43        u32   gpioistat;  /* Gpio Interrupt Status Register
  44                           * istat[x] = (gpiod[x] == level[x])
  45                           * cleared in ISR (STICKY bits)
  46                           */
  47        u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
  48};
  49
  50/* UART GPIO signals */
  51#define RC32434_UART0_SOUT      (1 << 0)
  52#define RC32434_UART0_SIN       (1 << 1)
  53#define RC32434_UART0_RTS       (1 << 2)
  54#define RC32434_UART0_CTS       (1 << 3)
  55
  56/* M & P bus GPIO signals */
  57#define RC32434_MP_BIT_22       (1 << 4)
  58#define RC32434_MP_BIT_23       (1 << 5)
  59#define RC32434_MP_BIT_24       (1 << 6)
  60#define RC32434_MP_BIT_25       (1 << 7)
  61
  62/* CPU GPIO signals */
  63#define RC32434_CPU_GPIO        (1 << 8)
  64
  65/* Reserved GPIO signals */
  66#define RC32434_AF_SPARE_6      (1 << 9)
  67#define RC32434_AF_SPARE_4      (1 << 10)
  68#define RC32434_AF_SPARE_3      (1 << 11)
  69#define RC32434_AF_SPARE_2      (1 << 12)
  70
  71/* PCI messaging unit */
  72#define RC32434_PCI_MSU_GPIO    (1 << 13)
  73
  74/* NAND GPIO signals */
  75#define GPIO_RDY                8
  76#define GPIO_WPX        9
  77#define GPIO_ALE                10
  78#define GPIO_CLE                11
  79
  80/* Compact Flash GPIO pin */
  81#define CF_GPIO_NUM             13
  82
  83/* S1 button GPIO (shared with UART0_SIN) */
  84#define GPIO_BTN_S1             1
  85
  86extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
  87extern void rb532_gpio_set_istat(int bit, unsigned gpio);
  88extern void rb532_gpio_set_func(unsigned gpio);
  89
  90#endif /* _RC32434_GPIO_H_ */
  91