1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_MIO_DEFS_H__ 29#define __CVMX_MIO_DEFS_H__ 30 31#define CVMX_MIO_BOOT_BIST_STAT \ 32 CVMX_ADD_IO_SEG(0x00011800000000F8ull) 33#define CVMX_MIO_BOOT_COMP \ 34 CVMX_ADD_IO_SEG(0x00011800000000B8ull) 35#define CVMX_MIO_BOOT_DMA_CFGX(offset) \ 36 CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8)) 37#define CVMX_MIO_BOOT_DMA_INTX(offset) \ 38 CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8)) 39#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \ 40 CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8)) 41#define CVMX_MIO_BOOT_DMA_TIMX(offset) \ 42 CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8)) 43#define CVMX_MIO_BOOT_ERR \ 44 CVMX_ADD_IO_SEG(0x00011800000000A0ull) 45#define CVMX_MIO_BOOT_INT \ 46 CVMX_ADD_IO_SEG(0x00011800000000A8ull) 47#define CVMX_MIO_BOOT_LOC_ADR \ 48 CVMX_ADD_IO_SEG(0x0001180000000090ull) 49#define CVMX_MIO_BOOT_LOC_CFGX(offset) \ 50 CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8)) 51#define CVMX_MIO_BOOT_LOC_DAT \ 52 CVMX_ADD_IO_SEG(0x0001180000000098ull) 53#define CVMX_MIO_BOOT_PIN_DEFS \ 54 CVMX_ADD_IO_SEG(0x00011800000000C0ull) 55#define CVMX_MIO_BOOT_REG_CFGX(offset) \ 56 CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8)) 57#define CVMX_MIO_BOOT_REG_TIMX(offset) \ 58 CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8)) 59#define CVMX_MIO_BOOT_THR \ 60 CVMX_ADD_IO_SEG(0x00011800000000B0ull) 61#define CVMX_MIO_FUS_BNK_DATX(offset) \ 62 CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8)) 63#define CVMX_MIO_FUS_DAT0 \ 64 CVMX_ADD_IO_SEG(0x0001180000001400ull) 65#define CVMX_MIO_FUS_DAT1 \ 66 CVMX_ADD_IO_SEG(0x0001180000001408ull) 67#define CVMX_MIO_FUS_DAT2 \ 68 CVMX_ADD_IO_SEG(0x0001180000001410ull) 69#define CVMX_MIO_FUS_DAT3 \ 70 CVMX_ADD_IO_SEG(0x0001180000001418ull) 71#define CVMX_MIO_FUS_EMA \ 72 CVMX_ADD_IO_SEG(0x0001180000001550ull) 73#define CVMX_MIO_FUS_PDF \ 74 CVMX_ADD_IO_SEG(0x0001180000001420ull) 75#define CVMX_MIO_FUS_PLL \ 76 CVMX_ADD_IO_SEG(0x0001180000001580ull) 77#define CVMX_MIO_FUS_PROG \ 78 CVMX_ADD_IO_SEG(0x0001180000001510ull) 79#define CVMX_MIO_FUS_PROG_TIMES \ 80 CVMX_ADD_IO_SEG(0x0001180000001518ull) 81#define CVMX_MIO_FUS_RCMD \ 82 CVMX_ADD_IO_SEG(0x0001180000001500ull) 83#define CVMX_MIO_FUS_SPR_REPAIR_RES \ 84 CVMX_ADD_IO_SEG(0x0001180000001548ull) 85#define CVMX_MIO_FUS_SPR_REPAIR_SUM \ 86 CVMX_ADD_IO_SEG(0x0001180000001540ull) 87#define CVMX_MIO_FUS_UNLOCK \ 88 CVMX_ADD_IO_SEG(0x0001180000001578ull) 89#define CVMX_MIO_FUS_WADR \ 90 CVMX_ADD_IO_SEG(0x0001180000001508ull) 91#define CVMX_MIO_NDF_DMA_CFG \ 92 CVMX_ADD_IO_SEG(0x0001180000000168ull) 93#define CVMX_MIO_NDF_DMA_INT \ 94 CVMX_ADD_IO_SEG(0x0001180000000170ull) 95#define CVMX_MIO_NDF_DMA_INT_EN \ 96 CVMX_ADD_IO_SEG(0x0001180000000178ull) 97#define CVMX_MIO_PLL_CTL \ 98 CVMX_ADD_IO_SEG(0x0001180000001448ull) 99#define CVMX_MIO_PLL_SETTING \ 100 CVMX_ADD_IO_SEG(0x0001180000001440ull) 101#define CVMX_MIO_TWSX_INT(offset) \ 102 CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512)) 103#define CVMX_MIO_TWSX_SW_TWSI(offset) \ 104 CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512)) 105#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \ 106 CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512)) 107#define CVMX_MIO_TWSX_TWSI_SW(offset) \ 108 CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512)) 109#define CVMX_MIO_UART2_DLH \ 110 CVMX_ADD_IO_SEG(0x0001180000000488ull) 111#define CVMX_MIO_UART2_DLL \ 112 CVMX_ADD_IO_SEG(0x0001180000000480ull) 113#define CVMX_MIO_UART2_FAR \ 114 CVMX_ADD_IO_SEG(0x0001180000000520ull) 115#define CVMX_MIO_UART2_FCR \ 116 CVMX_ADD_IO_SEG(0x0001180000000450ull) 117#define CVMX_MIO_UART2_HTX \ 118 CVMX_ADD_IO_SEG(0x0001180000000708ull) 119#define CVMX_MIO_UART2_IER \ 120 CVMX_ADD_IO_SEG(0x0001180000000408ull) 121#define CVMX_MIO_UART2_IIR \ 122 CVMX_ADD_IO_SEG(0x0001180000000410ull) 123#define CVMX_MIO_UART2_LCR \ 124 CVMX_ADD_IO_SEG(0x0001180000000418ull) 125#define CVMX_MIO_UART2_LSR \ 126 CVMX_ADD_IO_SEG(0x0001180000000428ull) 127#define CVMX_MIO_UART2_MCR \ 128 CVMX_ADD_IO_SEG(0x0001180000000420ull) 129#define CVMX_MIO_UART2_MSR \ 130 CVMX_ADD_IO_SEG(0x0001180000000430ull) 131#define CVMX_MIO_UART2_RBR \ 132 CVMX_ADD_IO_SEG(0x0001180000000400ull) 133#define CVMX_MIO_UART2_RFL \ 134 CVMX_ADD_IO_SEG(0x0001180000000608ull) 135#define CVMX_MIO_UART2_RFW \ 136 CVMX_ADD_IO_SEG(0x0001180000000530ull) 137#define CVMX_MIO_UART2_SBCR \ 138 CVMX_ADD_IO_SEG(0x0001180000000620ull) 139#define CVMX_MIO_UART2_SCR \ 140 CVMX_ADD_IO_SEG(0x0001180000000438ull) 141#define CVMX_MIO_UART2_SFE \ 142 CVMX_ADD_IO_SEG(0x0001180000000630ull) 143#define CVMX_MIO_UART2_SRR \ 144 CVMX_ADD_IO_SEG(0x0001180000000610ull) 145#define CVMX_MIO_UART2_SRT \ 146 CVMX_ADD_IO_SEG(0x0001180000000638ull) 147#define CVMX_MIO_UART2_SRTS \ 148 CVMX_ADD_IO_SEG(0x0001180000000618ull) 149#define CVMX_MIO_UART2_STT \ 150 CVMX_ADD_IO_SEG(0x0001180000000700ull) 151#define CVMX_MIO_UART2_TFL \ 152 CVMX_ADD_IO_SEG(0x0001180000000600ull) 153#define CVMX_MIO_UART2_TFR \ 154 CVMX_ADD_IO_SEG(0x0001180000000528ull) 155#define CVMX_MIO_UART2_THR \ 156 CVMX_ADD_IO_SEG(0x0001180000000440ull) 157#define CVMX_MIO_UART2_USR \ 158 CVMX_ADD_IO_SEG(0x0001180000000538ull) 159#define CVMX_MIO_UARTX_DLH(offset) \ 160 CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024)) 161#define CVMX_MIO_UARTX_DLL(offset) \ 162 CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024)) 163#define CVMX_MIO_UARTX_FAR(offset) \ 164 CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024)) 165#define CVMX_MIO_UARTX_FCR(offset) \ 166 CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024)) 167#define CVMX_MIO_UARTX_HTX(offset) \ 168 CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024)) 169#define CVMX_MIO_UARTX_IER(offset) \ 170 CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024)) 171#define CVMX_MIO_UARTX_IIR(offset) \ 172 CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024)) 173#define CVMX_MIO_UARTX_LCR(offset) \ 174 CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024)) 175#define CVMX_MIO_UARTX_LSR(offset) \ 176 CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024)) 177#define CVMX_MIO_UARTX_MCR(offset) \ 178 CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024)) 179#define CVMX_MIO_UARTX_MSR(offset) \ 180 CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024)) 181#define CVMX_MIO_UARTX_RBR(offset) \ 182 CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024)) 183#define CVMX_MIO_UARTX_RFL(offset) \ 184 CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024)) 185#define CVMX_MIO_UARTX_RFW(offset) \ 186 CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024)) 187#define CVMX_MIO_UARTX_SBCR(offset) \ 188 CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024)) 189#define CVMX_MIO_UARTX_SCR(offset) \ 190 CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024)) 191#define CVMX_MIO_UARTX_SFE(offset) \ 192 CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024)) 193#define CVMX_MIO_UARTX_SRR(offset) \ 194 CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024)) 195#define CVMX_MIO_UARTX_SRT(offset) \ 196 CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024)) 197#define CVMX_MIO_UARTX_SRTS(offset) \ 198 CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024)) 199#define CVMX_MIO_UARTX_STT(offset) \ 200 CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024)) 201#define CVMX_MIO_UARTX_TFL(offset) \ 202 CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024)) 203#define CVMX_MIO_UARTX_TFR(offset) \ 204 CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024)) 205#define CVMX_MIO_UARTX_THR(offset) \ 206 CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024)) 207#define CVMX_MIO_UARTX_USR(offset) \ 208 CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024)) 209 210union cvmx_mio_boot_bist_stat { 211 uint64_t u64; 212 struct cvmx_mio_boot_bist_stat_s { 213 uint64_t reserved_2_63:62; 214 uint64_t loc:1; 215 uint64_t ncbi:1; 216 } s; 217 struct cvmx_mio_boot_bist_stat_cn30xx { 218 uint64_t reserved_4_63:60; 219 uint64_t ncbo_1:1; 220 uint64_t ncbo_0:1; 221 uint64_t loc:1; 222 uint64_t ncbi:1; 223 } cn30xx; 224 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; 225 struct cvmx_mio_boot_bist_stat_cn38xx { 226 uint64_t reserved_3_63:61; 227 uint64_t ncbo_0:1; 228 uint64_t loc:1; 229 uint64_t ncbi:1; 230 } cn38xx; 231 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; 232 struct cvmx_mio_boot_bist_stat_cn50xx { 233 uint64_t reserved_6_63:58; 234 uint64_t pcm_1:1; 235 uint64_t pcm_0:1; 236 uint64_t ncbo_1:1; 237 uint64_t ncbo_0:1; 238 uint64_t loc:1; 239 uint64_t ncbi:1; 240 } cn50xx; 241 struct cvmx_mio_boot_bist_stat_cn52xx { 242 uint64_t reserved_6_63:58; 243 uint64_t ndf:2; 244 uint64_t ncbo_0:1; 245 uint64_t dma:1; 246 uint64_t loc:1; 247 uint64_t ncbi:1; 248 } cn52xx; 249 struct cvmx_mio_boot_bist_stat_cn52xxp1 { 250 uint64_t reserved_4_63:60; 251 uint64_t ncbo_0:1; 252 uint64_t dma:1; 253 uint64_t loc:1; 254 uint64_t ncbi:1; 255 } cn52xxp1; 256 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; 257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 258 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 260}; 261 262union cvmx_mio_boot_comp { 263 uint64_t u64; 264 struct cvmx_mio_boot_comp_s { 265 uint64_t reserved_10_63:54; 266 uint64_t pctl:5; 267 uint64_t nctl:5; 268 } s; 269 struct cvmx_mio_boot_comp_s cn50xx; 270 struct cvmx_mio_boot_comp_s cn52xx; 271 struct cvmx_mio_boot_comp_s cn52xxp1; 272 struct cvmx_mio_boot_comp_s cn56xx; 273 struct cvmx_mio_boot_comp_s cn56xxp1; 274}; 275 276union cvmx_mio_boot_dma_cfgx { 277 uint64_t u64; 278 struct cvmx_mio_boot_dma_cfgx_s { 279 uint64_t en:1; 280 uint64_t rw:1; 281 uint64_t clr:1; 282 uint64_t reserved_60_60:1; 283 uint64_t swap32:1; 284 uint64_t swap16:1; 285 uint64_t swap8:1; 286 uint64_t endian:1; 287 uint64_t size:20; 288 uint64_t adr:36; 289 } s; 290 struct cvmx_mio_boot_dma_cfgx_s cn52xx; 291 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 292 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 293 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 294}; 295 296union cvmx_mio_boot_dma_intx { 297 uint64_t u64; 298 struct cvmx_mio_boot_dma_intx_s { 299 uint64_t reserved_2_63:62; 300 uint64_t dmarq:1; 301 uint64_t done:1; 302 } s; 303 struct cvmx_mio_boot_dma_intx_s cn52xx; 304 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 305 struct cvmx_mio_boot_dma_intx_s cn56xx; 306 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 307}; 308 309union cvmx_mio_boot_dma_int_enx { 310 uint64_t u64; 311 struct cvmx_mio_boot_dma_int_enx_s { 312 uint64_t reserved_2_63:62; 313 uint64_t dmarq:1; 314 uint64_t done:1; 315 } s; 316 struct cvmx_mio_boot_dma_int_enx_s cn52xx; 317 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 318 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 319 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 320}; 321 322union cvmx_mio_boot_dma_timx { 323 uint64_t u64; 324 struct cvmx_mio_boot_dma_timx_s { 325 uint64_t dmack_pi:1; 326 uint64_t dmarq_pi:1; 327 uint64_t tim_mult:2; 328 uint64_t rd_dly:3; 329 uint64_t ddr:1; 330 uint64_t width:1; 331 uint64_t reserved_48_54:7; 332 uint64_t pause:6; 333 uint64_t dmack_h:6; 334 uint64_t we_n:6; 335 uint64_t we_a:6; 336 uint64_t oe_n:6; 337 uint64_t oe_a:6; 338 uint64_t dmack_s:6; 339 uint64_t dmarq:6; 340 } s; 341 struct cvmx_mio_boot_dma_timx_s cn52xx; 342 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 343 struct cvmx_mio_boot_dma_timx_s cn56xx; 344 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 345}; 346 347union cvmx_mio_boot_err { 348 uint64_t u64; 349 struct cvmx_mio_boot_err_s { 350 uint64_t reserved_2_63:62; 351 uint64_t wait_err:1; 352 uint64_t adr_err:1; 353 } s; 354 struct cvmx_mio_boot_err_s cn30xx; 355 struct cvmx_mio_boot_err_s cn31xx; 356 struct cvmx_mio_boot_err_s cn38xx; 357 struct cvmx_mio_boot_err_s cn38xxp2; 358 struct cvmx_mio_boot_err_s cn50xx; 359 struct cvmx_mio_boot_err_s cn52xx; 360 struct cvmx_mio_boot_err_s cn52xxp1; 361 struct cvmx_mio_boot_err_s cn56xx; 362 struct cvmx_mio_boot_err_s cn56xxp1; 363 struct cvmx_mio_boot_err_s cn58xx; 364 struct cvmx_mio_boot_err_s cn58xxp1; 365}; 366 367union cvmx_mio_boot_int { 368 uint64_t u64; 369 struct cvmx_mio_boot_int_s { 370 uint64_t reserved_2_63:62; 371 uint64_t wait_int:1; 372 uint64_t adr_int:1; 373 } s; 374 struct cvmx_mio_boot_int_s cn30xx; 375 struct cvmx_mio_boot_int_s cn31xx; 376 struct cvmx_mio_boot_int_s cn38xx; 377 struct cvmx_mio_boot_int_s cn38xxp2; 378 struct cvmx_mio_boot_int_s cn50xx; 379 struct cvmx_mio_boot_int_s cn52xx; 380 struct cvmx_mio_boot_int_s cn52xxp1; 381 struct cvmx_mio_boot_int_s cn56xx; 382 struct cvmx_mio_boot_int_s cn56xxp1; 383 struct cvmx_mio_boot_int_s cn58xx; 384 struct cvmx_mio_boot_int_s cn58xxp1; 385}; 386 387union cvmx_mio_boot_loc_adr { 388 uint64_t u64; 389 struct cvmx_mio_boot_loc_adr_s { 390 uint64_t reserved_8_63:56; 391 uint64_t adr:5; 392 uint64_t reserved_0_2:3; 393 } s; 394 struct cvmx_mio_boot_loc_adr_s cn30xx; 395 struct cvmx_mio_boot_loc_adr_s cn31xx; 396 struct cvmx_mio_boot_loc_adr_s cn38xx; 397 struct cvmx_mio_boot_loc_adr_s cn38xxp2; 398 struct cvmx_mio_boot_loc_adr_s cn50xx; 399 struct cvmx_mio_boot_loc_adr_s cn52xx; 400 struct cvmx_mio_boot_loc_adr_s cn52xxp1; 401 struct cvmx_mio_boot_loc_adr_s cn56xx; 402 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 403 struct cvmx_mio_boot_loc_adr_s cn58xx; 404 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 405}; 406 407union cvmx_mio_boot_loc_cfgx { 408 uint64_t u64; 409 struct cvmx_mio_boot_loc_cfgx_s { 410 uint64_t reserved_32_63:32; 411 uint64_t en:1; 412 uint64_t reserved_28_30:3; 413 uint64_t base:25; 414 uint64_t reserved_0_2:3; 415 } s; 416 struct cvmx_mio_boot_loc_cfgx_s cn30xx; 417 struct cvmx_mio_boot_loc_cfgx_s cn31xx; 418 struct cvmx_mio_boot_loc_cfgx_s cn38xx; 419 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2; 420 struct cvmx_mio_boot_loc_cfgx_s cn50xx; 421 struct cvmx_mio_boot_loc_cfgx_s cn52xx; 422 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1; 423 struct cvmx_mio_boot_loc_cfgx_s cn56xx; 424 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 425 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 426 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 427}; 428 429union cvmx_mio_boot_loc_dat { 430 uint64_t u64; 431 struct cvmx_mio_boot_loc_dat_s { 432 uint64_t data:64; 433 } s; 434 struct cvmx_mio_boot_loc_dat_s cn30xx; 435 struct cvmx_mio_boot_loc_dat_s cn31xx; 436 struct cvmx_mio_boot_loc_dat_s cn38xx; 437 struct cvmx_mio_boot_loc_dat_s cn38xxp2; 438 struct cvmx_mio_boot_loc_dat_s cn50xx; 439 struct cvmx_mio_boot_loc_dat_s cn52xx; 440 struct cvmx_mio_boot_loc_dat_s cn52xxp1; 441 struct cvmx_mio_boot_loc_dat_s cn56xx; 442 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 443 struct cvmx_mio_boot_loc_dat_s cn58xx; 444 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 445}; 446 447union cvmx_mio_boot_pin_defs { 448 uint64_t u64; 449 struct cvmx_mio_boot_pin_defs_s { 450 uint64_t reserved_16_63:48; 451 uint64_t ale:1; 452 uint64_t width:1; 453 uint64_t dmack_p2:1; 454 uint64_t dmack_p1:1; 455 uint64_t dmack_p0:1; 456 uint64_t term:2; 457 uint64_t nand:1; 458 uint64_t reserved_0_7:8; 459 } s; 460 struct cvmx_mio_boot_pin_defs_cn52xx { 461 uint64_t reserved_16_63:48; 462 uint64_t ale:1; 463 uint64_t width:1; 464 uint64_t reserved_13_13:1; 465 uint64_t dmack_p1:1; 466 uint64_t dmack_p0:1; 467 uint64_t term:2; 468 uint64_t nand:1; 469 uint64_t reserved_0_7:8; 470 } cn52xx; 471 struct cvmx_mio_boot_pin_defs_cn56xx { 472 uint64_t reserved_16_63:48; 473 uint64_t ale:1; 474 uint64_t width:1; 475 uint64_t dmack_p2:1; 476 uint64_t dmack_p1:1; 477 uint64_t dmack_p0:1; 478 uint64_t term:2; 479 uint64_t reserved_0_8:9; 480 } cn56xx; 481}; 482 483union cvmx_mio_boot_reg_cfgx { 484 uint64_t u64; 485 struct cvmx_mio_boot_reg_cfgx_s { 486 uint64_t reserved_44_63:20; 487 uint64_t dmack:2; 488 uint64_t tim_mult:2; 489 uint64_t rd_dly:3; 490 uint64_t sam:1; 491 uint64_t we_ext:2; 492 uint64_t oe_ext:2; 493 uint64_t en:1; 494 uint64_t orbit:1; 495 uint64_t ale:1; 496 uint64_t width:1; 497 uint64_t size:12; 498 uint64_t base:16; 499 } s; 500 struct cvmx_mio_boot_reg_cfgx_cn30xx { 501 uint64_t reserved_37_63:27; 502 uint64_t sam:1; 503 uint64_t we_ext:2; 504 uint64_t oe_ext:2; 505 uint64_t en:1; 506 uint64_t orbit:1; 507 uint64_t ale:1; 508 uint64_t width:1; 509 uint64_t size:12; 510 uint64_t base:16; 511 } cn30xx; 512 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; 513 struct cvmx_mio_boot_reg_cfgx_cn38xx { 514 uint64_t reserved_32_63:32; 515 uint64_t en:1; 516 uint64_t orbit:1; 517 uint64_t reserved_28_29:2; 518 uint64_t size:12; 519 uint64_t base:16; 520 } cn38xx; 521 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; 522 struct cvmx_mio_boot_reg_cfgx_cn50xx { 523 uint64_t reserved_42_63:22; 524 uint64_t tim_mult:2; 525 uint64_t rd_dly:3; 526 uint64_t sam:1; 527 uint64_t we_ext:2; 528 uint64_t oe_ext:2; 529 uint64_t en:1; 530 uint64_t orbit:1; 531 uint64_t ale:1; 532 uint64_t width:1; 533 uint64_t size:12; 534 uint64_t base:16; 535 } cn50xx; 536 struct cvmx_mio_boot_reg_cfgx_s cn52xx; 537 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; 538 struct cvmx_mio_boot_reg_cfgx_s cn56xx; 539 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 540 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 541 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 542}; 543 544union cvmx_mio_boot_reg_timx { 545 uint64_t u64; 546 struct cvmx_mio_boot_reg_timx_s { 547 uint64_t pagem:1; 548 uint64_t waitm:1; 549 uint64_t pages:2; 550 uint64_t ale:6; 551 uint64_t page:6; 552 uint64_t wait:6; 553 uint64_t pause:6; 554 uint64_t wr_hld:6; 555 uint64_t rd_hld:6; 556 uint64_t we:6; 557 uint64_t oe:6; 558 uint64_t ce:6; 559 uint64_t adr:6; 560 } s; 561 struct cvmx_mio_boot_reg_timx_s cn30xx; 562 struct cvmx_mio_boot_reg_timx_s cn31xx; 563 struct cvmx_mio_boot_reg_timx_cn38xx { 564 uint64_t pagem:1; 565 uint64_t waitm:1; 566 uint64_t pages:2; 567 uint64_t reserved_54_59:6; 568 uint64_t page:6; 569 uint64_t wait:6; 570 uint64_t pause:6; 571 uint64_t wr_hld:6; 572 uint64_t rd_hld:6; 573 uint64_t we:6; 574 uint64_t oe:6; 575 uint64_t ce:6; 576 uint64_t adr:6; 577 } cn38xx; 578 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; 579 struct cvmx_mio_boot_reg_timx_s cn50xx; 580 struct cvmx_mio_boot_reg_timx_s cn52xx; 581 struct cvmx_mio_boot_reg_timx_s cn52xxp1; 582 struct cvmx_mio_boot_reg_timx_s cn56xx; 583 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 584 struct cvmx_mio_boot_reg_timx_s cn58xx; 585 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 586}; 587 588union cvmx_mio_boot_thr { 589 uint64_t u64; 590 struct cvmx_mio_boot_thr_s { 591 uint64_t reserved_22_63:42; 592 uint64_t dma_thr:6; 593 uint64_t reserved_14_15:2; 594 uint64_t fif_cnt:6; 595 uint64_t reserved_6_7:2; 596 uint64_t fif_thr:6; 597 } s; 598 struct cvmx_mio_boot_thr_cn30xx { 599 uint64_t reserved_14_63:50; 600 uint64_t fif_cnt:6; 601 uint64_t reserved_6_7:2; 602 uint64_t fif_thr:6; 603 } cn30xx; 604 struct cvmx_mio_boot_thr_cn30xx cn31xx; 605 struct cvmx_mio_boot_thr_cn30xx cn38xx; 606 struct cvmx_mio_boot_thr_cn30xx cn38xxp2; 607 struct cvmx_mio_boot_thr_cn30xx cn50xx; 608 struct cvmx_mio_boot_thr_s cn52xx; 609 struct cvmx_mio_boot_thr_s cn52xxp1; 610 struct cvmx_mio_boot_thr_s cn56xx; 611 struct cvmx_mio_boot_thr_s cn56xxp1; 612 struct cvmx_mio_boot_thr_cn30xx cn58xx; 613 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 614}; 615 616union cvmx_mio_fus_bnk_datx { 617 uint64_t u64; 618 struct cvmx_mio_fus_bnk_datx_s { 619 uint64_t dat:64; 620 } s; 621 struct cvmx_mio_fus_bnk_datx_s cn50xx; 622 struct cvmx_mio_fus_bnk_datx_s cn52xx; 623 struct cvmx_mio_fus_bnk_datx_s cn52xxp1; 624 struct cvmx_mio_fus_bnk_datx_s cn56xx; 625 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 626 struct cvmx_mio_fus_bnk_datx_s cn58xx; 627 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 628}; 629 630union cvmx_mio_fus_dat0 { 631 uint64_t u64; 632 struct cvmx_mio_fus_dat0_s { 633 uint64_t reserved_32_63:32; 634 uint64_t man_info:32; 635 } s; 636 struct cvmx_mio_fus_dat0_s cn30xx; 637 struct cvmx_mio_fus_dat0_s cn31xx; 638 struct cvmx_mio_fus_dat0_s cn38xx; 639 struct cvmx_mio_fus_dat0_s cn38xxp2; 640 struct cvmx_mio_fus_dat0_s cn50xx; 641 struct cvmx_mio_fus_dat0_s cn52xx; 642 struct cvmx_mio_fus_dat0_s cn52xxp1; 643 struct cvmx_mio_fus_dat0_s cn56xx; 644 struct cvmx_mio_fus_dat0_s cn56xxp1; 645 struct cvmx_mio_fus_dat0_s cn58xx; 646 struct cvmx_mio_fus_dat0_s cn58xxp1; 647}; 648 649union cvmx_mio_fus_dat1 { 650 uint64_t u64; 651 struct cvmx_mio_fus_dat1_s { 652 uint64_t reserved_32_63:32; 653 uint64_t man_info:32; 654 } s; 655 struct cvmx_mio_fus_dat1_s cn30xx; 656 struct cvmx_mio_fus_dat1_s cn31xx; 657 struct cvmx_mio_fus_dat1_s cn38xx; 658 struct cvmx_mio_fus_dat1_s cn38xxp2; 659 struct cvmx_mio_fus_dat1_s cn50xx; 660 struct cvmx_mio_fus_dat1_s cn52xx; 661 struct cvmx_mio_fus_dat1_s cn52xxp1; 662 struct cvmx_mio_fus_dat1_s cn56xx; 663 struct cvmx_mio_fus_dat1_s cn56xxp1; 664 struct cvmx_mio_fus_dat1_s cn58xx; 665 struct cvmx_mio_fus_dat1_s cn58xxp1; 666}; 667 668union cvmx_mio_fus_dat2 { 669 uint64_t u64; 670 struct cvmx_mio_fus_dat2_s { 671 uint64_t reserved_34_63:30; 672 uint64_t fus318:1; 673 uint64_t raid_en:1; 674 uint64_t reserved_30_31:2; 675 uint64_t nokasu:1; 676 uint64_t nodfa_cp2:1; 677 uint64_t nomul:1; 678 uint64_t nocrypto:1; 679 uint64_t rst_sht:1; 680 uint64_t bist_dis:1; 681 uint64_t chip_id:8; 682 uint64_t reserved_0_15:16; 683 } s; 684 struct cvmx_mio_fus_dat2_cn30xx { 685 uint64_t reserved_29_63:35; 686 uint64_t nodfa_cp2:1; 687 uint64_t nomul:1; 688 uint64_t nocrypto:1; 689 uint64_t rst_sht:1; 690 uint64_t bist_dis:1; 691 uint64_t chip_id:8; 692 uint64_t pll_off:4; 693 uint64_t reserved_1_11:11; 694 uint64_t pp_dis:1; 695 } cn30xx; 696 struct cvmx_mio_fus_dat2_cn31xx { 697 uint64_t reserved_29_63:35; 698 uint64_t nodfa_cp2:1; 699 uint64_t nomul:1; 700 uint64_t nocrypto:1; 701 uint64_t rst_sht:1; 702 uint64_t bist_dis:1; 703 uint64_t chip_id:8; 704 uint64_t pll_off:4; 705 uint64_t reserved_2_11:10; 706 uint64_t pp_dis:2; 707 } cn31xx; 708 struct cvmx_mio_fus_dat2_cn38xx { 709 uint64_t reserved_29_63:35; 710 uint64_t nodfa_cp2:1; 711 uint64_t nomul:1; 712 uint64_t nocrypto:1; 713 uint64_t rst_sht:1; 714 uint64_t bist_dis:1; 715 uint64_t chip_id:8; 716 uint64_t pp_dis:16; 717 } cn38xx; 718 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; 719 struct cvmx_mio_fus_dat2_cn50xx { 720 uint64_t reserved_34_63:30; 721 uint64_t fus318:1; 722 uint64_t raid_en:1; 723 uint64_t reserved_30_31:2; 724 uint64_t nokasu:1; 725 uint64_t nodfa_cp2:1; 726 uint64_t nomul:1; 727 uint64_t nocrypto:1; 728 uint64_t rst_sht:1; 729 uint64_t bist_dis:1; 730 uint64_t chip_id:8; 731 uint64_t reserved_2_15:14; 732 uint64_t pp_dis:2; 733 } cn50xx; 734 struct cvmx_mio_fus_dat2_cn52xx { 735 uint64_t reserved_34_63:30; 736 uint64_t fus318:1; 737 uint64_t raid_en:1; 738 uint64_t reserved_30_31:2; 739 uint64_t nokasu:1; 740 uint64_t nodfa_cp2:1; 741 uint64_t nomul:1; 742 uint64_t nocrypto:1; 743 uint64_t rst_sht:1; 744 uint64_t bist_dis:1; 745 uint64_t chip_id:8; 746 uint64_t reserved_4_15:12; 747 uint64_t pp_dis:4; 748 } cn52xx; 749 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; 750 struct cvmx_mio_fus_dat2_cn56xx { 751 uint64_t reserved_34_63:30; 752 uint64_t fus318:1; 753 uint64_t raid_en:1; 754 uint64_t reserved_30_31:2; 755 uint64_t nokasu:1; 756 uint64_t nodfa_cp2:1; 757 uint64_t nomul:1; 758 uint64_t nocrypto:1; 759 uint64_t rst_sht:1; 760 uint64_t bist_dis:1; 761 uint64_t chip_id:8; 762 uint64_t reserved_12_15:4; 763 uint64_t pp_dis:12; 764 } cn56xx; 765 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; 766 struct cvmx_mio_fus_dat2_cn58xx { 767 uint64_t reserved_30_63:34; 768 uint64_t nokasu:1; 769 uint64_t nodfa_cp2:1; 770 uint64_t nomul:1; 771 uint64_t nocrypto:1; 772 uint64_t rst_sht:1; 773 uint64_t bist_dis:1; 774 uint64_t chip_id:8; 775 uint64_t pp_dis:16; 776 } cn58xx; 777 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 778}; 779 780union cvmx_mio_fus_dat3 { 781 uint64_t u64; 782 struct cvmx_mio_fus_dat3_s { 783 uint64_t reserved_32_63:32; 784 uint64_t pll_div4:1; 785 uint64_t zip_crip:2; 786 uint64_t bar2_en:1; 787 uint64_t efus_lck:1; 788 uint64_t efus_ign:1; 789 uint64_t nozip:1; 790 uint64_t nodfa_dte:1; 791 uint64_t icache:24; 792 } s; 793 struct cvmx_mio_fus_dat3_cn30xx { 794 uint64_t reserved_32_63:32; 795 uint64_t pll_div4:1; 796 uint64_t reserved_29_30:2; 797 uint64_t bar2_en:1; 798 uint64_t efus_lck:1; 799 uint64_t efus_ign:1; 800 uint64_t nozip:1; 801 uint64_t nodfa_dte:1; 802 uint64_t icache:24; 803 } cn30xx; 804 struct cvmx_mio_fus_dat3_s cn31xx; 805 struct cvmx_mio_fus_dat3_cn38xx { 806 uint64_t reserved_31_63:33; 807 uint64_t zip_crip:2; 808 uint64_t bar2_en:1; 809 uint64_t efus_lck:1; 810 uint64_t efus_ign:1; 811 uint64_t nozip:1; 812 uint64_t nodfa_dte:1; 813 uint64_t icache:24; 814 } cn38xx; 815 struct cvmx_mio_fus_dat3_cn38xxp2 { 816 uint64_t reserved_29_63:35; 817 uint64_t bar2_en:1; 818 uint64_t efus_lck:1; 819 uint64_t efus_ign:1; 820 uint64_t nozip:1; 821 uint64_t nodfa_dte:1; 822 uint64_t icache:24; 823 } cn38xxp2; 824 struct cvmx_mio_fus_dat3_cn38xx cn50xx; 825 struct cvmx_mio_fus_dat3_cn38xx cn52xx; 826 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1; 827 struct cvmx_mio_fus_dat3_cn38xx cn56xx; 828 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 829 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 830 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 831}; 832 833union cvmx_mio_fus_ema { 834 uint64_t u64; 835 struct cvmx_mio_fus_ema_s { 836 uint64_t reserved_7_63:57; 837 uint64_t eff_ema:3; 838 uint64_t reserved_3_3:1; 839 uint64_t ema:3; 840 } s; 841 struct cvmx_mio_fus_ema_s cn50xx; 842 struct cvmx_mio_fus_ema_s cn52xx; 843 struct cvmx_mio_fus_ema_s cn52xxp1; 844 struct cvmx_mio_fus_ema_s cn56xx; 845 struct cvmx_mio_fus_ema_s cn56xxp1; 846 struct cvmx_mio_fus_ema_cn58xx { 847 uint64_t reserved_2_63:62; 848 uint64_t ema:2; 849 } cn58xx; 850 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 851}; 852 853union cvmx_mio_fus_pdf { 854 uint64_t u64; 855 struct cvmx_mio_fus_pdf_s { 856 uint64_t pdf:64; 857 } s; 858 struct cvmx_mio_fus_pdf_s cn50xx; 859 struct cvmx_mio_fus_pdf_s cn52xx; 860 struct cvmx_mio_fus_pdf_s cn52xxp1; 861 struct cvmx_mio_fus_pdf_s cn56xx; 862 struct cvmx_mio_fus_pdf_s cn56xxp1; 863 struct cvmx_mio_fus_pdf_s cn58xx; 864}; 865 866union cvmx_mio_fus_pll { 867 uint64_t u64; 868 struct cvmx_mio_fus_pll_s { 869 uint64_t reserved_2_63:62; 870 uint64_t rfslip:1; 871 uint64_t fbslip:1; 872 } s; 873 struct cvmx_mio_fus_pll_s cn50xx; 874 struct cvmx_mio_fus_pll_s cn52xx; 875 struct cvmx_mio_fus_pll_s cn52xxp1; 876 struct cvmx_mio_fus_pll_s cn56xx; 877 struct cvmx_mio_fus_pll_s cn56xxp1; 878 struct cvmx_mio_fus_pll_s cn58xx; 879 struct cvmx_mio_fus_pll_s cn58xxp1; 880}; 881 882union cvmx_mio_fus_prog { 883 uint64_t u64; 884 struct cvmx_mio_fus_prog_s { 885 uint64_t reserved_1_63:63; 886 uint64_t prog:1; 887 } s; 888 struct cvmx_mio_fus_prog_s cn30xx; 889 struct cvmx_mio_fus_prog_s cn31xx; 890 struct cvmx_mio_fus_prog_s cn38xx; 891 struct cvmx_mio_fus_prog_s cn38xxp2; 892 struct cvmx_mio_fus_prog_s cn50xx; 893 struct cvmx_mio_fus_prog_s cn52xx; 894 struct cvmx_mio_fus_prog_s cn52xxp1; 895 struct cvmx_mio_fus_prog_s cn56xx; 896 struct cvmx_mio_fus_prog_s cn56xxp1; 897 struct cvmx_mio_fus_prog_s cn58xx; 898 struct cvmx_mio_fus_prog_s cn58xxp1; 899}; 900 901union cvmx_mio_fus_prog_times { 902 uint64_t u64; 903 struct cvmx_mio_fus_prog_times_s { 904 uint64_t reserved_33_63:31; 905 uint64_t prog_pin:1; 906 uint64_t out:8; 907 uint64_t sclk_lo:4; 908 uint64_t sclk_hi:12; 909 uint64_t setup:8; 910 } s; 911 struct cvmx_mio_fus_prog_times_s cn50xx; 912 struct cvmx_mio_fus_prog_times_s cn52xx; 913 struct cvmx_mio_fus_prog_times_s cn52xxp1; 914 struct cvmx_mio_fus_prog_times_s cn56xx; 915 struct cvmx_mio_fus_prog_times_s cn56xxp1; 916 struct cvmx_mio_fus_prog_times_s cn58xx; 917 struct cvmx_mio_fus_prog_times_s cn58xxp1; 918}; 919 920union cvmx_mio_fus_rcmd { 921 uint64_t u64; 922 struct cvmx_mio_fus_rcmd_s { 923 uint64_t reserved_24_63:40; 924 uint64_t dat:8; 925 uint64_t reserved_13_15:3; 926 uint64_t pend:1; 927 uint64_t reserved_9_11:3; 928 uint64_t efuse:1; 929 uint64_t addr:8; 930 } s; 931 struct cvmx_mio_fus_rcmd_cn30xx { 932 uint64_t reserved_24_63:40; 933 uint64_t dat:8; 934 uint64_t reserved_13_15:3; 935 uint64_t pend:1; 936 uint64_t reserved_9_11:3; 937 uint64_t efuse:1; 938 uint64_t reserved_7_7:1; 939 uint64_t addr:7; 940 } cn30xx; 941 struct cvmx_mio_fus_rcmd_cn30xx cn31xx; 942 struct cvmx_mio_fus_rcmd_cn30xx cn38xx; 943 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2; 944 struct cvmx_mio_fus_rcmd_cn30xx cn50xx; 945 struct cvmx_mio_fus_rcmd_s cn52xx; 946 struct cvmx_mio_fus_rcmd_s cn52xxp1; 947 struct cvmx_mio_fus_rcmd_s cn56xx; 948 struct cvmx_mio_fus_rcmd_s cn56xxp1; 949 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 950 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 951}; 952 953union cvmx_mio_fus_spr_repair_res { 954 uint64_t u64; 955 struct cvmx_mio_fus_spr_repair_res_s { 956 uint64_t reserved_42_63:22; 957 uint64_t repair2:14; 958 uint64_t repair1:14; 959 uint64_t repair0:14; 960 } s; 961 struct cvmx_mio_fus_spr_repair_res_s cn30xx; 962 struct cvmx_mio_fus_spr_repair_res_s cn31xx; 963 struct cvmx_mio_fus_spr_repair_res_s cn38xx; 964 struct cvmx_mio_fus_spr_repair_res_s cn50xx; 965 struct cvmx_mio_fus_spr_repair_res_s cn52xx; 966 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1; 967 struct cvmx_mio_fus_spr_repair_res_s cn56xx; 968 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 969 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 970 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 971}; 972 973union cvmx_mio_fus_spr_repair_sum { 974 uint64_t u64; 975 struct cvmx_mio_fus_spr_repair_sum_s { 976 uint64_t reserved_1_63:63; 977 uint64_t too_many:1; 978 } s; 979 struct cvmx_mio_fus_spr_repair_sum_s cn30xx; 980 struct cvmx_mio_fus_spr_repair_sum_s cn31xx; 981 struct cvmx_mio_fus_spr_repair_sum_s cn38xx; 982 struct cvmx_mio_fus_spr_repair_sum_s cn50xx; 983 struct cvmx_mio_fus_spr_repair_sum_s cn52xx; 984 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1; 985 struct cvmx_mio_fus_spr_repair_sum_s cn56xx; 986 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 987 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 988 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 989}; 990 991union cvmx_mio_fus_unlock { 992 uint64_t u64; 993 struct cvmx_mio_fus_unlock_s { 994 uint64_t reserved_24_63:40; 995 uint64_t key:24; 996 } s; 997 struct cvmx_mio_fus_unlock_s cn30xx; 998 struct cvmx_mio_fus_unlock_s cn31xx; 999}; 1000
1001union cvmx_mio_fus_wadr { 1002 uint64_t u64; 1003 struct cvmx_mio_fus_wadr_s { 1004 uint64_t reserved_10_63:54; 1005 uint64_t addr:10; 1006 } s; 1007 struct cvmx_mio_fus_wadr_s cn30xx; 1008 struct cvmx_mio_fus_wadr_s cn31xx; 1009 struct cvmx_mio_fus_wadr_s cn38xx; 1010 struct cvmx_mio_fus_wadr_s cn38xxp2; 1011 struct cvmx_mio_fus_wadr_cn50xx { 1012 uint64_t reserved_2_63:62; 1013 uint64_t addr:2; 1014 } cn50xx; 1015 struct cvmx_mio_fus_wadr_cn52xx { 1016 uint64_t reserved_3_63:61; 1017 uint64_t addr:3; 1018 } cn52xx; 1019 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; 1020 struct cvmx_mio_fus_wadr_cn52xx cn56xx; 1021 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 1022 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 1023 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 1024}; 1025 1026union cvmx_mio_ndf_dma_cfg { 1027 uint64_t u64; 1028 struct cvmx_mio_ndf_dma_cfg_s { 1029 uint64_t en:1; 1030 uint64_t rw:1; 1031 uint64_t clr:1; 1032 uint64_t reserved_60_60:1; 1033 uint64_t swap32:1; 1034 uint64_t swap16:1; 1035 uint64_t swap8:1; 1036 uint64_t endian:1; 1037 uint64_t size:20; 1038 uint64_t adr:36; 1039 } s; 1040 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 1041}; 1042 1043union cvmx_mio_ndf_dma_int { 1044 uint64_t u64; 1045 struct cvmx_mio_ndf_dma_int_s { 1046 uint64_t reserved_1_63:63; 1047 uint64_t done:1; 1048 } s; 1049 struct cvmx_mio_ndf_dma_int_s cn52xx; 1050}; 1051 1052union cvmx_mio_ndf_dma_int_en { 1053 uint64_t u64; 1054 struct cvmx_mio_ndf_dma_int_en_s { 1055 uint64_t reserved_1_63:63; 1056 uint64_t done:1; 1057 } s; 1058 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 1059}; 1060 1061union cvmx_mio_pll_ctl { 1062 uint64_t u64; 1063 struct cvmx_mio_pll_ctl_s { 1064 uint64_t reserved_5_63:59; 1065 uint64_t bw_ctl:5; 1066 } s; 1067 struct cvmx_mio_pll_ctl_s cn30xx; 1068 struct cvmx_mio_pll_ctl_s cn31xx; 1069}; 1070 1071union cvmx_mio_pll_setting { 1072 uint64_t u64; 1073 struct cvmx_mio_pll_setting_s { 1074 uint64_t reserved_17_63:47; 1075 uint64_t setting:17; 1076 } s; 1077 struct cvmx_mio_pll_setting_s cn30xx; 1078 struct cvmx_mio_pll_setting_s cn31xx; 1079}; 1080 1081union cvmx_mio_twsx_int { 1082 uint64_t u64; 1083 struct cvmx_mio_twsx_int_s { 1084 uint64_t reserved_12_63:52; 1085 uint64_t scl:1; 1086 uint64_t sda:1; 1087 uint64_t scl_ovr:1; 1088 uint64_t sda_ovr:1; 1089 uint64_t reserved_7_7:1; 1090 uint64_t core_en:1; 1091 uint64_t ts_en:1; 1092 uint64_t st_en:1; 1093 uint64_t reserved_3_3:1; 1094 uint64_t core_int:1; 1095 uint64_t ts_int:1; 1096 uint64_t st_int:1; 1097 } s; 1098 struct cvmx_mio_twsx_int_s cn30xx; 1099 struct cvmx_mio_twsx_int_s cn31xx; 1100 struct cvmx_mio_twsx_int_s cn38xx; 1101 struct cvmx_mio_twsx_int_cn38xxp2 { 1102 uint64_t reserved_7_63:57; 1103 uint64_t core_en:1; 1104 uint64_t ts_en:1; 1105 uint64_t st_en:1; 1106 uint64_t reserved_3_3:1; 1107 uint64_t core_int:1; 1108 uint64_t ts_int:1; 1109 uint64_t st_int:1; 1110 } cn38xxp2; 1111 struct cvmx_mio_twsx_int_s cn50xx; 1112 struct cvmx_mio_twsx_int_s cn52xx; 1113 struct cvmx_mio_twsx_int_s cn52xxp1; 1114 struct cvmx_mio_twsx_int_s cn56xx; 1115 struct cvmx_mio_twsx_int_s cn56xxp1; 1116 struct cvmx_mio_twsx_int_s cn58xx; 1117 struct cvmx_mio_twsx_int_s cn58xxp1; 1118}; 1119 1120union cvmx_mio_twsx_sw_twsi { 1121 uint64_t u64; 1122 struct cvmx_mio_twsx_sw_twsi_s { 1123 uint64_t v:1; 1124 uint64_t slonly:1; 1125 uint64_t eia:1; 1126 uint64_t op:4; 1127 uint64_t r:1; 1128 uint64_t sovr:1; 1129 uint64_t size:3; 1130 uint64_t scr:2; 1131 uint64_t a:10; 1132 uint64_t ia:5; 1133 uint64_t eop_ia:3; 1134 uint64_t d:32; 1135 } s; 1136 struct cvmx_mio_twsx_sw_twsi_s cn30xx; 1137 struct cvmx_mio_twsx_sw_twsi_s cn31xx; 1138 struct cvmx_mio_twsx_sw_twsi_s cn38xx; 1139 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2; 1140 struct cvmx_mio_twsx_sw_twsi_s cn50xx; 1141 struct cvmx_mio_twsx_sw_twsi_s cn52xx; 1142 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1; 1143 struct cvmx_mio_twsx_sw_twsi_s cn56xx; 1144 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 1145 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 1146 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 1147}; 1148 1149union cvmx_mio_twsx_sw_twsi_ext { 1150 uint64_t u64; 1151 struct cvmx_mio_twsx_sw_twsi_ext_s { 1152 uint64_t reserved_40_63:24; 1153 uint64_t ia:8; 1154 uint64_t d:32; 1155 } s; 1156 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; 1157 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; 1158 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx; 1159 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2; 1160 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx; 1161 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx; 1162 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1; 1163 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx; 1164 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 1165 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 1166 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 1167}; 1168 1169union cvmx_mio_twsx_twsi_sw { 1170 uint64_t u64; 1171 struct cvmx_mio_twsx_twsi_sw_s { 1172 uint64_t v:2; 1173 uint64_t reserved_32_61:30; 1174 uint64_t d:32; 1175 } s; 1176 struct cvmx_mio_twsx_twsi_sw_s cn30xx; 1177 struct cvmx_mio_twsx_twsi_sw_s cn31xx; 1178 struct cvmx_mio_twsx_twsi_sw_s cn38xx; 1179 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2; 1180 struct cvmx_mio_twsx_twsi_sw_s cn50xx; 1181 struct cvmx_mio_twsx_twsi_sw_s cn52xx; 1182 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1; 1183 struct cvmx_mio_twsx_twsi_sw_s cn56xx; 1184 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 1185 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 1186 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 1187}; 1188 1189union cvmx_mio_uartx_dlh { 1190 uint64_t u64; 1191 struct cvmx_mio_uartx_dlh_s { 1192 uint64_t reserved_8_63:56; 1193 uint64_t dlh:8; 1194 } s; 1195 struct cvmx_mio_uartx_dlh_s cn30xx; 1196 struct cvmx_mio_uartx_dlh_s cn31xx; 1197 struct cvmx_mio_uartx_dlh_s cn38xx; 1198 struct cvmx_mio_uartx_dlh_s cn38xxp2; 1199 struct cvmx_mio_uartx_dlh_s cn50xx; 1200 struct cvmx_mio_uartx_dlh_s cn52xx; 1201 struct cvmx_mio_uartx_dlh_s cn52xxp1; 1202 struct cvmx_mio_uartx_dlh_s cn56xx; 1203 struct cvmx_mio_uartx_dlh_s cn56xxp1; 1204 struct cvmx_mio_uartx_dlh_s cn58xx; 1205 struct cvmx_mio_uartx_dlh_s cn58xxp1; 1206}; 1207 1208union cvmx_mio_uartx_dll { 1209 uint64_t u64; 1210 struct cvmx_mio_uartx_dll_s { 1211 uint64_t reserved_8_63:56; 1212 uint64_t dll:8; 1213 } s; 1214 struct cvmx_mio_uartx_dll_s cn30xx; 1215 struct cvmx_mio_uartx_dll_s cn31xx; 1216 struct cvmx_mio_uartx_dll_s cn38xx; 1217 struct cvmx_mio_uartx_dll_s cn38xxp2; 1218 struct cvmx_mio_uartx_dll_s cn50xx; 1219 struct cvmx_mio_uartx_dll_s cn52xx; 1220 struct cvmx_mio_uartx_dll_s cn52xxp1; 1221 struct cvmx_mio_uartx_dll_s cn56xx; 1222 struct cvmx_mio_uartx_dll_s cn56xxp1; 1223 struct cvmx_mio_uartx_dll_s cn58xx; 1224 struct cvmx_mio_uartx_dll_s cn58xxp1; 1225}; 1226 1227union cvmx_mio_uartx_far { 1228 uint64_t u64; 1229 struct cvmx_mio_uartx_far_s { 1230 uint64_t reserved_1_63:63; 1231 uint64_t far:1; 1232 } s; 1233 struct cvmx_mio_uartx_far_s cn30xx; 1234 struct cvmx_mio_uartx_far_s cn31xx; 1235 struct cvmx_mio_uartx_far_s cn38xx; 1236 struct cvmx_mio_uartx_far_s cn38xxp2; 1237 struct cvmx_mio_uartx_far_s cn50xx; 1238 struct cvmx_mio_uartx_far_s cn52xx; 1239 struct cvmx_mio_uartx_far_s cn52xxp1; 1240 struct cvmx_mio_uartx_far_s cn56xx; 1241 struct cvmx_mio_uartx_far_s cn56xxp1; 1242 struct cvmx_mio_uartx_far_s cn58xx; 1243 struct cvmx_mio_uartx_far_s cn58xxp1; 1244}; 1245 1246union cvmx_mio_uartx_fcr { 1247 uint64_t u64; 1248 struct cvmx_mio_uartx_fcr_s { 1249 uint64_t reserved_8_63:56; 1250 uint64_t rxtrig:2; 1251 uint64_t txtrig:2; 1252 uint64_t reserved_3_3:1; 1253 uint64_t txfr:1; 1254 uint64_t rxfr:1; 1255 uint64_t en:1; 1256 } s; 1257 struct cvmx_mio_uartx_fcr_s cn30xx; 1258 struct cvmx_mio_uartx_fcr_s cn31xx; 1259 struct cvmx_mio_uartx_fcr_s cn38xx; 1260 struct cvmx_mio_uartx_fcr_s cn38xxp2; 1261 struct cvmx_mio_uartx_fcr_s cn50xx; 1262 struct cvmx_mio_uartx_fcr_s cn52xx; 1263 struct cvmx_mio_uartx_fcr_s cn52xxp1; 1264 struct cvmx_mio_uartx_fcr_s cn56xx; 1265 struct cvmx_mio_uartx_fcr_s cn56xxp1; 1266 struct cvmx_mio_uartx_fcr_s cn58xx; 1267 struct cvmx_mio_uartx_fcr_s cn58xxp1; 1268}; 1269 1270union cvmx_mio_uartx_htx { 1271 uint64_t u64; 1272 struct cvmx_mio_uartx_htx_s { 1273 uint64_t reserved_1_63:63; 1274 uint64_t htx:1; 1275 } s; 1276 struct cvmx_mio_uartx_htx_s cn30xx; 1277 struct cvmx_mio_uartx_htx_s cn31xx; 1278 struct cvmx_mio_uartx_htx_s cn38xx; 1279 struct cvmx_mio_uartx_htx_s cn38xxp2; 1280 struct cvmx_mio_uartx_htx_s cn50xx; 1281 struct cvmx_mio_uartx_htx_s cn52xx; 1282 struct cvmx_mio_uartx_htx_s cn52xxp1; 1283 struct cvmx_mio_uartx_htx_s cn56xx; 1284 struct cvmx_mio_uartx_htx_s cn56xxp1; 1285 struct cvmx_mio_uartx_htx_s cn58xx; 1286 struct cvmx_mio_uartx_htx_s cn58xxp1; 1287}; 1288 1289union cvmx_mio_uartx_ier { 1290 uint64_t u64; 1291 struct cvmx_mio_uartx_ier_s { 1292 uint64_t reserved_8_63:56; 1293 uint64_t ptime:1; 1294 uint64_t reserved_4_6:3; 1295 uint64_t edssi:1; 1296 uint64_t elsi:1; 1297 uint64_t etbei:1; 1298 uint64_t erbfi:1; 1299 } s; 1300 struct cvmx_mio_uartx_ier_s cn30xx; 1301 struct cvmx_mio_uartx_ier_s cn31xx; 1302 struct cvmx_mio_uartx_ier_s cn38xx; 1303 struct cvmx_mio_uartx_ier_s cn38xxp2; 1304 struct cvmx_mio_uartx_ier_s cn50xx; 1305 struct cvmx_mio_uartx_ier_s cn52xx; 1306 struct cvmx_mio_uartx_ier_s cn52xxp1; 1307 struct cvmx_mio_uartx_ier_s cn56xx; 1308 struct cvmx_mio_uartx_ier_s cn56xxp1; 1309 struct cvmx_mio_uartx_ier_s cn58xx; 1310 struct cvmx_mio_uartx_ier_s cn58xxp1; 1311}; 1312 1313union cvmx_mio_uartx_iir { 1314 uint64_t u64; 1315 struct cvmx_mio_uartx_iir_s { 1316 uint64_t reserved_8_63:56; 1317 uint64_t fen:2; 1318 uint64_t reserved_4_5:2; 1319 uint64_t iid:4; 1320 } s; 1321 struct cvmx_mio_uartx_iir_s cn30xx; 1322 struct cvmx_mio_uartx_iir_s cn31xx; 1323 struct cvmx_mio_uartx_iir_s cn38xx; 1324 struct cvmx_mio_uartx_iir_s cn38xxp2; 1325 struct cvmx_mio_uartx_iir_s cn50xx; 1326 struct cvmx_mio_uartx_iir_s cn52xx; 1327 struct cvmx_mio_uartx_iir_s cn52xxp1; 1328 struct cvmx_mio_uartx_iir_s cn56xx; 1329 struct cvmx_mio_uartx_iir_s cn56xxp1; 1330 struct cvmx_mio_uartx_iir_s cn58xx; 1331 struct cvmx_mio_uartx_iir_s cn58xxp1; 1332}; 1333 1334union cvmx_mio_uartx_lcr { 1335 uint64_t u64; 1336 struct cvmx_mio_uartx_lcr_s { 1337 uint64_t reserved_8_63:56; 1338 uint64_t dlab:1; 1339 uint64_t brk:1; 1340 uint64_t reserved_5_5:1; 1341 uint64_t eps:1; 1342 uint64_t pen:1; 1343 uint64_t stop:1; 1344 uint64_t cls:2; 1345 } s; 1346 struct cvmx_mio_uartx_lcr_s cn30xx; 1347 struct cvmx_mio_uartx_lcr_s cn31xx; 1348 struct cvmx_mio_uartx_lcr_s cn38xx; 1349 struct cvmx_mio_uartx_lcr_s cn38xxp2; 1350 struct cvmx_mio_uartx_lcr_s cn50xx; 1351 struct cvmx_mio_uartx_lcr_s cn52xx; 1352 struct cvmx_mio_uartx_lcr_s cn52xxp1; 1353 struct cvmx_mio_uartx_lcr_s cn56xx; 1354 struct cvmx_mio_uartx_lcr_s cn56xxp1; 1355 struct cvmx_mio_uartx_lcr_s cn58xx; 1356 struct cvmx_mio_uartx_lcr_s cn58xxp1; 1357}; 1358 1359union cvmx_mio_uartx_lsr { 1360 uint64_t u64; 1361 struct cvmx_mio_uartx_lsr_s { 1362 uint64_t reserved_8_63:56; 1363 uint64_t ferr:1; 1364 uint64_t temt:1; 1365 uint64_t thre:1; 1366 uint64_t bi:1; 1367 uint64_t fe:1; 1368 uint64_t pe:1; 1369 uint64_t oe:1; 1370 uint64_t dr:1; 1371 } s; 1372 struct cvmx_mio_uartx_lsr_s cn30xx; 1373 struct cvmx_mio_uartx_lsr_s cn31xx; 1374 struct cvmx_mio_uartx_lsr_s cn38xx; 1375 struct cvmx_mio_uartx_lsr_s cn38xxp2; 1376 struct cvmx_mio_uartx_lsr_s cn50xx; 1377 struct cvmx_mio_uartx_lsr_s cn52xx; 1378 struct cvmx_mio_uartx_lsr_s cn52xxp1; 1379 struct cvmx_mio_uartx_lsr_s cn56xx; 1380 struct cvmx_mio_uartx_lsr_s cn56xxp1; 1381 struct cvmx_mio_uartx_lsr_s cn58xx; 1382 struct cvmx_mio_uartx_lsr_s cn58xxp1; 1383}; 1384 1385union cvmx_mio_uartx_mcr { 1386 uint64_t u64; 1387 struct cvmx_mio_uartx_mcr_s { 1388 uint64_t reserved_6_63:58; 1389 uint64_t afce:1; 1390 uint64_t loop:1; 1391 uint64_t out2:1; 1392 uint64_t out1:1; 1393 uint64_t rts:1; 1394 uint64_t dtr:1; 1395 } s; 1396 struct cvmx_mio_uartx_mcr_s cn30xx; 1397 struct cvmx_mio_uartx_mcr_s cn31xx; 1398 struct cvmx_mio_uartx_mcr_s cn38xx; 1399 struct cvmx_mio_uartx_mcr_s cn38xxp2; 1400 struct cvmx_mio_uartx_mcr_s cn50xx; 1401 struct cvmx_mio_uartx_mcr_s cn52xx; 1402 struct cvmx_mio_uartx_mcr_s cn52xxp1; 1403 struct cvmx_mio_uartx_mcr_s cn56xx; 1404 struct cvmx_mio_uartx_mcr_s cn56xxp1; 1405 struct cvmx_mio_uartx_mcr_s cn58xx; 1406 struct cvmx_mio_uartx_mcr_s cn58xxp1; 1407}; 1408 1409union cvmx_mio_uartx_msr { 1410 uint64_t u64; 1411 struct cvmx_mio_uartx_msr_s { 1412 uint64_t reserved_8_63:56; 1413 uint64_t dcd:1; 1414 uint64_t ri:1; 1415 uint64_t dsr:1; 1416 uint64_t cts:1; 1417 uint64_t ddcd:1; 1418 uint64_t teri:1; 1419 uint64_t ddsr:1; 1420 uint64_t dcts:1; 1421 } s; 1422 struct cvmx_mio_uartx_msr_s cn30xx; 1423 struct cvmx_mio_uartx_msr_s cn31xx; 1424 struct cvmx_mio_uartx_msr_s cn38xx; 1425 struct cvmx_mio_uartx_msr_s cn38xxp2; 1426 struct cvmx_mio_uartx_msr_s cn50xx; 1427 struct cvmx_mio_uartx_msr_s cn52xx; 1428 struct cvmx_mio_uartx_msr_s cn52xxp1; 1429 struct cvmx_mio_uartx_msr_s cn56xx; 1430 struct cvmx_mio_uartx_msr_s cn56xxp1; 1431 struct cvmx_mio_uartx_msr_s cn58xx; 1432 struct cvmx_mio_uartx_msr_s cn58xxp1; 1433}; 1434 1435union cvmx_mio_uartx_rbr { 1436 uint64_t u64; 1437 struct cvmx_mio_uartx_rbr_s { 1438 uint64_t reserved_8_63:56; 1439 uint64_t rbr:8; 1440 } s; 1441 struct cvmx_mio_uartx_rbr_s cn30xx; 1442 struct cvmx_mio_uartx_rbr_s cn31xx; 1443 struct cvmx_mio_uartx_rbr_s cn38xx; 1444 struct cvmx_mio_uartx_rbr_s cn38xxp2; 1445 struct cvmx_mio_uartx_rbr_s cn50xx; 1446 struct cvmx_mio_uartx_rbr_s cn52xx; 1447 struct cvmx_mio_uartx_rbr_s cn52xxp1; 1448 struct cvmx_mio_uartx_rbr_s cn56xx; 1449 struct cvmx_mio_uartx_rbr_s cn56xxp1; 1450 struct cvmx_mio_uartx_rbr_s cn58xx; 1451 struct cvmx_mio_uartx_rbr_s cn58xxp1; 1452}; 1453 1454union cvmx_mio_uartx_rfl { 1455 uint64_t u64; 1456 struct cvmx_mio_uartx_rfl_s { 1457 uint64_t reserved_7_63:57; 1458 uint64_t rfl:7; 1459 } s; 1460 struct cvmx_mio_uartx_rfl_s cn30xx; 1461 struct cvmx_mio_uartx_rfl_s cn31xx; 1462 struct cvmx_mio_uartx_rfl_s cn38xx; 1463 struct cvmx_mio_uartx_rfl_s cn38xxp2; 1464 struct cvmx_mio_uartx_rfl_s cn50xx; 1465 struct cvmx_mio_uartx_rfl_s cn52xx; 1466 struct cvmx_mio_uartx_rfl_s cn52xxp1; 1467 struct cvmx_mio_uartx_rfl_s cn56xx; 1468 struct cvmx_mio_uartx_rfl_s cn56xxp1; 1469 struct cvmx_mio_uartx_rfl_s cn58xx; 1470 struct cvmx_mio_uartx_rfl_s cn58xxp1; 1471}; 1472 1473union cvmx_mio_uartx_rfw { 1474 uint64_t u64; 1475 struct cvmx_mio_uartx_rfw_s { 1476 uint64_t reserved_10_63:54; 1477 uint64_t rffe:1; 1478 uint64_t rfpe:1; 1479 uint64_t rfwd:8; 1480 } s; 1481 struct cvmx_mio_uartx_rfw_s cn30xx; 1482 struct cvmx_mio_uartx_rfw_s cn31xx; 1483 struct cvmx_mio_uartx_rfw_s cn38xx; 1484 struct cvmx_mio_uartx_rfw_s cn38xxp2; 1485 struct cvmx_mio_uartx_rfw_s cn50xx; 1486 struct cvmx_mio_uartx_rfw_s cn52xx; 1487 struct cvmx_mio_uartx_rfw_s cn52xxp1; 1488 struct cvmx_mio_uartx_rfw_s cn56xx; 1489 struct cvmx_mio_uartx_rfw_s cn56xxp1; 1490 struct cvmx_mio_uartx_rfw_s cn58xx; 1491 struct cvmx_mio_uartx_rfw_s cn58xxp1; 1492}; 1493 1494union cvmx_mio_uartx_sbcr { 1495 uint64_t u64; 1496 struct cvmx_mio_uartx_sbcr_s { 1497 uint64_t reserved_1_63:63; 1498 uint64_t sbcr:1; 1499 } s; 1500 struct cvmx_mio_uartx_sbcr_s cn30xx; 1501 struct cvmx_mio_uartx_sbcr_s cn31xx; 1502 struct cvmx_mio_uartx_sbcr_s cn38xx; 1503 struct cvmx_mio_uartx_sbcr_s cn38xxp2; 1504 struct cvmx_mio_uartx_sbcr_s cn50xx; 1505 struct cvmx_mio_uartx_sbcr_s cn52xx; 1506 struct cvmx_mio_uartx_sbcr_s cn52xxp1; 1507 struct cvmx_mio_uartx_sbcr_s cn56xx; 1508 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 1509 struct cvmx_mio_uartx_sbcr_s cn58xx; 1510 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 1511}; 1512 1513union cvmx_mio_uartx_scr { 1514 uint64_t u64; 1515 struct cvmx_mio_uartx_scr_s { 1516 uint64_t reserved_8_63:56; 1517 uint64_t scr:8; 1518 } s; 1519 struct cvmx_mio_uartx_scr_s cn30xx; 1520 struct cvmx_mio_uartx_scr_s cn31xx; 1521 struct cvmx_mio_uartx_scr_s cn38xx; 1522 struct cvmx_mio_uartx_scr_s cn38xxp2; 1523 struct cvmx_mio_uartx_scr_s cn50xx; 1524 struct cvmx_mio_uartx_scr_s cn52xx; 1525 struct cvmx_mio_uartx_scr_s cn52xxp1; 1526 struct cvmx_mio_uartx_scr_s cn56xx; 1527 struct cvmx_mio_uartx_scr_s cn56xxp1; 1528 struct cvmx_mio_uartx_scr_s cn58xx; 1529 struct cvmx_mio_uartx_scr_s cn58xxp1; 1530}; 1531 1532union cvmx_mio_uartx_sfe { 1533 uint64_t u64; 1534 struct cvmx_mio_uartx_sfe_s { 1535 uint64_t reserved_1_63:63; 1536 uint64_t sfe:1; 1537 } s; 1538 struct cvmx_mio_uartx_sfe_s cn30xx; 1539 struct cvmx_mio_uartx_sfe_s cn31xx; 1540 struct cvmx_mio_uartx_sfe_s cn38xx; 1541 struct cvmx_mio_uartx_sfe_s cn38xxp2; 1542 struct cvmx_mio_uartx_sfe_s cn50xx; 1543 struct cvmx_mio_uartx_sfe_s cn52xx; 1544 struct cvmx_mio_uartx_sfe_s cn52xxp1; 1545 struct cvmx_mio_uartx_sfe_s cn56xx; 1546 struct cvmx_mio_uartx_sfe_s cn56xxp1; 1547 struct cvmx_mio_uartx_sfe_s cn58xx; 1548 struct cvmx_mio_uartx_sfe_s cn58xxp1; 1549}; 1550 1551union cvmx_mio_uartx_srr { 1552 uint64_t u64; 1553 struct cvmx_mio_uartx_srr_s { 1554 uint64_t reserved_3_63:61; 1555 uint64_t stfr:1; 1556 uint64_t srfr:1; 1557 uint64_t usr:1; 1558 } s; 1559 struct cvmx_mio_uartx_srr_s cn30xx; 1560 struct cvmx_mio_uartx_srr_s cn31xx; 1561 struct cvmx_mio_uartx_srr_s cn38xx; 1562 struct cvmx_mio_uartx_srr_s cn38xxp2; 1563 struct cvmx_mio_uartx_srr_s cn50xx; 1564 struct cvmx_mio_uartx_srr_s cn52xx; 1565 struct cvmx_mio_uartx_srr_s cn52xxp1; 1566 struct cvmx_mio_uartx_srr_s cn56xx; 1567 struct cvmx_mio_uartx_srr_s cn56xxp1; 1568 struct cvmx_mio_uartx_srr_s cn58xx; 1569 struct cvmx_mio_uartx_srr_s cn58xxp1; 1570}; 1571 1572union cvmx_mio_uartx_srt { 1573 uint64_t u64; 1574 struct cvmx_mio_uartx_srt_s { 1575 uint64_t reserved_2_63:62; 1576 uint64_t srt:2; 1577 } s; 1578 struct cvmx_mio_uartx_srt_s cn30xx; 1579 struct cvmx_mio_uartx_srt_s cn31xx; 1580 struct cvmx_mio_uartx_srt_s cn38xx; 1581 struct cvmx_mio_uartx_srt_s cn38xxp2; 1582 struct cvmx_mio_uartx_srt_s cn50xx; 1583 struct cvmx_mio_uartx_srt_s cn52xx; 1584 struct cvmx_mio_uartx_srt_s cn52xxp1; 1585 struct cvmx_mio_uartx_srt_s cn56xx; 1586 struct cvmx_mio_uartx_srt_s cn56xxp1; 1587 struct cvmx_mio_uartx_srt_s cn58xx; 1588 struct cvmx_mio_uartx_srt_s cn58xxp1; 1589}; 1590 1591union cvmx_mio_uartx_srts { 1592 uint64_t u64; 1593 struct cvmx_mio_uartx_srts_s { 1594 uint64_t reserved_1_63:63; 1595 uint64_t srts:1; 1596 } s; 1597 struct cvmx_mio_uartx_srts_s cn30xx; 1598 struct cvmx_mio_uartx_srts_s cn31xx; 1599 struct cvmx_mio_uartx_srts_s cn38xx; 1600 struct cvmx_mio_uartx_srts_s cn38xxp2; 1601 struct cvmx_mio_uartx_srts_s cn50xx; 1602 struct cvmx_mio_uartx_srts_s cn52xx; 1603 struct cvmx_mio_uartx_srts_s cn52xxp1; 1604 struct cvmx_mio_uartx_srts_s cn56xx; 1605 struct cvmx_mio_uartx_srts_s cn56xxp1; 1606 struct cvmx_mio_uartx_srts_s cn58xx; 1607 struct cvmx_mio_uartx_srts_s cn58xxp1; 1608}; 1609 1610union cvmx_mio_uartx_stt { 1611 uint64_t u64; 1612 struct cvmx_mio_uartx_stt_s { 1613 uint64_t reserved_2_63:62; 1614 uint64_t stt:2; 1615 } s; 1616 struct cvmx_mio_uartx_stt_s cn30xx; 1617 struct cvmx_mio_uartx_stt_s cn31xx; 1618 struct cvmx_mio_uartx_stt_s cn38xx; 1619 struct cvmx_mio_uartx_stt_s cn38xxp2; 1620 struct cvmx_mio_uartx_stt_s cn50xx; 1621 struct cvmx_mio_uartx_stt_s cn52xx; 1622 struct cvmx_mio_uartx_stt_s cn52xxp1; 1623 struct cvmx_mio_uartx_stt_s cn56xx; 1624 struct cvmx_mio_uartx_stt_s cn56xxp1; 1625 struct cvmx_mio_uartx_stt_s cn58xx; 1626 struct cvmx_mio_uartx_stt_s cn58xxp1; 1627}; 1628 1629union cvmx_mio_uartx_tfl { 1630 uint64_t u64; 1631 struct cvmx_mio_uartx_tfl_s { 1632 uint64_t reserved_7_63:57; 1633 uint64_t tfl:7; 1634 } s; 1635 struct cvmx_mio_uartx_tfl_s cn30xx; 1636 struct cvmx_mio_uartx_tfl_s cn31xx; 1637 struct cvmx_mio_uartx_tfl_s cn38xx; 1638 struct cvmx_mio_uartx_tfl_s cn38xxp2; 1639 struct cvmx_mio_uartx_tfl_s cn50xx; 1640 struct cvmx_mio_uartx_tfl_s cn52xx; 1641 struct cvmx_mio_uartx_tfl_s cn52xxp1; 1642 struct cvmx_mio_uartx_tfl_s cn56xx; 1643 struct cvmx_mio_uartx_tfl_s cn56xxp1; 1644 struct cvmx_mio_uartx_tfl_s cn58xx; 1645 struct cvmx_mio_uartx_tfl_s cn58xxp1; 1646}; 1647 1648union cvmx_mio_uartx_tfr { 1649 uint64_t u64; 1650 struct cvmx_mio_uartx_tfr_s { 1651 uint64_t reserved_8_63:56; 1652 uint64_t tfr:8; 1653 } s; 1654 struct cvmx_mio_uartx_tfr_s cn30xx; 1655 struct cvmx_mio_uartx_tfr_s cn31xx; 1656 struct cvmx_mio_uartx_tfr_s cn38xx; 1657 struct cvmx_mio_uartx_tfr_s cn38xxp2; 1658 struct cvmx_mio_uartx_tfr_s cn50xx; 1659 struct cvmx_mio_uartx_tfr_s cn52xx; 1660 struct cvmx_mio_uartx_tfr_s cn52xxp1; 1661 struct cvmx_mio_uartx_tfr_s cn56xx; 1662 struct cvmx_mio_uartx_tfr_s cn56xxp1; 1663 struct cvmx_mio_uartx_tfr_s cn58xx; 1664 struct cvmx_mio_uartx_tfr_s cn58xxp1; 1665}; 1666 1667union cvmx_mio_uartx_thr { 1668 uint64_t u64; 1669 struct cvmx_mio_uartx_thr_s { 1670 uint64_t reserved_8_63:56; 1671 uint64_t thr:8; 1672 } s; 1673 struct cvmx_mio_uartx_thr_s cn30xx; 1674 struct cvmx_mio_uartx_thr_s cn31xx; 1675 struct cvmx_mio_uartx_thr_s cn38xx; 1676 struct cvmx_mio_uartx_thr_s cn38xxp2; 1677 struct cvmx_mio_uartx_thr_s cn50xx; 1678 struct cvmx_mio_uartx_thr_s cn52xx; 1679 struct cvmx_mio_uartx_thr_s cn52xxp1; 1680 struct cvmx_mio_uartx_thr_s cn56xx; 1681 struct cvmx_mio_uartx_thr_s cn56xxp1; 1682 struct cvmx_mio_uartx_thr_s cn58xx; 1683 struct cvmx_mio_uartx_thr_s cn58xxp1; 1684}; 1685 1686union cvmx_mio_uartx_usr { 1687 uint64_t u64; 1688 struct cvmx_mio_uartx_usr_s { 1689 uint64_t reserved_5_63:59; 1690 uint64_t rff:1; 1691 uint64_t rfne:1; 1692 uint64_t tfe:1; 1693 uint64_t tfnf:1; 1694 uint64_t busy:1; 1695 } s; 1696 struct cvmx_mio_uartx_usr_s cn30xx; 1697 struct cvmx_mio_uartx_usr_s cn31xx; 1698 struct cvmx_mio_uartx_usr_s cn38xx; 1699 struct cvmx_mio_uartx_usr_s cn38xxp2; 1700 struct cvmx_mio_uartx_usr_s cn50xx; 1701 struct cvmx_mio_uartx_usr_s cn52xx; 1702 struct cvmx_mio_uartx_usr_s cn52xxp1; 1703 struct cvmx_mio_uartx_usr_s cn56xx; 1704 struct cvmx_mio_uartx_usr_s cn56xxp1; 1705 struct cvmx_mio_uartx_usr_s cn58xx; 1706 struct cvmx_mio_uartx_usr_s cn58xxp1; 1707}; 1708 1709union cvmx_mio_uart2_dlh { 1710 uint64_t u64; 1711 struct cvmx_mio_uart2_dlh_s { 1712 uint64_t reserved_8_63:56; 1713 uint64_t dlh:8; 1714 } s; 1715 struct cvmx_mio_uart2_dlh_s cn52xx; 1716 struct cvmx_mio_uart2_dlh_s cn52xxp1; 1717}; 1718 1719union cvmx_mio_uart2_dll { 1720 uint64_t u64; 1721 struct cvmx_mio_uart2_dll_s { 1722 uint64_t reserved_8_63:56; 1723 uint64_t dll:8; 1724 } s; 1725 struct cvmx_mio_uart2_dll_s cn52xx; 1726 struct cvmx_mio_uart2_dll_s cn52xxp1; 1727}; 1728 1729union cvmx_mio_uart2_far { 1730 uint64_t u64; 1731 struct cvmx_mio_uart2_far_s { 1732 uint64_t reserved_1_63:63; 1733 uint64_t far:1; 1734 } s; 1735 struct cvmx_mio_uart2_far_s cn52xx; 1736 struct cvmx_mio_uart2_far_s cn52xxp1; 1737}; 1738 1739union cvmx_mio_uart2_fcr { 1740 uint64_t u64; 1741 struct cvmx_mio_uart2_fcr_s { 1742 uint64_t reserved_8_63:56; 1743 uint64_t rxtrig:2; 1744 uint64_t txtrig:2; 1745 uint64_t reserved_3_3:1; 1746 uint64_t txfr:1; 1747 uint64_t rxfr:1; 1748 uint64_t en:1; 1749 } s; 1750 struct cvmx_mio_uart2_fcr_s cn52xx; 1751 struct cvmx_mio_uart2_fcr_s cn52xxp1; 1752}; 1753 1754union cvmx_mio_uart2_htx { 1755 uint64_t u64; 1756 struct cvmx_mio_uart2_htx_s { 1757 uint64_t reserved_1_63:63; 1758 uint64_t htx:1; 1759 } s; 1760 struct cvmx_mio_uart2_htx_s cn52xx; 1761 struct cvmx_mio_uart2_htx_s cn52xxp1; 1762}; 1763 1764union cvmx_mio_uart2_ier { 1765 uint64_t u64; 1766 struct cvmx_mio_uart2_ier_s { 1767 uint64_t reserved_8_63:56; 1768 uint64_t ptime:1; 1769 uint64_t reserved_4_6:3; 1770 uint64_t edssi:1; 1771 uint64_t elsi:1; 1772 uint64_t etbei:1; 1773 uint64_t erbfi:1; 1774 } s; 1775 struct cvmx_mio_uart2_ier_s cn52xx; 1776 struct cvmx_mio_uart2_ier_s cn52xxp1; 1777}; 1778 1779union cvmx_mio_uart2_iir { 1780 uint64_t u64; 1781 struct cvmx_mio_uart2_iir_s { 1782 uint64_t reserved_8_63:56; 1783 uint64_t fen:2; 1784 uint64_t reserved_4_5:2; 1785 uint64_t iid:4; 1786 } s; 1787 struct cvmx_mio_uart2_iir_s cn52xx; 1788 struct cvmx_mio_uart2_iir_s cn52xxp1; 1789}; 1790 1791union cvmx_mio_uart2_lcr { 1792 uint64_t u64; 1793 struct cvmx_mio_uart2_lcr_s { 1794 uint64_t reserved_8_63:56; 1795 uint64_t dlab:1; 1796 uint64_t brk:1; 1797 uint64_t reserved_5_5:1; 1798 uint64_t eps:1; 1799 uint64_t pen:1; 1800 uint64_t stop:1; 1801 uint64_t cls:2; 1802 } s; 1803 struct cvmx_mio_uart2_lcr_s cn52xx; 1804 struct cvmx_mio_uart2_lcr_s cn52xxp1; 1805}; 1806 1807union cvmx_mio_uart2_lsr { 1808 uint64_t u64; 1809 struct cvmx_mio_uart2_lsr_s { 1810 uint64_t reserved_8_63:56; 1811 uint64_t ferr:1; 1812 uint64_t temt:1; 1813 uint64_t thre:1; 1814 uint64_t bi:1; 1815 uint64_t fe:1; 1816 uint64_t pe:1; 1817 uint64_t oe:1; 1818 uint64_t dr:1; 1819 } s; 1820 struct cvmx_mio_uart2_lsr_s cn52xx; 1821 struct cvmx_mio_uart2_lsr_s cn52xxp1; 1822}; 1823 1824union cvmx_mio_uart2_mcr { 1825 uint64_t u64; 1826 struct cvmx_mio_uart2_mcr_s { 1827 uint64_t reserved_6_63:58; 1828 uint64_t afce:1; 1829 uint64_t loop:1; 1830 uint64_t out2:1; 1831 uint64_t out1:1; 1832 uint64_t rts:1; 1833 uint64_t dtr:1; 1834 } s; 1835 struct cvmx_mio_uart2_mcr_s cn52xx; 1836 struct cvmx_mio_uart2_mcr_s cn52xxp1; 1837}; 1838 1839union cvmx_mio_uart2_msr { 1840 uint64_t u64; 1841 struct cvmx_mio_uart2_msr_s { 1842 uint64_t reserved_8_63:56; 1843 uint64_t dcd:1; 1844 uint64_t ri:1; 1845 uint64_t dsr:1; 1846 uint64_t cts:1; 1847 uint64_t ddcd:1; 1848 uint64_t teri:1; 1849 uint64_t ddsr:1; 1850 uint64_t dcts:1; 1851 } s; 1852 struct cvmx_mio_uart2_msr_s cn52xx; 1853 struct cvmx_mio_uart2_msr_s cn52xxp1; 1854}; 1855 1856union cvmx_mio_uart2_rbr { 1857 uint64_t u64; 1858 struct cvmx_mio_uart2_rbr_s { 1859 uint64_t reserved_8_63:56; 1860 uint64_t rbr:8; 1861 } s; 1862 struct cvmx_mio_uart2_rbr_s cn52xx; 1863 struct cvmx_mio_uart2_rbr_s cn52xxp1; 1864}; 1865 1866union cvmx_mio_uart2_rfl { 1867 uint64_t u64; 1868 struct cvmx_mio_uart2_rfl_s { 1869 uint64_t reserved_7_63:57; 1870 uint64_t rfl:7; 1871 } s; 1872 struct cvmx_mio_uart2_rfl_s cn52xx; 1873 struct cvmx_mio_uart2_rfl_s cn52xxp1; 1874}; 1875 1876union cvmx_mio_uart2_rfw { 1877 uint64_t u64; 1878 struct cvmx_mio_uart2_rfw_s { 1879 uint64_t reserved_10_63:54; 1880 uint64_t rffe:1; 1881 uint64_t rfpe:1; 1882 uint64_t rfwd:8; 1883 } s; 1884 struct cvmx_mio_uart2_rfw_s cn52xx; 1885 struct cvmx_mio_uart2_rfw_s cn52xxp1; 1886}; 1887 1888union cvmx_mio_uart2_sbcr { 1889 uint64_t u64; 1890 struct cvmx_mio_uart2_sbcr_s { 1891 uint64_t reserved_1_63:63; 1892 uint64_t sbcr:1; 1893 } s; 1894 struct cvmx_mio_uart2_sbcr_s cn52xx; 1895 struct cvmx_mio_uart2_sbcr_s cn52xxp1; 1896}; 1897 1898union cvmx_mio_uart2_scr { 1899 uint64_t u64; 1900 struct cvmx_mio_uart2_scr_s { 1901 uint64_t reserved_8_63:56; 1902 uint64_t scr:8; 1903 } s; 1904 struct cvmx_mio_uart2_scr_s cn52xx; 1905 struct cvmx_mio_uart2_scr_s cn52xxp1; 1906}; 1907 1908union cvmx_mio_uart2_sfe { 1909 uint64_t u64; 1910 struct cvmx_mio_uart2_sfe_s { 1911 uint64_t reserved_1_63:63; 1912 uint64_t sfe:1; 1913 } s; 1914 struct cvmx_mio_uart2_sfe_s cn52xx; 1915 struct cvmx_mio_uart2_sfe_s cn52xxp1; 1916}; 1917 1918union cvmx_mio_uart2_srr { 1919 uint64_t u64; 1920 struct cvmx_mio_uart2_srr_s { 1921 uint64_t reserved_3_63:61; 1922 uint64_t stfr:1; 1923 uint64_t srfr:1; 1924 uint64_t usr:1; 1925 } s; 1926 struct cvmx_mio_uart2_srr_s cn52xx; 1927 struct cvmx_mio_uart2_srr_s cn52xxp1; 1928}; 1929 1930union cvmx_mio_uart2_srt { 1931 uint64_t u64; 1932 struct cvmx_mio_uart2_srt_s { 1933 uint64_t reserved_2_63:62; 1934 uint64_t srt:2; 1935 } s; 1936 struct cvmx_mio_uart2_srt_s cn52xx; 1937 struct cvmx_mio_uart2_srt_s cn52xxp1; 1938}; 1939 1940union cvmx_mio_uart2_srts { 1941 uint64_t u64; 1942 struct cvmx_mio_uart2_srts_s { 1943 uint64_t reserved_1_63:63; 1944 uint64_t srts:1; 1945 } s; 1946 struct cvmx_mio_uart2_srts_s cn52xx; 1947 struct cvmx_mio_uart2_srts_s cn52xxp1; 1948}; 1949 1950union cvmx_mio_uart2_stt { 1951 uint64_t u64; 1952 struct cvmx_mio_uart2_stt_s { 1953 uint64_t reserved_2_63:62; 1954 uint64_t stt:2; 1955 } s; 1956 struct cvmx_mio_uart2_stt_s cn52xx; 1957 struct cvmx_mio_uart2_stt_s cn52xxp1; 1958}; 1959 1960union cvmx_mio_uart2_tfl { 1961 uint64_t u64; 1962 struct cvmx_mio_uart2_tfl_s { 1963 uint64_t reserved_7_63:57; 1964 uint64_t tfl:7; 1965 } s; 1966 struct cvmx_mio_uart2_tfl_s cn52xx; 1967 struct cvmx_mio_uart2_tfl_s cn52xxp1; 1968}; 1969 1970union cvmx_mio_uart2_tfr { 1971 uint64_t u64; 1972 struct cvmx_mio_uart2_tfr_s { 1973 uint64_t reserved_8_63:56; 1974 uint64_t tfr:8; 1975 } s; 1976 struct cvmx_mio_uart2_tfr_s cn52xx; 1977 struct cvmx_mio_uart2_tfr_s cn52xxp1; 1978}; 1979 1980union cvmx_mio_uart2_thr { 1981 uint64_t u64; 1982 struct cvmx_mio_uart2_thr_s { 1983 uint64_t reserved_8_63:56; 1984 uint64_t thr:8; 1985 } s; 1986 struct cvmx_mio_uart2_thr_s cn52xx; 1987 struct cvmx_mio_uart2_thr_s cn52xxp1; 1988}; 1989 1990union cvmx_mio_uart2_usr { 1991 uint64_t u64; 1992 struct cvmx_mio_uart2_usr_s { 1993 uint64_t reserved_5_63:59; 1994 uint64_t rff:1; 1995 uint64_t rfne:1; 1996 uint64_t tfe:1; 1997 uint64_t tfnf:1; 1998 uint64_t busy:1; 1999 } s; 2000 struct cvmx_mio_uart2_usr_s cn52xx;
2001 struct cvmx_mio_uart2_usr_s cn52xxp1; 2002}; 2003 2004#endif 2005