1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_PCIERCX_DEFS_H__ 29#define __CVMX_PCIERCX_DEFS_H__ 30 31#define CVMX_PCIERCX_CFG000(offset) \ 32 (0x0000000000000000ull + (((offset) & 1) * 0)) 33#define CVMX_PCIERCX_CFG001(offset) \ 34 (0x0000000000000004ull + (((offset) & 1) * 0)) 35#define CVMX_PCIERCX_CFG002(offset) \ 36 (0x0000000000000008ull + (((offset) & 1) * 0)) 37#define CVMX_PCIERCX_CFG003(offset) \ 38 (0x000000000000000Cull + (((offset) & 1) * 0)) 39#define CVMX_PCIERCX_CFG004(offset) \ 40 (0x0000000000000010ull + (((offset) & 1) * 0)) 41#define CVMX_PCIERCX_CFG005(offset) \ 42 (0x0000000000000014ull + (((offset) & 1) * 0)) 43#define CVMX_PCIERCX_CFG006(offset) \ 44 (0x0000000000000018ull + (((offset) & 1) * 0)) 45#define CVMX_PCIERCX_CFG007(offset) \ 46 (0x000000000000001Cull + (((offset) & 1) * 0)) 47#define CVMX_PCIERCX_CFG008(offset) \ 48 (0x0000000000000020ull + (((offset) & 1) * 0)) 49#define CVMX_PCIERCX_CFG009(offset) \ 50 (0x0000000000000024ull + (((offset) & 1) * 0)) 51#define CVMX_PCIERCX_CFG010(offset) \ 52 (0x0000000000000028ull + (((offset) & 1) * 0)) 53#define CVMX_PCIERCX_CFG011(offset) \ 54 (0x000000000000002Cull + (((offset) & 1) * 0)) 55#define CVMX_PCIERCX_CFG012(offset) \ 56 (0x0000000000000030ull + (((offset) & 1) * 0)) 57#define CVMX_PCIERCX_CFG013(offset) \ 58 (0x0000000000000034ull + (((offset) & 1) * 0)) 59#define CVMX_PCIERCX_CFG014(offset) \ 60 (0x0000000000000038ull + (((offset) & 1) * 0)) 61#define CVMX_PCIERCX_CFG015(offset) \ 62 (0x000000000000003Cull + (((offset) & 1) * 0)) 63#define CVMX_PCIERCX_CFG016(offset) \ 64 (0x0000000000000040ull + (((offset) & 1) * 0)) 65#define CVMX_PCIERCX_CFG017(offset) \ 66 (0x0000000000000044ull + (((offset) & 1) * 0)) 67#define CVMX_PCIERCX_CFG020(offset) \ 68 (0x0000000000000050ull + (((offset) & 1) * 0)) 69#define CVMX_PCIERCX_CFG021(offset) \ 70 (0x0000000000000054ull + (((offset) & 1) * 0)) 71#define CVMX_PCIERCX_CFG022(offset) \ 72 (0x0000000000000058ull + (((offset) & 1) * 0)) 73#define CVMX_PCIERCX_CFG023(offset) \ 74 (0x000000000000005Cull + (((offset) & 1) * 0)) 75#define CVMX_PCIERCX_CFG028(offset) \ 76 (0x0000000000000070ull + (((offset) & 1) * 0)) 77#define CVMX_PCIERCX_CFG029(offset) \ 78 (0x0000000000000074ull + (((offset) & 1) * 0)) 79#define CVMX_PCIERCX_CFG030(offset) \ 80 (0x0000000000000078ull + (((offset) & 1) * 0)) 81#define CVMX_PCIERCX_CFG031(offset) \ 82 (0x000000000000007Cull + (((offset) & 1) * 0)) 83#define CVMX_PCIERCX_CFG032(offset) \ 84 (0x0000000000000080ull + (((offset) & 1) * 0)) 85#define CVMX_PCIERCX_CFG033(offset) \ 86 (0x0000000000000084ull + (((offset) & 1) * 0)) 87#define CVMX_PCIERCX_CFG034(offset) \ 88 (0x0000000000000088ull + (((offset) & 1) * 0)) 89#define CVMX_PCIERCX_CFG035(offset) \ 90 (0x000000000000008Cull + (((offset) & 1) * 0)) 91#define CVMX_PCIERCX_CFG036(offset) \ 92 (0x0000000000000090ull + (((offset) & 1) * 0)) 93#define CVMX_PCIERCX_CFG037(offset) \ 94 (0x0000000000000094ull + (((offset) & 1) * 0)) 95#define CVMX_PCIERCX_CFG038(offset) \ 96 (0x0000000000000098ull + (((offset) & 1) * 0)) 97#define CVMX_PCIERCX_CFG039(offset) \ 98 (0x000000000000009Cull + (((offset) & 1) * 0)) 99#define CVMX_PCIERCX_CFG040(offset) \ 100 (0x00000000000000A0ull + (((offset) & 1) * 0)) 101#define CVMX_PCIERCX_CFG041(offset) \ 102 (0x00000000000000A4ull + (((offset) & 1) * 0)) 103#define CVMX_PCIERCX_CFG042(offset) \ 104 (0x00000000000000A8ull + (((offset) & 1) * 0)) 105#define CVMX_PCIERCX_CFG064(offset) \ 106 (0x0000000000000100ull + (((offset) & 1) * 0)) 107#define CVMX_PCIERCX_CFG065(offset) \ 108 (0x0000000000000104ull + (((offset) & 1) * 0)) 109#define CVMX_PCIERCX_CFG066(offset) \ 110 (0x0000000000000108ull + (((offset) & 1) * 0)) 111#define CVMX_PCIERCX_CFG067(offset) \ 112 (0x000000000000010Cull + (((offset) & 1) * 0)) 113#define CVMX_PCIERCX_CFG068(offset) \ 114 (0x0000000000000110ull + (((offset) & 1) * 0)) 115#define CVMX_PCIERCX_CFG069(offset) \ 116 (0x0000000000000114ull + (((offset) & 1) * 0)) 117#define CVMX_PCIERCX_CFG070(offset) \ 118 (0x0000000000000118ull + (((offset) & 1) * 0)) 119#define CVMX_PCIERCX_CFG071(offset) \ 120 (0x000000000000011Cull + (((offset) & 1) * 0)) 121#define CVMX_PCIERCX_CFG072(offset) \ 122 (0x0000000000000120ull + (((offset) & 1) * 0)) 123#define CVMX_PCIERCX_CFG073(offset) \ 124 (0x0000000000000124ull + (((offset) & 1) * 0)) 125#define CVMX_PCIERCX_CFG074(offset) \ 126 (0x0000000000000128ull + (((offset) & 1) * 0)) 127#define CVMX_PCIERCX_CFG075(offset) \ 128 (0x000000000000012Cull + (((offset) & 1) * 0)) 129#define CVMX_PCIERCX_CFG076(offset) \ 130 (0x0000000000000130ull + (((offset) & 1) * 0)) 131#define CVMX_PCIERCX_CFG077(offset) \ 132 (0x0000000000000134ull + (((offset) & 1) * 0)) 133#define CVMX_PCIERCX_CFG448(offset) \ 134 (0x0000000000000700ull + (((offset) & 1) * 0)) 135#define CVMX_PCIERCX_CFG449(offset) \ 136 (0x0000000000000704ull + (((offset) & 1) * 0)) 137#define CVMX_PCIERCX_CFG450(offset) \ 138 (0x0000000000000708ull + (((offset) & 1) * 0)) 139#define CVMX_PCIERCX_CFG451(offset) \ 140 (0x000000000000070Cull + (((offset) & 1) * 0)) 141#define CVMX_PCIERCX_CFG452(offset) \ 142 (0x0000000000000710ull + (((offset) & 1) * 0)) 143#define CVMX_PCIERCX_CFG453(offset) \ 144 (0x0000000000000714ull + (((offset) & 1) * 0)) 145#define CVMX_PCIERCX_CFG454(offset) \ 146 (0x0000000000000718ull + (((offset) & 1) * 0)) 147#define CVMX_PCIERCX_CFG455(offset) \ 148 (0x000000000000071Cull + (((offset) & 1) * 0)) 149#define CVMX_PCIERCX_CFG456(offset) \ 150 (0x0000000000000720ull + (((offset) & 1) * 0)) 151#define CVMX_PCIERCX_CFG458(offset) \ 152 (0x0000000000000728ull + (((offset) & 1) * 0)) 153#define CVMX_PCIERCX_CFG459(offset) \ 154 (0x000000000000072Cull + (((offset) & 1) * 0)) 155#define CVMX_PCIERCX_CFG460(offset) \ 156 (0x0000000000000730ull + (((offset) & 1) * 0)) 157#define CVMX_PCIERCX_CFG461(offset) \ 158 (0x0000000000000734ull + (((offset) & 1) * 0)) 159#define CVMX_PCIERCX_CFG462(offset) \ 160 (0x0000000000000738ull + (((offset) & 1) * 0)) 161#define CVMX_PCIERCX_CFG463(offset) \ 162 (0x000000000000073Cull + (((offset) & 1) * 0)) 163#define CVMX_PCIERCX_CFG464(offset) \ 164 (0x0000000000000740ull + (((offset) & 1) * 0)) 165#define CVMX_PCIERCX_CFG465(offset) \ 166 (0x0000000000000744ull + (((offset) & 1) * 0)) 167#define CVMX_PCIERCX_CFG466(offset) \ 168 (0x0000000000000748ull + (((offset) & 1) * 0)) 169#define CVMX_PCIERCX_CFG467(offset) \ 170 (0x000000000000074Cull + (((offset) & 1) * 0)) 171#define CVMX_PCIERCX_CFG468(offset) \ 172 (0x0000000000000750ull + (((offset) & 1) * 0)) 173#define CVMX_PCIERCX_CFG490(offset) \ 174 (0x00000000000007A8ull + (((offset) & 1) * 0)) 175#define CVMX_PCIERCX_CFG491(offset) \ 176 (0x00000000000007ACull + (((offset) & 1) * 0)) 177#define CVMX_PCIERCX_CFG492(offset) \ 178 (0x00000000000007B0ull + (((offset) & 1) * 0)) 179#define CVMX_PCIERCX_CFG516(offset) \ 180 (0x0000000000000810ull + (((offset) & 1) * 0)) 181#define CVMX_PCIERCX_CFG517(offset) \ 182 (0x0000000000000814ull + (((offset) & 1) * 0)) 183 184union cvmx_pciercx_cfg000 { 185 uint32_t u32; 186 struct cvmx_pciercx_cfg000_s { 187 uint32_t devid:16; 188 uint32_t vendid:16; 189 } s; 190 struct cvmx_pciercx_cfg000_s cn52xx; 191 struct cvmx_pciercx_cfg000_s cn52xxp1; 192 struct cvmx_pciercx_cfg000_s cn56xx; 193 struct cvmx_pciercx_cfg000_s cn56xxp1; 194}; 195 196union cvmx_pciercx_cfg001 { 197 uint32_t u32; 198 struct cvmx_pciercx_cfg001_s { 199 uint32_t dpe:1; 200 uint32_t sse:1; 201 uint32_t rma:1; 202 uint32_t rta:1; 203 uint32_t sta:1; 204 uint32_t devt:2; 205 uint32_t mdpe:1; 206 uint32_t fbb:1; 207 uint32_t reserved_22_22:1; 208 uint32_t m66:1; 209 uint32_t cl:1; 210 uint32_t i_stat:1; 211 uint32_t reserved_11_18:8; 212 uint32_t i_dis:1; 213 uint32_t fbbe:1; 214 uint32_t see:1; 215 uint32_t ids_wcc:1; 216 uint32_t per:1; 217 uint32_t vps:1; 218 uint32_t mwice:1; 219 uint32_t scse:1; 220 uint32_t me:1; 221 uint32_t msae:1; 222 uint32_t isae:1; 223 } s; 224 struct cvmx_pciercx_cfg001_s cn52xx; 225 struct cvmx_pciercx_cfg001_s cn52xxp1; 226 struct cvmx_pciercx_cfg001_s cn56xx; 227 struct cvmx_pciercx_cfg001_s cn56xxp1; 228}; 229 230union cvmx_pciercx_cfg002 { 231 uint32_t u32; 232 struct cvmx_pciercx_cfg002_s { 233 uint32_t bcc:8; 234 uint32_t sc:8; 235 uint32_t pi:8; 236 uint32_t rid:8; 237 } s; 238 struct cvmx_pciercx_cfg002_s cn52xx; 239 struct cvmx_pciercx_cfg002_s cn52xxp1; 240 struct cvmx_pciercx_cfg002_s cn56xx; 241 struct cvmx_pciercx_cfg002_s cn56xxp1; 242}; 243 244union cvmx_pciercx_cfg003 { 245 uint32_t u32; 246 struct cvmx_pciercx_cfg003_s { 247 uint32_t bist:8; 248 uint32_t mfd:1; 249 uint32_t chf:7; 250 uint32_t lt:8; 251 uint32_t cls:8; 252 } s; 253 struct cvmx_pciercx_cfg003_s cn52xx; 254 struct cvmx_pciercx_cfg003_s cn52xxp1; 255 struct cvmx_pciercx_cfg003_s cn56xx; 256 struct cvmx_pciercx_cfg003_s cn56xxp1; 257}; 258 259union cvmx_pciercx_cfg004 { 260 uint32_t u32; 261 struct cvmx_pciercx_cfg004_s { 262 uint32_t reserved_0_31:32; 263 } s; 264 struct cvmx_pciercx_cfg004_s cn52xx; 265 struct cvmx_pciercx_cfg004_s cn52xxp1; 266 struct cvmx_pciercx_cfg004_s cn56xx; 267 struct cvmx_pciercx_cfg004_s cn56xxp1; 268}; 269 270union cvmx_pciercx_cfg005 { 271 uint32_t u32; 272 struct cvmx_pciercx_cfg005_s { 273 uint32_t reserved_0_31:32; 274 } s; 275 struct cvmx_pciercx_cfg005_s cn52xx; 276 struct cvmx_pciercx_cfg005_s cn52xxp1; 277 struct cvmx_pciercx_cfg005_s cn56xx; 278 struct cvmx_pciercx_cfg005_s cn56xxp1; 279}; 280 281union cvmx_pciercx_cfg006 { 282 uint32_t u32; 283 struct cvmx_pciercx_cfg006_s { 284 uint32_t slt:8; 285 uint32_t subbnum:8; 286 uint32_t sbnum:8; 287 uint32_t pbnum:8; 288 } s; 289 struct cvmx_pciercx_cfg006_s cn52xx; 290 struct cvmx_pciercx_cfg006_s cn52xxp1; 291 struct cvmx_pciercx_cfg006_s cn56xx; 292 struct cvmx_pciercx_cfg006_s cn56xxp1; 293}; 294 295union cvmx_pciercx_cfg007 { 296 uint32_t u32; 297 struct cvmx_pciercx_cfg007_s { 298 uint32_t dpe:1; 299 uint32_t sse:1; 300 uint32_t rma:1; 301 uint32_t rta:1; 302 uint32_t sta:1; 303 uint32_t devt:2; 304 uint32_t mdpe:1; 305 uint32_t fbb:1; 306 uint32_t reserved_22_22:1; 307 uint32_t m66:1; 308 uint32_t reserved_16_20:5; 309 uint32_t lio_limi:4; 310 uint32_t reserved_9_11:3; 311 uint32_t io32b:1; 312 uint32_t lio_base:4; 313 uint32_t reserved_1_3:3; 314 uint32_t io32a:1; 315 } s; 316 struct cvmx_pciercx_cfg007_s cn52xx; 317 struct cvmx_pciercx_cfg007_s cn52xxp1; 318 struct cvmx_pciercx_cfg007_s cn56xx; 319 struct cvmx_pciercx_cfg007_s cn56xxp1; 320}; 321 322union cvmx_pciercx_cfg008 { 323 uint32_t u32; 324 struct cvmx_pciercx_cfg008_s { 325 uint32_t ml_addr:12; 326 uint32_t reserved_16_19:4; 327 uint32_t mb_addr:12; 328 uint32_t reserved_0_3:4; 329 } s; 330 struct cvmx_pciercx_cfg008_s cn52xx; 331 struct cvmx_pciercx_cfg008_s cn52xxp1; 332 struct cvmx_pciercx_cfg008_s cn56xx; 333 struct cvmx_pciercx_cfg008_s cn56xxp1; 334}; 335 336union cvmx_pciercx_cfg009 { 337 uint32_t u32; 338 struct cvmx_pciercx_cfg009_s { 339 uint32_t lmem_limit:12; 340 uint32_t reserved_17_19:3; 341 uint32_t mem64b:1; 342 uint32_t lmem_base:12; 343 uint32_t reserved_1_3:3; 344 uint32_t mem64a:1; 345 } s; 346 struct cvmx_pciercx_cfg009_s cn52xx; 347 struct cvmx_pciercx_cfg009_s cn52xxp1; 348 struct cvmx_pciercx_cfg009_s cn56xx; 349 struct cvmx_pciercx_cfg009_s cn56xxp1; 350}; 351 352union cvmx_pciercx_cfg010 { 353 uint32_t u32; 354 struct cvmx_pciercx_cfg010_s { 355 uint32_t umem_base:32; 356 } s; 357 struct cvmx_pciercx_cfg010_s cn52xx; 358 struct cvmx_pciercx_cfg010_s cn52xxp1; 359 struct cvmx_pciercx_cfg010_s cn56xx; 360 struct cvmx_pciercx_cfg010_s cn56xxp1; 361}; 362 363union cvmx_pciercx_cfg011 { 364 uint32_t u32; 365 struct cvmx_pciercx_cfg011_s { 366 uint32_t umem_limit:32; 367 } s; 368 struct cvmx_pciercx_cfg011_s cn52xx; 369 struct cvmx_pciercx_cfg011_s cn52xxp1; 370 struct cvmx_pciercx_cfg011_s cn56xx; 371 struct cvmx_pciercx_cfg011_s cn56xxp1; 372}; 373 374union cvmx_pciercx_cfg012 { 375 uint32_t u32; 376 struct cvmx_pciercx_cfg012_s { 377 uint32_t uio_limit:16; 378 uint32_t uio_base:16; 379 } s; 380 struct cvmx_pciercx_cfg012_s cn52xx; 381 struct cvmx_pciercx_cfg012_s cn52xxp1; 382 struct cvmx_pciercx_cfg012_s cn56xx; 383 struct cvmx_pciercx_cfg012_s cn56xxp1; 384}; 385 386union cvmx_pciercx_cfg013 { 387 uint32_t u32; 388 struct cvmx_pciercx_cfg013_s { 389 uint32_t reserved_8_31:24; 390 uint32_t cp:8; 391 } s; 392 struct cvmx_pciercx_cfg013_s cn52xx; 393 struct cvmx_pciercx_cfg013_s cn52xxp1; 394 struct cvmx_pciercx_cfg013_s cn56xx; 395 struct cvmx_pciercx_cfg013_s cn56xxp1; 396}; 397 398union cvmx_pciercx_cfg014 { 399 uint32_t u32; 400 struct cvmx_pciercx_cfg014_s { 401 uint32_t reserved_0_31:32; 402 } s; 403 struct cvmx_pciercx_cfg014_s cn52xx; 404 struct cvmx_pciercx_cfg014_s cn52xxp1; 405 struct cvmx_pciercx_cfg014_s cn56xx; 406 struct cvmx_pciercx_cfg014_s cn56xxp1; 407}; 408 409union cvmx_pciercx_cfg015 { 410 uint32_t u32; 411 struct cvmx_pciercx_cfg015_s { 412 uint32_t reserved_28_31:4; 413 uint32_t dtsees:1; 414 uint32_t dts:1; 415 uint32_t sdt:1; 416 uint32_t pdt:1; 417 uint32_t fbbe:1; 418 uint32_t sbrst:1; 419 uint32_t mam:1; 420 uint32_t vga16d:1; 421 uint32_t vgae:1; 422 uint32_t isae:1; 423 uint32_t see:1; 424 uint32_t pere:1; 425 uint32_t inta:8; 426 uint32_t il:8; 427 } s; 428 struct cvmx_pciercx_cfg015_s cn52xx; 429 struct cvmx_pciercx_cfg015_s cn52xxp1; 430 struct cvmx_pciercx_cfg015_s cn56xx; 431 struct cvmx_pciercx_cfg015_s cn56xxp1; 432}; 433 434union cvmx_pciercx_cfg016 { 435 uint32_t u32; 436 struct cvmx_pciercx_cfg016_s { 437 uint32_t pmes:5; 438 uint32_t d2s:1; 439 uint32_t d1s:1; 440 uint32_t auxc:3; 441 uint32_t dsi:1; 442 uint32_t reserved_20_20:1; 443 uint32_t pme_clock:1; 444 uint32_t pmsv:3; 445 uint32_t ncp:8; 446 uint32_t pmcid:8; 447 } s; 448 struct cvmx_pciercx_cfg016_s cn52xx; 449 struct cvmx_pciercx_cfg016_s cn52xxp1; 450 struct cvmx_pciercx_cfg016_s cn56xx; 451 struct cvmx_pciercx_cfg016_s cn56xxp1; 452}; 453 454union cvmx_pciercx_cfg017 { 455 uint32_t u32; 456 struct cvmx_pciercx_cfg017_s { 457 uint32_t pmdia:8; 458 uint32_t bpccee:1; 459 uint32_t bd3h:1; 460 uint32_t reserved_16_21:6; 461 uint32_t pmess:1; 462 uint32_t pmedsia:2; 463 uint32_t pmds:4; 464 uint32_t pmeens:1; 465 uint32_t reserved_4_7:4; 466 uint32_t nsr:1; 467 uint32_t reserved_2_2:1; 468 uint32_t ps:2; 469 } s; 470 struct cvmx_pciercx_cfg017_s cn52xx; 471 struct cvmx_pciercx_cfg017_s cn52xxp1; 472 struct cvmx_pciercx_cfg017_s cn56xx; 473 struct cvmx_pciercx_cfg017_s cn56xxp1; 474}; 475 476union cvmx_pciercx_cfg020 { 477 uint32_t u32; 478 struct cvmx_pciercx_cfg020_s { 479 uint32_t reserved_24_31:8; 480 uint32_t m64:1; 481 uint32_t mme:3; 482 uint32_t mmc:3; 483 uint32_t msien:1; 484 uint32_t ncp:8; 485 uint32_t msicid:8; 486 } s; 487 struct cvmx_pciercx_cfg020_s cn52xx; 488 struct cvmx_pciercx_cfg020_s cn52xxp1; 489 struct cvmx_pciercx_cfg020_s cn56xx; 490 struct cvmx_pciercx_cfg020_s cn56xxp1; 491}; 492 493union cvmx_pciercx_cfg021 { 494 uint32_t u32; 495 struct cvmx_pciercx_cfg021_s { 496 uint32_t lmsi:30; 497 uint32_t reserved_0_1:2; 498 } s; 499 struct cvmx_pciercx_cfg021_s cn52xx; 500 struct cvmx_pciercx_cfg021_s cn52xxp1; 501 struct cvmx_pciercx_cfg021_s cn56xx; 502 struct cvmx_pciercx_cfg021_s cn56xxp1; 503}; 504 505union cvmx_pciercx_cfg022 { 506 uint32_t u32; 507 struct cvmx_pciercx_cfg022_s { 508 uint32_t umsi:32; 509 } s; 510 struct cvmx_pciercx_cfg022_s cn52xx; 511 struct cvmx_pciercx_cfg022_s cn52xxp1; 512 struct cvmx_pciercx_cfg022_s cn56xx; 513 struct cvmx_pciercx_cfg022_s cn56xxp1; 514}; 515 516union cvmx_pciercx_cfg023 { 517 uint32_t u32; 518 struct cvmx_pciercx_cfg023_s { 519 uint32_t reserved_16_31:16; 520 uint32_t msimd:16; 521 } s; 522 struct cvmx_pciercx_cfg023_s cn52xx; 523 struct cvmx_pciercx_cfg023_s cn52xxp1; 524 struct cvmx_pciercx_cfg023_s cn56xx; 525 struct cvmx_pciercx_cfg023_s cn56xxp1; 526}; 527 528union cvmx_pciercx_cfg028 { 529 uint32_t u32; 530 struct cvmx_pciercx_cfg028_s { 531 uint32_t reserved_30_31:2; 532 uint32_t imn:5; 533 uint32_t si:1; 534 uint32_t dpt:4; 535 uint32_t pciecv:4; 536 uint32_t ncp:8; 537 uint32_t pcieid:8; 538 } s; 539 struct cvmx_pciercx_cfg028_s cn52xx; 540 struct cvmx_pciercx_cfg028_s cn52xxp1; 541 struct cvmx_pciercx_cfg028_s cn56xx; 542 struct cvmx_pciercx_cfg028_s cn56xxp1; 543}; 544 545union cvmx_pciercx_cfg029 { 546 uint32_t u32; 547 struct cvmx_pciercx_cfg029_s { 548 uint32_t reserved_28_31:4; 549 uint32_t cspls:2; 550 uint32_t csplv:8; 551 uint32_t reserved_16_17:2; 552 uint32_t rber:1; 553 uint32_t reserved_12_14:3; 554 uint32_t el1al:3; 555 uint32_t el0al:3; 556 uint32_t etfs:1; 557 uint32_t pfs:2; 558 uint32_t mpss:3; 559 } s; 560 struct cvmx_pciercx_cfg029_s cn52xx; 561 struct cvmx_pciercx_cfg029_s cn52xxp1; 562 struct cvmx_pciercx_cfg029_s cn56xx; 563 struct cvmx_pciercx_cfg029_s cn56xxp1; 564}; 565 566union cvmx_pciercx_cfg030 { 567 uint32_t u32; 568 struct cvmx_pciercx_cfg030_s { 569 uint32_t reserved_22_31:10; 570 uint32_t tp:1; 571 uint32_t ap_d:1; 572 uint32_t ur_d:1; 573 uint32_t fe_d:1; 574 uint32_t nfe_d:1; 575 uint32_t ce_d:1; 576 uint32_t reserved_15_15:1; 577 uint32_t mrrs:3; 578 uint32_t ns_en:1; 579 uint32_t ap_en:1; 580 uint32_t pf_en:1; 581 uint32_t etf_en:1; 582 uint32_t mps:3; 583 uint32_t ro_en:1; 584 uint32_t ur_en:1; 585 uint32_t fe_en:1; 586 uint32_t nfe_en:1; 587 uint32_t ce_en:1; 588 } s; 589 struct cvmx_pciercx_cfg030_s cn52xx; 590 struct cvmx_pciercx_cfg030_s cn52xxp1; 591 struct cvmx_pciercx_cfg030_s cn56xx; 592 struct cvmx_pciercx_cfg030_s cn56xxp1; 593}; 594 595union cvmx_pciercx_cfg031 { 596 uint32_t u32; 597 struct cvmx_pciercx_cfg031_s { 598 uint32_t pnum:8; 599 uint32_t reserved_22_23:2; 600 uint32_t lbnc:1; 601 uint32_t dllarc:1; 602 uint32_t sderc:1; 603 uint32_t cpm:1; 604 uint32_t l1el:3; 605 uint32_t l0el:3; 606 uint32_t aslpms:2; 607 uint32_t mlw:6; 608 uint32_t mls:4; 609 } s; 610 struct cvmx_pciercx_cfg031_s cn52xx; 611 struct cvmx_pciercx_cfg031_s cn52xxp1; 612 struct cvmx_pciercx_cfg031_s cn56xx; 613 struct cvmx_pciercx_cfg031_s cn56xxp1; 614}; 615 616union cvmx_pciercx_cfg032 { 617 uint32_t u32; 618 struct cvmx_pciercx_cfg032_s { 619 uint32_t lab:1; 620 uint32_t lbm:1; 621 uint32_t dlla:1; 622 uint32_t scc:1; 623 uint32_t lt:1; 624 uint32_t reserved_26_26:1; 625 uint32_t nlw:6; 626 uint32_t ls:4; 627 uint32_t reserved_12_15:4; 628 uint32_t lab_int_enb:1; 629 uint32_t lbm_int_enb:1; 630 uint32_t hawd:1; 631 uint32_t ecpm:1; 632 uint32_t es:1; 633 uint32_t ccc:1; 634 uint32_t rl:1; 635 uint32_t ld:1; 636 uint32_t rcb:1; 637 uint32_t reserved_2_2:1; 638 uint32_t aslpc:2; 639 } s; 640 struct cvmx_pciercx_cfg032_s cn52xx; 641 struct cvmx_pciercx_cfg032_s cn52xxp1; 642 struct cvmx_pciercx_cfg032_s cn56xx; 643 struct cvmx_pciercx_cfg032_s cn56xxp1; 644}; 645 646union cvmx_pciercx_cfg033 { 647 uint32_t u32; 648 struct cvmx_pciercx_cfg033_s { 649 uint32_t ps_num:13; 650 uint32_t nccs:1; 651 uint32_t emip:1; 652 uint32_t sp_ls:2; 653 uint32_t sp_lv:8; 654 uint32_t hp_c:1; 655 uint32_t hp_s:1; 656 uint32_t pip:1; 657 uint32_t aip:1; 658 uint32_t mrlsp:1; 659 uint32_t pcp:1; 660 uint32_t abp:1; 661 } s; 662 struct cvmx_pciercx_cfg033_s cn52xx; 663 struct cvmx_pciercx_cfg033_s cn52xxp1; 664 struct cvmx_pciercx_cfg033_s cn56xx; 665 struct cvmx_pciercx_cfg033_s cn56xxp1; 666}; 667 668union cvmx_pciercx_cfg034 { 669 uint32_t u32; 670 struct cvmx_pciercx_cfg034_s { 671 uint32_t reserved_25_31:7; 672 uint32_t dlls_c:1; 673 uint32_t emis:1; 674 uint32_t pds:1; 675 uint32_t mrlss:1; 676 uint32_t ccint_d:1; 677 uint32_t pd_c:1; 678 uint32_t mrls_c:1; 679 uint32_t pf_d:1; 680 uint32_t abp_d:1; 681 uint32_t reserved_13_15:3; 682 uint32_t dlls_en:1; 683 uint32_t emic:1; 684 uint32_t pcc:1; 685 uint32_t pic:2; 686 uint32_t aic:2; 687 uint32_t hpint_en:1; 688 uint32_t ccint_en:1; 689 uint32_t pd_en:1; 690 uint32_t mrls_en:1; 691 uint32_t pf_en:1; 692 uint32_t abp_en:1; 693 } s; 694 struct cvmx_pciercx_cfg034_s cn52xx; 695 struct cvmx_pciercx_cfg034_s cn52xxp1; 696 struct cvmx_pciercx_cfg034_s cn56xx; 697 struct cvmx_pciercx_cfg034_s cn56xxp1; 698}; 699 700union cvmx_pciercx_cfg035 { 701 uint32_t u32; 702 struct cvmx_pciercx_cfg035_s { 703 uint32_t reserved_17_31:15; 704 uint32_t crssv:1; 705 uint32_t reserved_5_15:11; 706 uint32_t crssve:1; 707 uint32_t pmeie:1; 708 uint32_t sefee:1; 709 uint32_t senfee:1; 710 uint32_t secee:1; 711 } s; 712 struct cvmx_pciercx_cfg035_s cn52xx; 713 struct cvmx_pciercx_cfg035_s cn52xxp1; 714 struct cvmx_pciercx_cfg035_s cn56xx; 715 struct cvmx_pciercx_cfg035_s cn56xxp1; 716}; 717 718union cvmx_pciercx_cfg036 { 719 uint32_t u32; 720 struct cvmx_pciercx_cfg036_s { 721 uint32_t reserved_18_31:14; 722 uint32_t pme_pend:1; 723 uint32_t pme_stat:1; 724 uint32_t pme_rid:16; 725 } s; 726 struct cvmx_pciercx_cfg036_s cn52xx; 727 struct cvmx_pciercx_cfg036_s cn52xxp1; 728 struct cvmx_pciercx_cfg036_s cn56xx; 729 struct cvmx_pciercx_cfg036_s cn56xxp1; 730}; 731 732union cvmx_pciercx_cfg037 { 733 uint32_t u32; 734 struct cvmx_pciercx_cfg037_s { 735 uint32_t reserved_5_31:27; 736 uint32_t ctds:1; 737 uint32_t ctrs:4; 738 } s; 739 struct cvmx_pciercx_cfg037_s cn52xx; 740 struct cvmx_pciercx_cfg037_s cn52xxp1; 741 struct cvmx_pciercx_cfg037_s cn56xx; 742 struct cvmx_pciercx_cfg037_s cn56xxp1; 743}; 744 745union cvmx_pciercx_cfg038 { 746 uint32_t u32; 747 struct cvmx_pciercx_cfg038_s { 748 uint32_t reserved_5_31:27; 749 uint32_t ctd:1; 750 uint32_t ctv:4; 751 } s; 752 struct cvmx_pciercx_cfg038_s cn52xx; 753 struct cvmx_pciercx_cfg038_s cn52xxp1; 754 struct cvmx_pciercx_cfg038_s cn56xx; 755 struct cvmx_pciercx_cfg038_s cn56xxp1; 756}; 757 758union cvmx_pciercx_cfg039 { 759 uint32_t u32; 760 struct cvmx_pciercx_cfg039_s { 761 uint32_t reserved_0_31:32; 762 } s; 763 struct cvmx_pciercx_cfg039_s cn52xx; 764 struct cvmx_pciercx_cfg039_s cn52xxp1; 765 struct cvmx_pciercx_cfg039_s cn56xx; 766 struct cvmx_pciercx_cfg039_s cn56xxp1; 767}; 768 769union cvmx_pciercx_cfg040 { 770 uint32_t u32; 771 struct cvmx_pciercx_cfg040_s { 772 uint32_t reserved_0_31:32; 773 } s; 774 struct cvmx_pciercx_cfg040_s cn52xx; 775 struct cvmx_pciercx_cfg040_s cn52xxp1; 776 struct cvmx_pciercx_cfg040_s cn56xx; 777 struct cvmx_pciercx_cfg040_s cn56xxp1; 778}; 779 780union cvmx_pciercx_cfg041 { 781 uint32_t u32; 782 struct cvmx_pciercx_cfg041_s { 783 uint32_t reserved_0_31:32; 784 } s; 785 struct cvmx_pciercx_cfg041_s cn52xx; 786 struct cvmx_pciercx_cfg041_s cn52xxp1; 787 struct cvmx_pciercx_cfg041_s cn56xx; 788 struct cvmx_pciercx_cfg041_s cn56xxp1; 789}; 790 791union cvmx_pciercx_cfg042 { 792 uint32_t u32; 793 struct cvmx_pciercx_cfg042_s { 794 uint32_t reserved_0_31:32; 795 } s; 796 struct cvmx_pciercx_cfg042_s cn52xx; 797 struct cvmx_pciercx_cfg042_s cn52xxp1; 798 struct cvmx_pciercx_cfg042_s cn56xx; 799 struct cvmx_pciercx_cfg042_s cn56xxp1; 800}; 801 802union cvmx_pciercx_cfg064 { 803 uint32_t u32; 804 struct cvmx_pciercx_cfg064_s { 805 uint32_t nco:12; 806 uint32_t cv:4; 807 uint32_t pcieec:16; 808 } s; 809 struct cvmx_pciercx_cfg064_s cn52xx; 810 struct cvmx_pciercx_cfg064_s cn52xxp1; 811 struct cvmx_pciercx_cfg064_s cn56xx; 812 struct cvmx_pciercx_cfg064_s cn56xxp1; 813}; 814 815union cvmx_pciercx_cfg065 { 816 uint32_t u32; 817 struct cvmx_pciercx_cfg065_s { 818 uint32_t reserved_21_31:11; 819 uint32_t ures:1; 820 uint32_t ecrces:1; 821 uint32_t mtlps:1; 822 uint32_t ros:1; 823 uint32_t ucs:1; 824 uint32_t cas:1; 825 uint32_t cts:1; 826 uint32_t fcpes:1; 827 uint32_t ptlps:1; 828 uint32_t reserved_6_11:6; 829 uint32_t sdes:1; 830 uint32_t dlpes:1; 831 uint32_t reserved_0_3:4; 832 } s; 833 struct cvmx_pciercx_cfg065_s cn52xx; 834 struct cvmx_pciercx_cfg065_s cn52xxp1; 835 struct cvmx_pciercx_cfg065_s cn56xx; 836 struct cvmx_pciercx_cfg065_s cn56xxp1; 837}; 838 839union cvmx_pciercx_cfg066 { 840 uint32_t u32; 841 struct cvmx_pciercx_cfg066_s { 842 uint32_t reserved_21_31:11; 843 uint32_t urem:1; 844 uint32_t ecrcem:1; 845 uint32_t mtlpm:1; 846 uint32_t rom:1; 847 uint32_t ucm:1; 848 uint32_t cam:1; 849 uint32_t ctm:1; 850 uint32_t fcpem:1; 851 uint32_t ptlpm:1; 852 uint32_t reserved_6_11:6; 853 uint32_t sdem:1; 854 uint32_t dlpem:1; 855 uint32_t reserved_0_3:4; 856 } s; 857 struct cvmx_pciercx_cfg066_s cn52xx; 858 struct cvmx_pciercx_cfg066_s cn52xxp1; 859 struct cvmx_pciercx_cfg066_s cn56xx; 860 struct cvmx_pciercx_cfg066_s cn56xxp1; 861}; 862 863union cvmx_pciercx_cfg067 { 864 uint32_t u32; 865 struct cvmx_pciercx_cfg067_s { 866 uint32_t reserved_21_31:11; 867 uint32_t ures:1; 868 uint32_t ecrces:1; 869 uint32_t mtlps:1; 870 uint32_t ros:1; 871 uint32_t ucs:1; 872 uint32_t cas:1; 873 uint32_t cts:1; 874 uint32_t fcpes:1; 875 uint32_t ptlps:1; 876 uint32_t reserved_6_11:6; 877 uint32_t sdes:1; 878 uint32_t dlpes:1; 879 uint32_t reserved_0_3:4; 880 } s; 881 struct cvmx_pciercx_cfg067_s cn52xx; 882 struct cvmx_pciercx_cfg067_s cn52xxp1; 883 struct cvmx_pciercx_cfg067_s cn56xx; 884 struct cvmx_pciercx_cfg067_s cn56xxp1; 885}; 886 887union cvmx_pciercx_cfg068 { 888 uint32_t u32; 889 struct cvmx_pciercx_cfg068_s { 890 uint32_t reserved_14_31:18; 891 uint32_t anfes:1; 892 uint32_t rtts:1; 893 uint32_t reserved_9_11:3; 894 uint32_t rnrs:1; 895 uint32_t bdllps:1; 896 uint32_t btlps:1; 897 uint32_t reserved_1_5:5; 898 uint32_t res:1; 899 } s; 900 struct cvmx_pciercx_cfg068_s cn52xx; 901 struct cvmx_pciercx_cfg068_s cn52xxp1; 902 struct cvmx_pciercx_cfg068_s cn56xx; 903 struct cvmx_pciercx_cfg068_s cn56xxp1; 904}; 905 906union cvmx_pciercx_cfg069 { 907 uint32_t u32; 908 struct cvmx_pciercx_cfg069_s { 909 uint32_t reserved_14_31:18; 910 uint32_t anfem:1; 911 uint32_t rttm:1; 912 uint32_t reserved_9_11:3; 913 uint32_t rnrm:1; 914 uint32_t bdllpm:1; 915 uint32_t btlpm:1; 916 uint32_t reserved_1_5:5; 917 uint32_t rem:1; 918 } s; 919 struct cvmx_pciercx_cfg069_s cn52xx; 920 struct cvmx_pciercx_cfg069_s cn52xxp1; 921 struct cvmx_pciercx_cfg069_s cn56xx; 922 struct cvmx_pciercx_cfg069_s cn56xxp1; 923}; 924 925union cvmx_pciercx_cfg070 { 926 uint32_t u32; 927 struct cvmx_pciercx_cfg070_s { 928 uint32_t reserved_9_31:23; 929 uint32_t ce:1; 930 uint32_t cc:1; 931 uint32_t ge:1; 932 uint32_t gc:1; 933 uint32_t fep:5; 934 } s; 935 struct cvmx_pciercx_cfg070_s cn52xx; 936 struct cvmx_pciercx_cfg070_s cn52xxp1; 937 struct cvmx_pciercx_cfg070_s cn56xx; 938 struct cvmx_pciercx_cfg070_s cn56xxp1; 939}; 940 941union cvmx_pciercx_cfg071 { 942 uint32_t u32; 943 struct cvmx_pciercx_cfg071_s { 944 uint32_t dword1:32; 945 } s; 946 struct cvmx_pciercx_cfg071_s cn52xx; 947 struct cvmx_pciercx_cfg071_s cn52xxp1; 948 struct cvmx_pciercx_cfg071_s cn56xx; 949 struct cvmx_pciercx_cfg071_s cn56xxp1; 950}; 951 952union cvmx_pciercx_cfg072 { 953 uint32_t u32; 954 struct cvmx_pciercx_cfg072_s { 955 uint32_t dword2:32; 956 } s; 957 struct cvmx_pciercx_cfg072_s cn52xx; 958 struct cvmx_pciercx_cfg072_s cn52xxp1; 959 struct cvmx_pciercx_cfg072_s cn56xx; 960 struct cvmx_pciercx_cfg072_s cn56xxp1; 961}; 962 963union cvmx_pciercx_cfg073 { 964 uint32_t u32; 965 struct cvmx_pciercx_cfg073_s { 966 uint32_t dword3:32; 967 } s; 968 struct cvmx_pciercx_cfg073_s cn52xx; 969 struct cvmx_pciercx_cfg073_s cn52xxp1; 970 struct cvmx_pciercx_cfg073_s cn56xx; 971 struct cvmx_pciercx_cfg073_s cn56xxp1; 972}; 973 974union cvmx_pciercx_cfg074 { 975 uint32_t u32; 976 struct cvmx_pciercx_cfg074_s { 977 uint32_t dword4:32; 978 } s; 979 struct cvmx_pciercx_cfg074_s cn52xx; 980 struct cvmx_pciercx_cfg074_s cn52xxp1; 981 struct cvmx_pciercx_cfg074_s cn56xx; 982 struct cvmx_pciercx_cfg074_s cn56xxp1; 983}; 984 985union cvmx_pciercx_cfg075 { 986 uint32_t u32; 987 struct cvmx_pciercx_cfg075_s { 988 uint32_t reserved_3_31:29; 989 uint32_t fere:1; 990 uint32_t nfere:1; 991 uint32_t cere:1; 992 } s; 993 struct cvmx_pciercx_cfg075_s cn52xx; 994 struct cvmx_pciercx_cfg075_s cn52xxp1; 995 struct cvmx_pciercx_cfg075_s cn56xx; 996 struct cvmx_pciercx_cfg075_s cn56xxp1; 997}; 998 999union cvmx_pciercx_cfg076 { 1000 uint32_t u32;
1001 struct cvmx_pciercx_cfg076_s { 1002 uint32_t aeimn:5; 1003 uint32_t reserved_7_26:20; 1004 uint32_t femr:1; 1005 uint32_t nfemr:1; 1006 uint32_t fuf:1; 1007 uint32_t multi_efnfr:1; 1008 uint32_t efnfr:1; 1009 uint32_t multi_ecr:1; 1010 uint32_t ecr:1; 1011 } s; 1012 struct cvmx_pciercx_cfg076_s cn52xx; 1013 struct cvmx_pciercx_cfg076_s cn52xxp1; 1014 struct cvmx_pciercx_cfg076_s cn56xx; 1015 struct cvmx_pciercx_cfg076_s cn56xxp1; 1016}; 1017 1018union cvmx_pciercx_cfg077 { 1019 uint32_t u32; 1020 struct cvmx_pciercx_cfg077_s { 1021 uint32_t efnfsi:16; 1022 uint32_t ecsi:16; 1023 } s; 1024 struct cvmx_pciercx_cfg077_s cn52xx; 1025 struct cvmx_pciercx_cfg077_s cn52xxp1; 1026 struct cvmx_pciercx_cfg077_s cn56xx; 1027 struct cvmx_pciercx_cfg077_s cn56xxp1; 1028}; 1029 1030union cvmx_pciercx_cfg448 { 1031 uint32_t u32; 1032 struct cvmx_pciercx_cfg448_s { 1033 uint32_t rtl:16; 1034 uint32_t rtltl:16; 1035 } s; 1036 struct cvmx_pciercx_cfg448_s cn52xx; 1037 struct cvmx_pciercx_cfg448_s cn52xxp1; 1038 struct cvmx_pciercx_cfg448_s cn56xx; 1039 struct cvmx_pciercx_cfg448_s cn56xxp1; 1040}; 1041 1042union cvmx_pciercx_cfg449 { 1043 uint32_t u32; 1044 struct cvmx_pciercx_cfg449_s { 1045 uint32_t omr:32; 1046 } s; 1047 struct cvmx_pciercx_cfg449_s cn52xx; 1048 struct cvmx_pciercx_cfg449_s cn52xxp1; 1049 struct cvmx_pciercx_cfg449_s cn56xx; 1050 struct cvmx_pciercx_cfg449_s cn56xxp1; 1051}; 1052 1053union cvmx_pciercx_cfg450 { 1054 uint32_t u32; 1055 struct cvmx_pciercx_cfg450_s { 1056 uint32_t lpec:8; 1057 uint32_t reserved_22_23:2; 1058 uint32_t link_state:6; 1059 uint32_t force_link:1; 1060 uint32_t reserved_8_14:7; 1061 uint32_t link_num:8; 1062 } s; 1063 struct cvmx_pciercx_cfg450_s cn52xx; 1064 struct cvmx_pciercx_cfg450_s cn52xxp1; 1065 struct cvmx_pciercx_cfg450_s cn56xx; 1066 struct cvmx_pciercx_cfg450_s cn56xxp1; 1067}; 1068 1069union cvmx_pciercx_cfg451 { 1070 uint32_t u32; 1071 struct cvmx_pciercx_cfg451_s { 1072 uint32_t reserved_30_31:2; 1073 uint32_t l1el:3; 1074 uint32_t l0el:3; 1075 uint32_t n_fts_cc:8; 1076 uint32_t n_fts:8; 1077 uint32_t ack_freq:8; 1078 } s; 1079 struct cvmx_pciercx_cfg451_s cn52xx; 1080 struct cvmx_pciercx_cfg451_s cn52xxp1; 1081 struct cvmx_pciercx_cfg451_s cn56xx; 1082 struct cvmx_pciercx_cfg451_s cn56xxp1; 1083}; 1084 1085union cvmx_pciercx_cfg452 { 1086 uint32_t u32; 1087 struct cvmx_pciercx_cfg452_s { 1088 uint32_t reserved_26_31:6; 1089 uint32_t eccrc:1; 1090 uint32_t reserved_22_24:3; 1091 uint32_t lme:6; 1092 uint32_t reserved_8_15:8; 1093 uint32_t flm:1; 1094 uint32_t reserved_6_6:1; 1095 uint32_t dllle:1; 1096 uint32_t reserved_4_4:1; 1097 uint32_t ra:1; 1098 uint32_t le:1; 1099 uint32_t sd:1; 1100 uint32_t omr:1; 1101 } s; 1102 struct cvmx_pciercx_cfg452_s cn52xx; 1103 struct cvmx_pciercx_cfg452_s cn52xxp1; 1104 struct cvmx_pciercx_cfg452_s cn56xx; 1105 struct cvmx_pciercx_cfg452_s cn56xxp1; 1106}; 1107 1108union cvmx_pciercx_cfg453 { 1109 uint32_t u32; 1110 struct cvmx_pciercx_cfg453_s { 1111 uint32_t dlld:1; 1112 uint32_t reserved_26_30:5; 1113 uint32_t ack_nak:1; 1114 uint32_t fcd:1; 1115 uint32_t ilst:24; 1116 } s; 1117 struct cvmx_pciercx_cfg453_s cn52xx; 1118 struct cvmx_pciercx_cfg453_s cn52xxp1; 1119 struct cvmx_pciercx_cfg453_s cn56xx; 1120 struct cvmx_pciercx_cfg453_s cn56xxp1; 1121}; 1122 1123union cvmx_pciercx_cfg454 { 1124 uint32_t u32; 1125 struct cvmx_pciercx_cfg454_s { 1126 uint32_t reserved_29_31:3; 1127 uint32_t tmfcwt:5; 1128 uint32_t tmanlt:5; 1129 uint32_t tmrt:5; 1130 uint32_t reserved_11_13:3; 1131 uint32_t nskps:3; 1132 uint32_t reserved_4_7:4; 1133 uint32_t ntss:4; 1134 } s; 1135 struct cvmx_pciercx_cfg454_s cn52xx; 1136 struct cvmx_pciercx_cfg454_s cn52xxp1; 1137 struct cvmx_pciercx_cfg454_s cn56xx; 1138 struct cvmx_pciercx_cfg454_s cn56xxp1; 1139}; 1140 1141union cvmx_pciercx_cfg455 { 1142 uint32_t u32; 1143 struct cvmx_pciercx_cfg455_s { 1144 uint32_t m_cfg0_filt:1; 1145 uint32_t m_io_filt:1; 1146 uint32_t msg_ctrl:1; 1147 uint32_t m_cpl_ecrc_filt:1; 1148 uint32_t m_ecrc_filt:1; 1149 uint32_t m_cpl_len_err:1; 1150 uint32_t m_cpl_attr_err:1; 1151 uint32_t m_cpl_tc_err:1; 1152 uint32_t m_cpl_fun_err:1; 1153 uint32_t m_cpl_rid_err:1; 1154 uint32_t m_cpl_tag_err:1; 1155 uint32_t m_lk_filt:1; 1156 uint32_t m_cfg1_filt:1; 1157 uint32_t m_bar_match:1; 1158 uint32_t m_pois_filt:1; 1159 uint32_t m_fun:1; 1160 uint32_t dfcwt:1; 1161 uint32_t reserved_11_14:4; 1162 uint32_t skpiv:11; 1163 } s; 1164 struct cvmx_pciercx_cfg455_s cn52xx; 1165 struct cvmx_pciercx_cfg455_s cn52xxp1; 1166 struct cvmx_pciercx_cfg455_s cn56xx; 1167 struct cvmx_pciercx_cfg455_s cn56xxp1; 1168}; 1169 1170union cvmx_pciercx_cfg456 { 1171 uint32_t u32; 1172 struct cvmx_pciercx_cfg456_s { 1173 uint32_t reserved_2_31:30; 1174 uint32_t m_vend1_drp:1; 1175 uint32_t m_vend0_drp:1; 1176 } s; 1177 struct cvmx_pciercx_cfg456_s cn52xx; 1178 struct cvmx_pciercx_cfg456_s cn52xxp1; 1179 struct cvmx_pciercx_cfg456_s cn56xx; 1180 struct cvmx_pciercx_cfg456_s cn56xxp1; 1181}; 1182 1183union cvmx_pciercx_cfg458 { 1184 uint32_t u32; 1185 struct cvmx_pciercx_cfg458_s { 1186 uint32_t dbg_info_l32:32; 1187 } s; 1188 struct cvmx_pciercx_cfg458_s cn52xx; 1189 struct cvmx_pciercx_cfg458_s cn52xxp1; 1190 struct cvmx_pciercx_cfg458_s cn56xx; 1191 struct cvmx_pciercx_cfg458_s cn56xxp1; 1192}; 1193 1194union cvmx_pciercx_cfg459 { 1195 uint32_t u32; 1196 struct cvmx_pciercx_cfg459_s { 1197 uint32_t dbg_info_u32:32; 1198 } s; 1199 struct cvmx_pciercx_cfg459_s cn52xx; 1200 struct cvmx_pciercx_cfg459_s cn52xxp1; 1201 struct cvmx_pciercx_cfg459_s cn56xx; 1202 struct cvmx_pciercx_cfg459_s cn56xxp1; 1203}; 1204 1205union cvmx_pciercx_cfg460 { 1206 uint32_t u32; 1207 struct cvmx_pciercx_cfg460_s { 1208 uint32_t reserved_20_31:12; 1209 uint32_t tphfcc:8; 1210 uint32_t tpdfcc:12; 1211 } s; 1212 struct cvmx_pciercx_cfg460_s cn52xx; 1213 struct cvmx_pciercx_cfg460_s cn52xxp1; 1214 struct cvmx_pciercx_cfg460_s cn56xx; 1215 struct cvmx_pciercx_cfg460_s cn56xxp1; 1216}; 1217 1218union cvmx_pciercx_cfg461 { 1219 uint32_t u32; 1220 struct cvmx_pciercx_cfg461_s { 1221 uint32_t reserved_20_31:12; 1222 uint32_t tchfcc:8; 1223 uint32_t tcdfcc:12; 1224 } s; 1225 struct cvmx_pciercx_cfg461_s cn52xx; 1226 struct cvmx_pciercx_cfg461_s cn52xxp1; 1227 struct cvmx_pciercx_cfg461_s cn56xx; 1228 struct cvmx_pciercx_cfg461_s cn56xxp1; 1229}; 1230 1231union cvmx_pciercx_cfg462 { 1232 uint32_t u32; 1233 struct cvmx_pciercx_cfg462_s { 1234 uint32_t reserved_20_31:12; 1235 uint32_t tchfcc:8; 1236 uint32_t tcdfcc:12; 1237 } s; 1238 struct cvmx_pciercx_cfg462_s cn52xx; 1239 struct cvmx_pciercx_cfg462_s cn52xxp1; 1240 struct cvmx_pciercx_cfg462_s cn56xx; 1241 struct cvmx_pciercx_cfg462_s cn56xxp1; 1242}; 1243 1244union cvmx_pciercx_cfg463 { 1245 uint32_t u32; 1246 struct cvmx_pciercx_cfg463_s { 1247 uint32_t reserved_3_31:29; 1248 uint32_t rqne:1; 1249 uint32_t trbne:1; 1250 uint32_t rtlpfccnr:1; 1251 } s; 1252 struct cvmx_pciercx_cfg463_s cn52xx; 1253 struct cvmx_pciercx_cfg463_s cn52xxp1; 1254 struct cvmx_pciercx_cfg463_s cn56xx; 1255 struct cvmx_pciercx_cfg463_s cn56xxp1; 1256}; 1257 1258union cvmx_pciercx_cfg464 { 1259 uint32_t u32; 1260 struct cvmx_pciercx_cfg464_s { 1261 uint32_t wrr_vc3:8; 1262 uint32_t wrr_vc2:8; 1263 uint32_t wrr_vc1:8; 1264 uint32_t wrr_vc0:8; 1265 } s; 1266 struct cvmx_pciercx_cfg464_s cn52xx; 1267 struct cvmx_pciercx_cfg464_s cn52xxp1; 1268 struct cvmx_pciercx_cfg464_s cn56xx; 1269 struct cvmx_pciercx_cfg464_s cn56xxp1; 1270}; 1271 1272union cvmx_pciercx_cfg465 { 1273 uint32_t u32; 1274 struct cvmx_pciercx_cfg465_s { 1275 uint32_t wrr_vc7:8; 1276 uint32_t wrr_vc6:8; 1277 uint32_t wrr_vc5:8; 1278 uint32_t wrr_vc4:8; 1279 } s; 1280 struct cvmx_pciercx_cfg465_s cn52xx; 1281 struct cvmx_pciercx_cfg465_s cn52xxp1; 1282 struct cvmx_pciercx_cfg465_s cn56xx; 1283 struct cvmx_pciercx_cfg465_s cn56xxp1; 1284}; 1285 1286union cvmx_pciercx_cfg466 { 1287 uint32_t u32; 1288 struct cvmx_pciercx_cfg466_s { 1289 uint32_t rx_queue_order:1; 1290 uint32_t type_ordering:1; 1291 uint32_t reserved_24_29:6; 1292 uint32_t queue_mode:3; 1293 uint32_t reserved_20_20:1; 1294 uint32_t header_credits:8; 1295 uint32_t data_credits:12; 1296 } s; 1297 struct cvmx_pciercx_cfg466_s cn52xx; 1298 struct cvmx_pciercx_cfg466_s cn52xxp1; 1299 struct cvmx_pciercx_cfg466_s cn56xx; 1300 struct cvmx_pciercx_cfg466_s cn56xxp1; 1301}; 1302 1303union cvmx_pciercx_cfg467 { 1304 uint32_t u32; 1305 struct cvmx_pciercx_cfg467_s { 1306 uint32_t reserved_24_31:8; 1307 uint32_t queue_mode:3; 1308 uint32_t reserved_20_20:1; 1309 uint32_t header_credits:8; 1310 uint32_t data_credits:12; 1311 } s; 1312 struct cvmx_pciercx_cfg467_s cn52xx; 1313 struct cvmx_pciercx_cfg467_s cn52xxp1; 1314 struct cvmx_pciercx_cfg467_s cn56xx; 1315 struct cvmx_pciercx_cfg467_s cn56xxp1; 1316}; 1317 1318union cvmx_pciercx_cfg468 { 1319 uint32_t u32; 1320 struct cvmx_pciercx_cfg468_s { 1321 uint32_t reserved_24_31:8; 1322 uint32_t queue_mode:3; 1323 uint32_t reserved_20_20:1; 1324 uint32_t header_credits:8; 1325 uint32_t data_credits:12; 1326 } s; 1327 struct cvmx_pciercx_cfg468_s cn52xx; 1328 struct cvmx_pciercx_cfg468_s cn52xxp1; 1329 struct cvmx_pciercx_cfg468_s cn56xx; 1330 struct cvmx_pciercx_cfg468_s cn56xxp1; 1331}; 1332 1333union cvmx_pciercx_cfg490 { 1334 uint32_t u32; 1335 struct cvmx_pciercx_cfg490_s { 1336 uint32_t reserved_26_31:6; 1337 uint32_t header_depth:10; 1338 uint32_t reserved_14_15:2; 1339 uint32_t data_depth:14; 1340 } s; 1341 struct cvmx_pciercx_cfg490_s cn52xx; 1342 struct cvmx_pciercx_cfg490_s cn52xxp1; 1343 struct cvmx_pciercx_cfg490_s cn56xx; 1344 struct cvmx_pciercx_cfg490_s cn56xxp1; 1345}; 1346 1347union cvmx_pciercx_cfg491 { 1348 uint32_t u32; 1349 struct cvmx_pciercx_cfg491_s { 1350 uint32_t reserved_26_31:6; 1351 uint32_t header_depth:10; 1352 uint32_t reserved_14_15:2; 1353 uint32_t data_depth:14; 1354 } s; 1355 struct cvmx_pciercx_cfg491_s cn52xx; 1356 struct cvmx_pciercx_cfg491_s cn52xxp1; 1357 struct cvmx_pciercx_cfg491_s cn56xx; 1358 struct cvmx_pciercx_cfg491_s cn56xxp1; 1359}; 1360 1361union cvmx_pciercx_cfg492 { 1362 uint32_t u32; 1363 struct cvmx_pciercx_cfg492_s { 1364 uint32_t reserved_26_31:6; 1365 uint32_t header_depth:10; 1366 uint32_t reserved_14_15:2; 1367 uint32_t data_depth:14; 1368 } s; 1369 struct cvmx_pciercx_cfg492_s cn52xx; 1370 struct cvmx_pciercx_cfg492_s cn52xxp1; 1371 struct cvmx_pciercx_cfg492_s cn56xx; 1372 struct cvmx_pciercx_cfg492_s cn56xxp1; 1373}; 1374 1375union cvmx_pciercx_cfg516 { 1376 uint32_t u32; 1377 struct cvmx_pciercx_cfg516_s { 1378 uint32_t phy_stat:32; 1379 } s; 1380 struct cvmx_pciercx_cfg516_s cn52xx; 1381 struct cvmx_pciercx_cfg516_s cn52xxp1; 1382 struct cvmx_pciercx_cfg516_s cn56xx; 1383 struct cvmx_pciercx_cfg516_s cn56xxp1; 1384}; 1385 1386union cvmx_pciercx_cfg517 { 1387 uint32_t u32; 1388 struct cvmx_pciercx_cfg517_s { 1389 uint32_t phy_ctrl:32; 1390 } s; 1391 struct cvmx_pciercx_cfg517_s cn52xx; 1392 struct cvmx_pciercx_cfg517_s cn52xxp1; 1393 struct cvmx_pciercx_cfg517_s cn56xx; 1394 struct cvmx_pciercx_cfg517_s cn56xxp1; 1395}; 1396 1397#endif 1398