LXR linux/arch/mips/include/asm/processor.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 Waldorf GMBH
   7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8 * Copyright (C) 1996 Paul M. Antoine
   9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10 */
  11#ifndef _ASM_PROCESSOR_H
  12#define _ASM_PROCESSOR_H
  13
  14#include <linux/cpumask.h>
  15#include <linux/threads.h>
  16
  17#include <asm/cachectl.h>
  18#include <asm/cpu.h>
  19#include <asm/cpu-info.h>
  20#include <asm/mipsregs.h>
  21#include <asm/prefetch.h>
  22#include <asm/system.h>
  23
  24/*
  25 * Return current * instruction pointer ("program counter").
  26 */
  27#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  28
  29/*
  30 * System setup and hardware flags..
  31 */
  32extern void (*cpu_wait)(void);
  33
  34extern unsigned int vced_count, vcei_count;
  35
  36#ifdef CONFIG_32BIT
  37/*
  38 * User space process size: 2GB. This is hardcoded into a few places,
  39 * so don't change it unless you know what you are doing.
  40 */
  41#define TASK_SIZE       0x7fff8000UL
  42#define STACK_TOP       TASK_SIZE
  43
  44/*
  45 * This decides where the kernel will search for a free chunk of vm
  46 * space during mmap's.
  47 */
  48#define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
  49#endif
  50
  51#ifdef CONFIG_64BIT
  52/*
  53 * User space process size: 1TB. This is hardcoded into a few places,
  54 * so don't change it unless you know what you are doing.  TASK_SIZE
  55 * is limited to 1TB by the R4000 architecture; R10000 and better can
  56 * support 16TB; the architectural reserve for future expansion is
  57 * 8192EB ...
  58 */
  59#define TASK_SIZE32     0x7fff8000UL
  60#define TASK_SIZE       0x10000000000UL
  61#define STACK_TOP       \
  62      (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
  63
  64/*
  65 * This decides where the kernel will search for a free chunk of vm
  66 * space during mmap's.
  67 */
  68#define TASK_UNMAPPED_BASE                                              \
  69        (test_thread_flag(TIF_32BIT_ADDR) ?                             \
  70                PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
  71#define TASK_SIZE_OF(tsk)                                               \
  72        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
  73#endif
  74
  75#ifdef __KERNEL__
  76#define STACK_TOP_MAX   TASK_SIZE
  77#endif
  78
  79#define NUM_FPU_REGS    32
  80
  81typedef __u64 fpureg_t;
  82
  83/*
  84 * It would be nice to add some more fields for emulator statistics, but there
  85 * are a number of fixed offsets in offset.h and elsewhere that would have to
  86 * be recalculated by hand.  So the additional information will be private to
  87 * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
  88 */
  89
  90struct mips_fpu_struct {
  91        fpureg_t        fpr[NUM_FPU_REGS];
  92        unsigned int    fcr31;
  93};
  94
  95#define NUM_DSP_REGS   6
  96
  97typedef __u32 dspreg_t;
  98
  99struct mips_dsp_state {
 100        dspreg_t        dspr[NUM_DSP_REGS];
 101        unsigned int    dspcontrol;
 102};
 103
 104#define INIT_CPUMASK { \
 105        {0,} \
 106}
 107
 108struct mips3264_watch_reg_state {
 109        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 110           64 bit kernel.  We use unsigned long as it has the same
 111           property. */
 112        unsigned long watchlo[NUM_WATCH_REGS];
 113        /* Only the mask and IRW bits from watchhi. */
 114        u16 watchhi[NUM_WATCH_REGS];
 115};
 116
 117union mips_watch_reg_state {
 118        struct mips3264_watch_reg_state mips3264;
 119};
 120
 121#ifdef CONFIG_CPU_CAVIUM_OCTEON
 122
 123struct octeon_cop2_state {
 124        /* DMFC2 rt, 0x0201 */
 125        unsigned long   cop2_crc_iv;
 126        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 127        unsigned long   cop2_crc_length;
 128        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 129        unsigned long   cop2_crc_poly;
 130        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 131        unsigned long   cop2_llm_dat[2];
 132       /* DMFC2 rt, 0x0084 */
 133        unsigned long   cop2_3des_iv;
 134        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 135        unsigned long   cop2_3des_key[3];
 136        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 137        unsigned long   cop2_3des_result;
 138        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 139        unsigned long   cop2_aes_inp0;
 140        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 141        unsigned long   cop2_aes_iv[2];
 142        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 143         * rt, 0x0107 */
 144        unsigned long   cop2_aes_key[4];
 145        /* DMFC2 rt, 0x0110 */
 146        unsigned long   cop2_aes_keylen;
 147        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 148        unsigned long   cop2_aes_result[2];
 149        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 150         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 151         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 152         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 153         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 154        unsigned long   cop2_hsh_datw[15];
 155        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 156         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 157         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 158        unsigned long   cop2_hsh_ivw[8];
 159        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 160        unsigned long   cop2_gfm_mult[2];
 161        /* DMFC2 rt, 0x025E - Pass2 */
 162        unsigned long   cop2_gfm_poly;
 163        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 164        unsigned long   cop2_gfm_result[2];
 165};
 166#define INIT_OCTEON_COP2 {0,}
 167
 168struct octeon_cvmseg_state {
 169        unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 170                            [cpu_dcache_line_size() / sizeof(unsigned long)];
 171};
 172
 173#endif
 174
 175typedef struct {
 176        unsigned long seg;
 177} mm_segment_t;
 178
 179#define ARCH_MIN_TASKALIGN      8
 180
 181struct mips_abi;
 182
 183/*
 184 * If you change thread_struct remember to change the #defines below too!
 185 */
 186struct thread_struct {
 187        /* Saved main processor registers. */
 188        unsigned long reg16;
 189        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 190        unsigned long reg29, reg30, reg31;
 191
 192        /* Saved cp0 stuff. */
 193        unsigned long cp0_status;
 194
 195        /* Saved fpu/fpu emulator stuff. */
 196        struct mips_fpu_struct fpu;
 197#ifdef CONFIG_MIPS_MT_FPAFF
 198        /* Emulated instruction count */
 199        unsigned long emulated_fp;
 200        /* Saved per-thread scheduler affinity mask */
 201        cpumask_t user_cpus_allowed;
 202#endif /* CONFIG_MIPS_MT_FPAFF */
 203
 204        /* Saved state of the DSP ASE, if available. */
 205        struct mips_dsp_state dsp;
 206
 207        /* Saved watch register state, if available. */
 208        union mips_watch_reg_state watch;
 209
 210        /* Other stuff associated with the thread. */
 211        unsigned long cp0_badvaddr;     /* Last user fault */
 212        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 213        unsigned long error_code;
 214        unsigned long trap_no;
 215        unsigned long irix_trampoline;  /* Wheee... */
 216        unsigned long irix_oldctx;
 217#ifdef CONFIG_CPU_CAVIUM_OCTEON
 218    struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 219    struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 220#endif
 221        struct mips_abi *abi;
 222};
 223
 224#ifdef CONFIG_MIPS_MT_FPAFF
 225#define FPAFF_INIT                                              \
 226        .emulated_fp                    = 0,                    \
 227        .user_cpus_allowed              = INIT_CPUMASK,
 228#else
 229#define FPAFF_INIT
 230#endif /* CONFIG_MIPS_MT_FPAFF */
 231
 232#ifdef CONFIG_CPU_CAVIUM_OCTEON
 233#define OCTEON_INIT                                             \
 234        .cp2                    = INIT_OCTEON_COP2,
 235#else
 236#define OCTEON_INIT
 237#endif /* CONFIG_CPU_CAVIUM_OCTEON */
 238
 239#define INIT_THREAD  {                                          \
 240        /*                                                      \
 241         * Saved main processor registers                       \
 242         */                                                     \
 243        .reg16                  = 0,                            \
 244        .reg17                  = 0,                            \
 245        .reg18                  = 0,                            \
 246        .reg19                  = 0,                            \
 247        .reg20                  = 0,                            \
 248        .reg21                  = 0,                            \
 249        .reg22                  = 0,                            \
 250        .reg23                  = 0,                            \
 251        .reg29                  = 0,                            \
 252        .reg30                  = 0,                            \
 253        .reg31                  = 0,                            \
 254        /*                                                      \
 255         * Saved cp0 stuff                                      \
 256         */                                                     \
 257        .cp0_status             = 0,                            \
 258        /*                                                      \
 259         * Saved FPU/FPU emulator stuff                         \
 260         */                                                     \
 261        .fpu                    = {                             \
 262                .fpr            = {0,},                         \
 263                .fcr31          = 0,                            \
 264        },                                                      \
 265        /*                                                      \
 266         * FPU affinity state (null if not FPAFF)               \
 267         */                                                     \
 268        FPAFF_INIT                                              \
 269        /*                                                      \
 270         * Saved DSP stuff                                      \
 271         */                                                     \
 272        .dsp                    = {                             \
 273                .dspr           = {0, },                        \
 274                .dspcontrol     = 0,                            \
 275        },                                                      \
 276        /*                                                      \
 277         * saved watch register stuff                           \
 278         */                                                     \
 279        .watch = {{{0,},},},                                    \
 280        /*                                                      \
 281         * Other stuff associated with the process              \
 282         */                                                     \
 283        .cp0_badvaddr           = 0,                            \
 284        .cp0_baduaddr           = 0,                            \
 285        .error_code             = 0,                            \
 286        .trap_no                = 0,                            \
 287        .irix_trampoline        = 0,                            \
 288        .irix_oldctx            = 0,                            \
 289        /*                                                      \
 290         * Cavium Octeon specifics (null if not Octeon)         \
 291         */                                                     \
 292        OCTEON_INIT                                             \
 293}
 294
 295struct task_struct;
 296
 297/* Free all resources held by a thread. */
 298#define release_thread(thread) do { } while(0)
 299
 300/* Prepare to copy thread state - unlazy all lazy status */
 301#define prepare_to_copy(tsk)    do { } while (0)
 302
 303extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 304
 305extern unsigned long thread_saved_pc(struct task_struct *tsk);
 306
 307/*
 308 * Do necessary setup to start up a newly executed thread.
 309 */
 310extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 311
 312unsigned long get_wchan(struct task_struct *p);
 313
 314#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 315                         THREAD_SIZE - 32 - sizeof(struct pt_regs))
 316#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 317#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 318#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 319#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 320
 321#define cpu_relax()     barrier()
 322
 323/*
 324 * Return_address is a replacement for __builtin_return_address(count)
 325 * which on certain architectures cannot reasonably be implemented in GCC
 326 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 327 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 328 * aborts compilation on some CPUs.  It's simply not possible to unwind
 329 * some CPU's stackframes.
 330 *
 331 * __builtin_return_address works only for non-leaf functions.  We avoid the
 332 * overhead of a function call by forcing the compiler to save the return
 333 * address register on the stack.
 334 */
 335#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 336
 337#ifdef CONFIG_CPU_HAS_PREFETCH
 338
 339#define ARCH_HAS_PREFETCH
 340
 341static inline void prefetch(const void *addr)
 342{
 343        __asm__ __volatile__(
 344        "       .set    mips4           \n"
 345        "       pref    %0, (%1)        \n"
 346        "       .set    mips0           \n"
 347        :
 348        : "i" (Pref_Load), "r" (addr));
 349}
 350
 351#endif
 352
 353#endif /* _ASM_PROCESSOR_H */
 354