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14#include <linux/bug.h>
15#include <linux/compiler.h>
16#include <linux/init.h>
17#include <linux/mm.h>
18#include <linux/module.h>
19#include <linux/sched.h>
20#include <linux/smp.h>
21#include <linux/spinlock.h>
22#include <linux/kallsyms.h>
23#include <linux/bootmem.h>
24#include <linux/interrupt.h>
25#include <linux/ptrace.h>
26#include <linux/kgdb.h>
27#include <linux/kdebug.h>
28
29#include <asm/bootinfo.h>
30#include <asm/branch.h>
31#include <asm/break.h>
32#include <asm/cpu.h>
33#include <asm/dsp.h>
34#include <asm/fpu.h>
35#include <asm/fpu_emulator.h>
36#include <asm/mipsregs.h>
37#include <asm/mipsmtregs.h>
38#include <asm/module.h>
39#include <asm/pgtable.h>
40#include <asm/ptrace.h>
41#include <asm/sections.h>
42#include <asm/system.h>
43#include <asm/tlbdebug.h>
44#include <asm/traps.h>
45#include <asm/uaccess.h>
46#include <asm/watch.h>
47#include <asm/mmu_context.h>
48#include <asm/types.h>
49#include <asm/stacktrace.h>
50#include <asm/irq.h>
51
52extern void check_wait(void);
53extern asmlinkage void r4k_wait(void);
54extern asmlinkage void rollback_handle_int(void);
55extern asmlinkage void handle_int(void);
56extern asmlinkage void handle_tlbm(void);
57extern asmlinkage void handle_tlbl(void);
58extern asmlinkage void handle_tlbs(void);
59extern asmlinkage void handle_adel(void);
60extern asmlinkage void handle_ades(void);
61extern asmlinkage void handle_ibe(void);
62extern asmlinkage void handle_dbe(void);
63extern asmlinkage void handle_sys(void);
64extern asmlinkage void handle_bp(void);
65extern asmlinkage void handle_ri(void);
66extern asmlinkage void handle_ri_rdhwr_vivt(void);
67extern asmlinkage void handle_ri_rdhwr(void);
68extern asmlinkage void handle_cpu(void);
69extern asmlinkage void handle_ov(void);
70extern asmlinkage void handle_tr(void);
71extern asmlinkage void handle_fpe(void);
72extern asmlinkage void handle_mdmx(void);
73extern asmlinkage void handle_watch(void);
74extern asmlinkage void handle_mt(void);
75extern asmlinkage void handle_dsp(void);
76extern asmlinkage void handle_mcheck(void);
77extern asmlinkage void handle_reserved(void);
78
79extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
80 struct mips_fpu_struct *ctx, int has_fpu);
81
82#ifdef CONFIG_CPU_CAVIUM_OCTEON
83extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84#endif
85
86void (*board_be_init)(void);
87int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
88void (*board_nmi_handler_setup)(void);
89void (*board_ejtag_handler_setup)(void);
90void (*board_bind_eic_interrupt)(int irq, int regset);
91
92
93static void show_raw_backtrace(unsigned long reg29)
94{
95 unsigned long *sp = (unsigned long *)(reg29 & ~3);
96 unsigned long addr;
97
98 printk("Call Trace:");
99#ifdef CONFIG_KALLSYMS
100 printk("\n");
101#endif
102 while (!kstack_end(sp)) {
103 unsigned long __user *p =
104 (unsigned long __user *)(unsigned long)sp++;
105 if (__get_user(addr, p)) {
106 printk(" (Bad stack address)");
107 break;
108 }
109 if (__kernel_text_address(addr))
110 print_ip_sym(addr);
111 }
112 printk("\n");
113}
114
115#ifdef CONFIG_KALLSYMS
116int raw_show_trace;
117static int __init set_raw_show_trace(char *str)
118{
119 raw_show_trace = 1;
120 return 1;
121}
122__setup("raw_show_trace", set_raw_show_trace);
123#endif
124
125static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
126{
127 unsigned long sp = regs->regs[29];
128 unsigned long ra = regs->regs[31];
129 unsigned long pc = regs->cp0_epc;
130
131 if (raw_show_trace || !__kernel_text_address(pc)) {
132 show_raw_backtrace(sp);
133 return;
134 }
135 printk("Call Trace:\n");
136 do {
137 print_ip_sym(pc);
138 pc = unwind_stack(task, &sp, pc, &ra);
139 } while (pc);
140 printk("\n");
141}
142
143
144
145
146
147static void show_stacktrace(struct task_struct *task,
148 const struct pt_regs *regs)
149{
150 const int field = 2 * sizeof(unsigned long);
151 long stackdata;
152 int i;
153 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
154
155 printk("Stack :");
156 i = 0;
157 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
158 if (i && ((i % (64 / field)) == 0))
159 printk("\n ");
160 if (i > 39) {
161 printk(" ...");
162 break;
163 }
164
165 if (__get_user(stackdata, sp++)) {
166 printk(" (Bad stack address)");
167 break;
168 }
169
170 printk(" %0*lx", field, stackdata);
171 i++;
172 }
173 printk("\n");
174 show_backtrace(task, regs);
175}
176
177void show_stack(struct task_struct *task, unsigned long *sp)
178{
179 struct pt_regs regs;
180 if (sp) {
181 regs.regs[29] = (unsigned long)sp;
182 regs.regs[31] = 0;
183 regs.cp0_epc = 0;
184 } else {
185 if (task && task != current) {
186 regs.regs[29] = task->thread.reg29;
187 regs.regs[31] = 0;
188 regs.cp0_epc = task->thread.reg31;
189 } else {
190 prepare_frametrace(®s);
191 }
192 }
193 show_stacktrace(task, ®s);
194}
195
196
197
198
199void dump_stack(void)
200{
201 struct pt_regs regs;
202
203 prepare_frametrace(®s);
204 show_backtrace(current, ®s);
205}
206
207EXPORT_SYMBOL(dump_stack);
208
209static void show_code(unsigned int __user *pc)
210{
211 long i;
212 unsigned short __user *pc16 = NULL;
213
214 printk("\nCode:");
215
216 if ((unsigned long)pc & 1)
217 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
218 for(i = -3 ; i < 6 ; i++) {
219 unsigned int insn;
220 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
221 printk(" (Bad address in epc)\n");
222 break;
223 }
224 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
225 }
226}
227
228static void __show_regs(const struct pt_regs *regs)
229{
230 const int field = 2 * sizeof(unsigned long);
231 unsigned int cause = regs->cp0_cause;
232 int i;
233
234 printk("Cpu %d\n", smp_processor_id());
235
236
237
238
239 for (i = 0; i < 32; ) {
240 if ((i % 4) == 0)
241 printk("$%2d :", i);
242 if (i == 0)
243 printk(" %0*lx", field, 0UL);
244 else if (i == 26 || i == 27)
245 printk(" %*s", field, "");
246 else
247 printk(" %0*lx", field, regs->regs[i]);
248
249 i++;
250 if ((i % 4) == 0)
251 printk("\n");
252 }
253
254#ifdef CONFIG_CPU_HAS_SMARTMIPS
255 printk("Acx : %0*lx\n", field, regs->acx);
256#endif
257 printk("Hi : %0*lx\n", field, regs->hi);
258 printk("Lo : %0*lx\n", field, regs->lo);
259
260
261
262
263 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
264 (void *) regs->cp0_epc);
265 printk(" %s\n", print_tainted());
266 printk("ra : %0*lx %pS\n", field, regs->regs[31],
267 (void *) regs->regs[31]);
268
269 printk("Status: %08x ", (uint32_t) regs->cp0_status);
270
271 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
272 if (regs->cp0_status & ST0_KUO)
273 printk("KUo ");
274 if (regs->cp0_status & ST0_IEO)
275 printk("IEo ");
276 if (regs->cp0_status & ST0_KUP)
277 printk("KUp ");
278 if (regs->cp0_status & ST0_IEP)
279 printk("IEp ");
280 if (regs->cp0_status & ST0_KUC)
281 printk("KUc ");
282 if (regs->cp0_status & ST0_IEC)
283 printk("IEc ");
284 } else {
285 if (regs->cp0_status & ST0_KX)
286 printk("KX ");
287 if (regs->cp0_status & ST0_SX)
288 printk("SX ");
289 if (regs->cp0_status & ST0_UX)
290 printk("UX ");
291 switch (regs->cp0_status & ST0_KSU) {
292 case KSU_USER:
293 printk("USER ");
294 break;
295 case KSU_SUPERVISOR:
296 printk("SUPERVISOR ");
297 break;
298 case KSU_KERNEL:
299 printk("KERNEL ");
300 break;
301 default:
302 printk("BAD_MODE ");
303 break;
304 }
305 if (regs->cp0_status & ST0_ERL)
306 printk("ERL ");
307 if (regs->cp0_status & ST0_EXL)
308 printk("EXL ");
309 if (regs->cp0_status & ST0_IE)
310 printk("IE ");
311 }
312 printk("\n");
313
314 printk("Cause : %08x\n", cause);
315
316 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
317 if (1 <= cause && cause <= 5)
318 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
319
320 printk("PrId : %08x (%s)\n", read_c0_prid(),
321 cpu_name_string());
322}
323
324
325
326
327void show_regs(struct pt_regs *regs)
328{
329 __show_regs((struct pt_regs *)regs);
330}
331
332void show_registers(const struct pt_regs *regs)
333{
334 const int field = 2 * sizeof(unsigned long);
335
336 __show_regs(regs);
337 print_modules();
338 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
339 current->comm, current->pid, current_thread_info(), current,
340 field, current_thread_info()->tp_value);
341 if (cpu_has_userlocal) {
342 unsigned long tls;
343
344 tls = read_c0_userlocal();
345 if (tls != current_thread_info()->tp_value)
346 printk("*HwTLS: %0*lx\n", field, tls);
347 }
348
349 show_stacktrace(current, regs);
350 show_code((unsigned int __user *) regs->cp0_epc);
351 printk("\n");
352}
353
354static DEFINE_SPINLOCK(die_lock);
355
356void __noreturn die(const char * str, const struct pt_regs * regs)
357{
358 static int die_counter;
359#ifdef CONFIG_MIPS_MT_SMTC
360 unsigned long dvpret = dvpe();
361#endif
362
363 console_verbose();
364 spin_lock_irq(&die_lock);
365 bust_spinlocks(1);
366#ifdef CONFIG_MIPS_MT_SMTC
367 mips_mt_regdump(dvpret);
368#endif
369 printk("%s[#%d]:\n", str, ++die_counter);
370 show_registers(regs);
371 add_taint(TAINT_DIE);
372 spin_unlock_irq(&die_lock);
373
374 if (in_interrupt())
375 panic("Fatal exception in interrupt");
376
377 if (panic_on_oops) {
378 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
379 ssleep(5);
380 panic("Fatal exception");
381 }
382
383 do_exit(SIGSEGV);
384}
385
386extern struct exception_table_entry __start___dbe_table[];
387extern struct exception_table_entry __stop___dbe_table[];
388
389__asm__(
390" .section __dbe_table, \"a\"\n"
391" .previous \n");
392
393
394static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
395{
396 const struct exception_table_entry *e;
397
398 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
399 if (!e)
400 e = search_module_dbetables(addr);
401 return e;
402}
403
404asmlinkage void do_be(struct pt_regs *regs)
405{
406 const int field = 2 * sizeof(unsigned long);
407 const struct exception_table_entry *fixup = NULL;
408 int data = regs->cp0_cause & 4;
409 int action = MIPS_BE_FATAL;
410
411
412 if (data && !user_mode(regs))
413 fixup = search_dbe_tables(exception_epc(regs));
414
415 if (fixup)
416 action = MIPS_BE_FIXUP;
417
418 if (board_be_handler)
419 action = board_be_handler(regs, fixup != NULL);
420
421 switch (action) {
422 case MIPS_BE_DISCARD:
423 return;
424 case MIPS_BE_FIXUP:
425 if (fixup) {
426 regs->cp0_epc = fixup->nextinsn;
427 return;
428 }
429 break;
430 default:
431 break;
432 }
433
434
435
436
437 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
438 data ? "Data" : "Instruction",
439 field, regs->cp0_epc, field, regs->regs[31]);
440 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
441 == NOTIFY_STOP)
442 return;
443
444 die_if_kernel("Oops", regs);
445 force_sig(SIGBUS, current);
446}
447
448
449
450
451
452#define OPCODE 0xfc000000
453#define BASE 0x03e00000
454#define RT 0x001f0000
455#define OFFSET 0x0000ffff
456#define LL 0xc0000000
457#define SC 0xe0000000
458#define SPEC0 0x00000000
459#define SPEC3 0x7c000000
460#define RD 0x0000f800
461#define FUNC 0x0000003f
462#define SYNC 0x0000000f
463#define RDHWR 0x0000003b
464
465
466
467
468
469unsigned int ll_bit;
470struct task_struct *ll_task;
471
472static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
473{
474 unsigned long value, __user *vaddr;
475 long offset;
476
477
478
479
480
481
482
483 offset = opcode & OFFSET;
484 offset <<= 16;
485 offset >>= 16;
486
487 vaddr = (unsigned long __user *)
488 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
489
490 if ((unsigned long)vaddr & 3)
491 return SIGBUS;
492 if (get_user(value, vaddr))
493 return SIGSEGV;
494
495 preempt_disable();
496
497 if (ll_task == NULL || ll_task == current) {
498 ll_bit = 1;
499 } else {
500 ll_bit = 0;
501 }
502 ll_task = current;
503
504 preempt_enable();
505
506 regs->regs[(opcode & RT) >> 16] = value;
507
508 return 0;
509}
510
511static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
512{
513 unsigned long __user *vaddr;
514 unsigned long reg;
515 long offset;
516
517
518
519
520
521
522
523 offset = opcode & OFFSET;
524 offset <<= 16;
525 offset >>= 16;
526
527 vaddr = (unsigned long __user *)
528 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
529 reg = (opcode & RT) >> 16;
530
531 if ((unsigned long)vaddr & 3)
532 return SIGBUS;
533
534 preempt_disable();
535
536 if (ll_bit == 0 || ll_task != current) {
537 regs->regs[reg] = 0;
538 preempt_enable();
539 return 0;
540 }
541
542 preempt_enable();
543
544 if (put_user(regs->regs[reg], vaddr))
545 return SIGSEGV;
546
547 regs->regs[reg] = 1;
548
549 return 0;
550}
551
552
553
554
555
556
557
558
559static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
560{
561 if ((opcode & OPCODE) == LL)
562 return simulate_ll(regs, opcode);
563 if ((opcode & OPCODE) == SC)
564 return simulate_sc(regs, opcode);
565
566 return -1;
567}
568
569
570
571
572
573static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
574{
575 struct thread_info *ti = task_thread_info(current);
576
577 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
578 int rd = (opcode & RD) >> 11;
579 int rt = (opcode & RT) >> 16;
580 switch (rd) {
581 case 0:
582 regs->regs[rt] = smp_processor_id();
583 return 0;
584 case 1:
585 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
586 current_cpu_data.icache.linesz);
587 return 0;
588 case 2:
589 regs->regs[rt] = read_c0_count();
590 return 0;
591 case 3:
592 switch (current_cpu_data.cputype) {
593 case CPU_20KC:
594 case CPU_25KF:
595 regs->regs[rt] = 1;
596 break;
597 default:
598 regs->regs[rt] = 2;
599 }
600 return 0;
601 case 29:
602 regs->regs[rt] = ti->tp_value;
603 return 0;
604 default:
605 return -1;
606 }
607 }
608
609
610 return -1;
611}
612
613static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
614{
615 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
616 return 0;
617
618 return -1;
619}
620
621asmlinkage void do_ov(struct pt_regs *regs)
622{
623 siginfo_t info;
624
625 die_if_kernel("Integer overflow", regs);
626
627 info.si_code = FPE_INTOVF;
628 info.si_signo = SIGFPE;
629 info.si_errno = 0;
630 info.si_addr = (void __user *) regs->cp0_epc;
631 force_sig_info(SIGFPE, &info, current);
632}
633
634
635
636
637asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
638{
639 siginfo_t info;
640
641 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
642 == NOTIFY_STOP)
643 return;
644 die_if_kernel("FP exception in kernel code", regs);
645
646 if (fcr31 & FPU_CSR_UNI_X) {
647 int sig;
648
649
650
651
652
653
654
655
656
657
658
659
660 lose_fpu(1);
661
662
663 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1);
664
665
666
667
668
669 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
670
671
672 own_fpu(1);
673
674
675 if (sig)
676 force_sig(sig, current);
677
678 return;
679 } else if (fcr31 & FPU_CSR_INV_X)
680 info.si_code = FPE_FLTINV;
681 else if (fcr31 & FPU_CSR_DIV_X)
682 info.si_code = FPE_FLTDIV;
683 else if (fcr31 & FPU_CSR_OVF_X)
684 info.si_code = FPE_FLTOVF;
685 else if (fcr31 & FPU_CSR_UDF_X)
686 info.si_code = FPE_FLTUND;
687 else if (fcr31 & FPU_CSR_INE_X)
688 info.si_code = FPE_FLTRES;
689 else
690 info.si_code = __SI_FAULT;
691 info.si_signo = SIGFPE;
692 info.si_errno = 0;
693 info.si_addr = (void __user *) regs->cp0_epc;
694 force_sig_info(SIGFPE, &info, current);
695}
696
697static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
698 const char *str)
699{
700 siginfo_t info;
701 char b[40];
702
703 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
704 return;
705
706
707
708
709
710
711
712 switch (code) {
713 case BRK_OVERFLOW:
714 case BRK_DIVZERO:
715 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
716 die_if_kernel(b, regs);
717 if (code == BRK_DIVZERO)
718 info.si_code = FPE_INTDIV;
719 else
720 info.si_code = FPE_INTOVF;
721 info.si_signo = SIGFPE;
722 info.si_errno = 0;
723 info.si_addr = (void __user *) regs->cp0_epc;
724 force_sig_info(SIGFPE, &info, current);
725 break;
726 case BRK_BUG:
727 die_if_kernel("Kernel bug detected", regs);
728 force_sig(SIGTRAP, current);
729 break;
730 case BRK_MEMU:
731
732
733
734
735
736
737
738
739 if (do_dsemulret(regs))
740 return;
741
742 die_if_kernel("Math emu break/trap", regs);
743 force_sig(SIGTRAP, current);
744 break;
745 default:
746 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
747 die_if_kernel(b, regs);
748 force_sig(SIGTRAP, current);
749 }
750}
751
752asmlinkage void do_bp(struct pt_regs *regs)
753{
754 unsigned int opcode, bcode;
755
756 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
757 goto out_sigsegv;
758
759
760
761
762
763
764
765 bcode = ((opcode >> 6) & ((1 << 20) - 1));
766 if (bcode >= (1 << 10))
767 bcode >>= 10;
768
769 do_trap_or_bp(regs, bcode, "Break");
770 return;
771
772out_sigsegv:
773 force_sig(SIGSEGV, current);
774}
775
776asmlinkage void do_tr(struct pt_regs *regs)
777{
778 unsigned int opcode, tcode = 0;
779
780 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
781 goto out_sigsegv;
782
783
784 if (!(opcode & OPCODE))
785 tcode = ((opcode >> 6) & ((1 << 10) - 1));
786
787 do_trap_or_bp(regs, tcode, "Trap");
788 return;
789
790out_sigsegv:
791 force_sig(SIGSEGV, current);
792}
793
794asmlinkage void do_ri(struct pt_regs *regs)
795{
796 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
797 unsigned long old_epc = regs->cp0_epc;
798 unsigned int opcode = 0;
799 int status = -1;
800
801 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
802 == NOTIFY_STOP)
803 return;
804
805 die_if_kernel("Reserved instruction in kernel code", regs);
806
807 if (unlikely(compute_return_epc(regs) < 0))
808 return;
809
810 if (unlikely(get_user(opcode, epc) < 0))
811 status = SIGSEGV;
812
813 if (!cpu_has_llsc && status < 0)
814 status = simulate_llsc(regs, opcode);
815
816 if (status < 0)
817 status = simulate_rdhwr(regs, opcode);
818
819 if (status < 0)
820 status = simulate_sync(regs, opcode);
821
822 if (status < 0)
823 status = SIGILL;
824
825 if (unlikely(status > 0)) {
826 regs->cp0_epc = old_epc;
827 force_sig(status, current);
828 }
829}
830
831
832
833
834
835
836static void mt_ase_fp_affinity(void)
837{
838#ifdef CONFIG_MIPS_MT_FPAFF
839 if (mt_fpemul_threshold > 0 &&
840 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
841
842
843
844
845
846 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
847 cpumask_t tmask;
848
849 current->thread.user_cpus_allowed
850 = current->cpus_allowed;
851 cpus_and(tmask, current->cpus_allowed,
852 mt_fpu_cpumask);
853 set_cpus_allowed(current, tmask);
854 set_thread_flag(TIF_FPUBOUND);
855 }
856 }
857#endif
858}
859
860asmlinkage void do_cpu(struct pt_regs *regs)
861{
862 unsigned int __user *epc;
863 unsigned long old_epc;
864 unsigned int opcode;
865 unsigned int cpid;
866 int status;
867 unsigned long __maybe_unused flags;
868
869 die_if_kernel("do_cpu invoked from kernel context!", regs);
870
871 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
872
873 switch (cpid) {
874 case 0:
875 epc = (unsigned int __user *)exception_epc(regs);
876 old_epc = regs->cp0_epc;
877 opcode = 0;
878 status = -1;
879
880 if (unlikely(compute_return_epc(regs) < 0))
881 return;
882
883 if (unlikely(get_user(opcode, epc) < 0))
884 status = SIGSEGV;
885
886 if (!cpu_has_llsc && status < 0)
887 status = simulate_llsc(regs, opcode);
888
889 if (status < 0)
890 status = simulate_rdhwr(regs, opcode);
891
892 if (status < 0)
893 status = SIGILL;
894
895 if (unlikely(status > 0)) {
896 regs->cp0_epc = old_epc;
897 force_sig(status, current);
898 }
899
900 return;
901
902 case 1:
903 if (used_math())
904 own_fpu(1);
905 else {
906 init_fpu();
907 set_used_math();
908 }
909
910 if (!raw_cpu_has_fpu) {
911 int sig;
912 sig = fpu_emulator_cop1Handler(regs,
913 ¤t->thread.fpu, 0);
914 if (sig)
915 force_sig(sig, current);
916 else
917 mt_ase_fp_affinity();
918 }
919
920 return;
921
922 case 2:
923#ifdef CONFIG_CPU_CAVIUM_OCTEON
924 prefetch(¤t->thread.cp2);
925 local_irq_save(flags);
926 KSTK_STATUS(current) |= ST0_CU2;
927 status = read_c0_status();
928 write_c0_status(status | ST0_CU2);
929 octeon_cop2_restore(&(current->thread.cp2));
930 write_c0_status(status & ~ST0_CU2);
931 local_irq_restore(flags);
932 return;
933#endif
934 case 3:
935 break;
936 }
937
938 force_sig(SIGILL, current);
939}
940
941asmlinkage void do_mdmx(struct pt_regs *regs)
942{
943 force_sig(SIGILL, current);
944}
945
946
947
948
949asmlinkage void do_watch(struct pt_regs *regs)
950{
951 u32 cause;
952
953
954
955
956
957 cause = read_c0_cause();
958 cause &= ~(1 << 22);
959 write_c0_cause(cause);
960
961
962
963
964
965
966 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
967 mips_read_watch_registers();
968 local_irq_enable();
969 force_sig(SIGTRAP, current);
970 } else {
971 mips_clear_watch_registers();
972 local_irq_enable();
973 }
974}
975
976asmlinkage void do_mcheck(struct pt_regs *regs)
977{
978 const int field = 2 * sizeof(unsigned long);
979 int multi_match = regs->cp0_status & ST0_TS;
980
981 show_regs(regs);
982
983 if (multi_match) {
984 printk("Index : %0x\n", read_c0_index());
985 printk("Pagemask: %0x\n", read_c0_pagemask());
986 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
987 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
988 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
989 printk("\n");
990 dump_tlb_all();
991 }
992
993 show_code((unsigned int __user *) regs->cp0_epc);
994
995
996
997
998
999 panic("Caught Machine Check exception - %scaused by multiple "
1000 "matching entries in the TLB.",
1001 (multi_match) ? "" : "not ");
1002}
1003
1004asmlinkage void do_mt(struct pt_regs *regs)
1005{
1006 int subcode;
1007
1008 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1009 >> VPECONTROL_EXCPT_SHIFT;
1010 switch (subcode) {
1011 case 0:
1012 printk(KERN_DEBUG "Thread Underflow\n");
1013 break;
1014 case 1:
1015 printk(KERN_DEBUG "Thread Overflow\n");
1016 break;
1017 case 2:
1018 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1019 break;
1020 case 3:
1021 printk(KERN_DEBUG "Gating Storage Exception\n");
1022 break;
1023 case 4:
1024 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1025 break;
1026 case 5:
1027 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1028 break;
1029 default:
1030 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1031 subcode);
1032 break;
1033 }
1034 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1035
1036 force_sig(SIGILL, current);
1037}
1038
1039
1040asmlinkage void do_dsp(struct pt_regs *regs)
1041{
1042 if (cpu_has_dsp)
1043 panic("Unexpected DSP exception\n");
1044
1045 force_sig(SIGILL, current);
1046}
1047
1048asmlinkage void do_reserved(struct pt_regs *regs)
1049{
1050
1051
1052
1053
1054
1055 show_regs(regs);
1056 panic("Caught reserved exception %ld - should not happen.",
1057 (regs->cp0_cause & 0x7f) >> 2);
1058}
1059
1060static int __initdata l1parity = 1;
1061static int __init nol1parity(char *s)
1062{
1063 l1parity = 0;
1064 return 1;
1065}
1066__setup("nol1par", nol1parity);
1067static int __initdata l2parity = 1;
1068static int __init nol2parity(char *s)
1069{
1070 l2parity = 0;
1071 return 1;
1072}
1073__setup("nol2par", nol2parity);
1074
1075
1076
1077
1078
1079static inline void parity_protection_init(void)
1080{
1081 switch (current_cpu_type()) {
1082 case CPU_24K:
1083 case CPU_34K:
1084 case CPU_74K:
1085 case CPU_1004K:
1086 {
1087#define ERRCTL_PE 0x80000000
1088#define ERRCTL_L2P 0x00800000
1089 unsigned long errctl;
1090 unsigned int l1parity_present, l2parity_present;
1091
1092 errctl = read_c0_ecc();
1093 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1094
1095
1096 write_c0_ecc(errctl | ERRCTL_PE);
1097 back_to_back_c0_hazard();
1098 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1099
1100
1101 write_c0_ecc(errctl|ERRCTL_L2P);
1102 back_to_back_c0_hazard();
1103 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1104
1105 if (l1parity_present && l2parity_present) {
1106 if (l1parity)
1107 errctl |= ERRCTL_PE;
1108 if (l1parity ^ l2parity)
1109 errctl |= ERRCTL_L2P;
1110 } else if (l1parity_present) {
1111 if (l1parity)
1112 errctl |= ERRCTL_PE;
1113 } else if (l2parity_present) {
1114 if (l2parity)
1115 errctl |= ERRCTL_L2P;
1116 } else {
1117
1118 }
1119
1120 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1121
1122 write_c0_ecc(errctl);
1123 back_to_back_c0_hazard();
1124 errctl = read_c0_ecc();
1125 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1126
1127 if (l1parity_present)
1128 printk(KERN_INFO "Cache parity protection %sabled\n",
1129 (errctl & ERRCTL_PE) ? "en" : "dis");
1130
1131 if (l2parity_present) {
1132 if (l1parity_present && l1parity)
1133 errctl ^= ERRCTL_L2P;
1134 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1135 (errctl & ERRCTL_L2P) ? "en" : "dis");
1136 }
1137 }
1138 break;
1139
1140 case CPU_5KC:
1141 write_c0_ecc(0x80000000);
1142 back_to_back_c0_hazard();
1143
1144 printk(KERN_INFO "Cache parity protection %sabled\n",
1145 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1146 break;
1147 case CPU_20KC:
1148 case CPU_25KF:
1149
1150 printk(KERN_INFO "Enable cache parity protection for "
1151 "MIPS 20KC/25KF CPUs.\n");
1152 clear_c0_status(ST0_DE);
1153 break;
1154 default:
1155 break;
1156 }
1157}
1158
1159asmlinkage void cache_parity_error(void)
1160{
1161 const int field = 2 * sizeof(unsigned long);
1162 unsigned int reg_val;
1163
1164
1165 printk("Cache error exception:\n");
1166 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1167 reg_val = read_c0_cacheerr();
1168 printk("c0_cacheerr == %08x\n", reg_val);
1169
1170 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1171 reg_val & (1<<30) ? "secondary" : "primary",
1172 reg_val & (1<<31) ? "data" : "insn");
1173 printk("Error bits: %s%s%s%s%s%s%s\n",
1174 reg_val & (1<<29) ? "ED " : "",
1175 reg_val & (1<<28) ? "ET " : "",
1176 reg_val & (1<<26) ? "EE " : "",
1177 reg_val & (1<<25) ? "EB " : "",
1178 reg_val & (1<<24) ? "EI " : "",
1179 reg_val & (1<<23) ? "E1 " : "",
1180 reg_val & (1<<22) ? "E0 " : "");
1181 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1182
1183#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1184 if (reg_val & (1<<22))
1185 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1186
1187 if (reg_val & (1<<23))
1188 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1189#endif
1190
1191 panic("Can't handle the cache error!");
1192}
1193
1194
1195
1196
1197
1198void ejtag_exception_handler(struct pt_regs *regs)
1199{
1200 const int field = 2 * sizeof(unsigned long);
1201 unsigned long depc, old_epc;
1202 unsigned int debug;
1203
1204 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1205 depc = read_c0_depc();
1206 debug = read_c0_debug();
1207 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1208 if (debug & 0x80000000) {
1209
1210
1211
1212
1213
1214
1215 old_epc = regs->cp0_epc;
1216 regs->cp0_epc = depc;
1217 __compute_return_epc(regs);
1218 depc = regs->cp0_epc;
1219 regs->cp0_epc = old_epc;
1220 } else
1221 depc += 4;
1222 write_c0_depc(depc);
1223
1224#if 0
1225 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1226 write_c0_debug(debug | 0x100);
1227#endif
1228}
1229
1230
1231
1232
1233NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1234{
1235 bust_spinlocks(1);
1236 printk("NMI taken!!!!\n");
1237 die("NMI", regs);
1238}
1239
1240#define VECTORSPACING 0x100
1241
1242unsigned long ebase;
1243unsigned long exception_handlers[32];
1244unsigned long vi_handlers[64];
1245
1246
1247
1248
1249
1250
1251void *set_except_vector(int n, void *addr)
1252{
1253 unsigned long handler = (unsigned long) addr;
1254 unsigned long old_handler = exception_handlers[n];
1255
1256 exception_handlers[n] = handler;
1257 if (n == 0 && cpu_has_divec) {
1258 *(u32 *)(ebase + 0x200) = 0x08000000 |
1259 (0x03ffffff & (handler >> 2));
1260 local_flush_icache_range(ebase + 0x200, ebase + 0x204);
1261 }
1262 return (void *)old_handler;
1263}
1264
1265static asmlinkage void do_default_vi(void)
1266{
1267 show_regs(get_irq_regs());
1268 panic("Caught unexpected vectored interrupt.");
1269}
1270
1271static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1272{
1273 unsigned long handler;
1274 unsigned long old_handler = vi_handlers[n];
1275 int srssets = current_cpu_data.srsets;
1276 u32 *w;
1277 unsigned char *b;
1278
1279 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1280
1281 if (addr == NULL) {
1282 handler = (unsigned long) do_default_vi;
1283 srs = 0;
1284 } else
1285 handler = (unsigned long) addr;
1286 vi_handlers[n] = (unsigned long) addr;
1287
1288 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1289
1290 if (srs >= srssets)
1291 panic("Shadow register set %d not supported", srs);
1292
1293 if (cpu_has_veic) {
1294 if (board_bind_eic_interrupt)
1295 board_bind_eic_interrupt(n, srs);
1296 } else if (cpu_has_vint) {
1297
1298 if (srssets > 1)
1299 change_c0_srsmap(0xf << n*4, srs << n*4);
1300 }
1301
1302 if (srs == 0) {
1303
1304
1305
1306
1307
1308 extern char except_vec_vi, except_vec_vi_lui;
1309 extern char except_vec_vi_ori, except_vec_vi_end;
1310 extern char rollback_except_vec_vi;
1311 char *vec_start = (cpu_wait == r4k_wait) ?
1312 &rollback_except_vec_vi : &except_vec_vi;
1313#ifdef CONFIG_MIPS_MT_SMTC
1314
1315
1316
1317
1318
1319 extern char except_vec_vi_mori;
1320 const int mori_offset = &except_vec_vi_mori - vec_start;
1321#endif
1322 const int handler_len = &except_vec_vi_end - vec_start;
1323 const int lui_offset = &except_vec_vi_lui - vec_start;
1324 const int ori_offset = &except_vec_vi_ori - vec_start;
1325
1326 if (handler_len > VECTORSPACING) {
1327
1328
1329
1330
1331 panic("VECTORSPACING too small");
1332 }
1333
1334 memcpy(b, vec_start, handler_len);
1335#ifdef CONFIG_MIPS_MT_SMTC
1336 BUG_ON(n > 7);
1337
1338 w = (u32 *)(b + mori_offset);
1339 *w = (*w & 0xffff0000) | (0x100 << n);
1340#endif
1341 w = (u32 *)(b + lui_offset);
1342 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1343 w = (u32 *)(b + ori_offset);
1344 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1345 local_flush_icache_range((unsigned long)b,
1346 (unsigned long)(b+handler_len));
1347 }
1348 else {
1349
1350
1351
1352
1353
1354
1355 w = (u32 *)b;
1356 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff);
1357 *w = 0;
1358 local_flush_icache_range((unsigned long)b,
1359 (unsigned long)(b+8));
1360 }
1361
1362 return (void *)old_handler;
1363}
1364
1365void *set_vi_handler(int n, vi_handler_t addr)
1366{
1367 return set_vi_srs_handler(n, addr, 0);
1368}
1369
1370
1371
1372
1373asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1374asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1375
1376extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1377extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1378
1379extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1380extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1381
1382#ifdef CONFIG_SMP
1383static int smp_save_fp_context(struct sigcontext __user *sc)
1384{
1385 return raw_cpu_has_fpu
1386 ? _save_fp_context(sc)
1387 : fpu_emulator_save_context(sc);
1388}
1389
1390static int smp_restore_fp_context(struct sigcontext __user *sc)
1391{
1392 return raw_cpu_has_fpu
1393 ? _restore_fp_context(sc)
1394 : fpu_emulator_restore_context(sc);
1395}
1396#endif
1397
1398static inline void signal_init(void)
1399{
1400#ifdef CONFIG_SMP
1401
1402 save_fp_context = smp_save_fp_context;
1403 restore_fp_context = smp_restore_fp_context;
1404#else
1405 if (cpu_has_fpu) {
1406 save_fp_context = _save_fp_context;
1407 restore_fp_context = _restore_fp_context;
1408 } else {
1409 save_fp_context = fpu_emulator_save_context;
1410 restore_fp_context = fpu_emulator_restore_context;
1411 }
1412#endif
1413}
1414
1415#ifdef CONFIG_MIPS32_COMPAT
1416
1417
1418
1419
1420asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1421asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1422
1423extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1424extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1425
1426extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1427extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1428
1429static inline void signal32_init(void)
1430{
1431 if (cpu_has_fpu) {
1432 save_fp_context32 = _save_fp_context32;
1433 restore_fp_context32 = _restore_fp_context32;
1434 } else {
1435 save_fp_context32 = fpu_emulator_save_context32;
1436 restore_fp_context32 = fpu_emulator_restore_context32;
1437 }
1438}
1439#endif
1440
1441extern void cpu_cache_init(void);
1442extern void tlb_init(void);
1443extern void flush_tlb_handlers(void);
1444
1445
1446
1447
1448int cp0_compare_irq;
1449
1450
1451
1452
1453int cp0_perfcount_irq;
1454EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1455
1456static int __cpuinitdata noulri;
1457
1458static int __init ulri_disable(char *s)
1459{
1460 pr_info("Disabling ulri\n");
1461 noulri = 1;
1462
1463 return 1;
1464}
1465__setup("noulri", ulri_disable);
1466
1467void __cpuinit per_cpu_trap_init(void)
1468{
1469 unsigned int cpu = smp_processor_id();
1470 unsigned int status_set = ST0_CU0;
1471#ifdef CONFIG_MIPS_MT_SMTC
1472 int secondaryTC = 0;
1473 int bootTC = (cpu == 0);
1474
1475
1476
1477
1478
1479
1480
1481 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1482 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1483 secondaryTC = 1;
1484#endif
1485
1486
1487
1488
1489
1490
1491
1492#ifdef CONFIG_64BIT
1493 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1494#endif
1495 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1496 status_set |= ST0_XX;
1497 if (cpu_has_dsp)
1498 status_set |= ST0_MX;
1499
1500 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1501 status_set);
1502
1503 if (cpu_has_mips_r2) {
1504 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
1505
1506 if (!noulri && cpu_has_userlocal)
1507 enable |= (1 << 29);
1508
1509 write_c0_hwrena(enable);
1510 }
1511
1512#ifdef CONFIG_MIPS_MT_SMTC
1513 if (!secondaryTC) {
1514#endif
1515
1516 if (cpu_has_veic || cpu_has_vint) {
1517 unsigned long sr = set_c0_status(ST0_BEV);
1518 write_c0_ebase(ebase);
1519 write_c0_status(sr);
1520
1521 change_c0_intctl(0x3e0, VECTORSPACING);
1522 }
1523 if (cpu_has_divec) {
1524 if (cpu_has_mipsmt) {
1525 unsigned int vpflags = dvpe();
1526 set_c0_cause(CAUSEF_IV);
1527 evpe(vpflags);
1528 } else
1529 set_c0_cause(CAUSEF_IV);
1530 }
1531
1532
1533
1534
1535
1536
1537
1538 if (cpu_has_mips_r2) {
1539 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1540 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1541 if (cp0_perfcount_irq == cp0_compare_irq)
1542 cp0_perfcount_irq = -1;
1543 } else {
1544 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1545 cp0_perfcount_irq = -1;
1546 }
1547
1548#ifdef CONFIG_MIPS_MT_SMTC
1549 }
1550#endif
1551
1552 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1553 TLBMISS_HANDLER_SETUP();
1554
1555 atomic_inc(&init_mm.mm_count);
1556 current->active_mm = &init_mm;
1557 BUG_ON(current->mm);
1558 enter_lazy_tlb(&init_mm, current);
1559
1560#ifdef CONFIG_MIPS_MT_SMTC
1561 if (bootTC) {
1562#endif
1563 cpu_cache_init();
1564 tlb_init();
1565#ifdef CONFIG_MIPS_MT_SMTC
1566 } else if (!secondaryTC) {
1567
1568
1569
1570
1571 write_c0_pagemask(PM_DEFAULT_MASK);
1572 write_c0_wired(0);
1573 }
1574#endif
1575}
1576
1577
1578void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1579{
1580 memcpy((void *)(ebase + offset), addr, size);
1581 local_flush_icache_range(ebase + offset, ebase + offset + size);
1582}
1583
1584static char panic_null_cerr[] __cpuinitdata =
1585 "Trying to set NULL cache error exception handler";
1586
1587
1588
1589
1590
1591
1592void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1593 unsigned long size)
1594{
1595#ifdef CONFIG_32BIT
1596 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1597#endif
1598#ifdef CONFIG_64BIT
1599 unsigned long uncached_ebase = TO_UNCAC(ebase);
1600#endif
1601
1602 if (!addr)
1603 panic(panic_null_cerr);
1604
1605 memcpy((void *)(uncached_ebase + offset), addr, size);
1606}
1607
1608static int __initdata rdhwr_noopt;
1609static int __init set_rdhwr_noopt(char *str)
1610{
1611 rdhwr_noopt = 1;
1612 return 1;
1613}
1614
1615__setup("rdhwr_noopt", set_rdhwr_noopt);
1616
1617void __init trap_init(void)
1618{
1619 extern char except_vec3_generic, except_vec3_r4000;
1620 extern char except_vec4;
1621 unsigned long i;
1622 int rollback;
1623
1624 check_wait();
1625 rollback = (cpu_wait == r4k_wait);
1626
1627#if defined(CONFIG_KGDB)
1628 if (kgdb_early_setup)
1629 return;
1630#endif
1631
1632 if (cpu_has_veic || cpu_has_vint) {
1633 unsigned long size = 0x200 + VECTORSPACING*64;
1634 ebase = (unsigned long)
1635 __alloc_bootmem(size, 1 << fls(size), 0);
1636 } else {
1637 ebase = CAC_BASE;
1638 if (cpu_has_mips_r2)
1639 ebase += (read_c0_ebase() & 0x3ffff000);
1640 }
1641
1642 per_cpu_trap_init();
1643
1644
1645
1646
1647
1648
1649 set_handler(0x180, &except_vec3_generic, 0x80);
1650
1651
1652
1653
1654 for (i = 0; i <= 31; i++)
1655 set_except_vector(i, handle_reserved);
1656
1657
1658
1659
1660
1661 if (cpu_has_ejtag && board_ejtag_handler_setup)
1662 board_ejtag_handler_setup();
1663
1664
1665
1666
1667 if (cpu_has_watch)
1668 set_except_vector(23, handle_watch);
1669
1670
1671
1672
1673 if (cpu_has_veic || cpu_has_vint) {
1674 int nvec = cpu_has_veic ? 64 : 8;
1675 for (i = 0; i < nvec; i++)
1676 set_vi_handler(i, NULL);
1677 }
1678 else if (cpu_has_divec)
1679 set_handler(0x200, &except_vec4, 0x8);
1680
1681
1682
1683
1684
1685 parity_protection_init();
1686
1687
1688
1689
1690
1691
1692 if (board_be_init)
1693 board_be_init();
1694
1695 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1696 set_except_vector(1, handle_tlbm);
1697 set_except_vector(2, handle_tlbl);
1698 set_except_vector(3, handle_tlbs);
1699
1700 set_except_vector(4, handle_adel);
1701 set_except_vector(5, handle_ades);
1702
1703 set_except_vector(6, handle_ibe);
1704 set_except_vector(7, handle_dbe);
1705
1706 set_except_vector(8, handle_sys);
1707 set_except_vector(9, handle_bp);
1708 set_except_vector(10, rdhwr_noopt ? handle_ri :
1709 (cpu_has_vtag_icache ?
1710 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1711 set_except_vector(11, handle_cpu);
1712 set_except_vector(12, handle_ov);
1713 set_except_vector(13, handle_tr);
1714
1715 if (current_cpu_type() == CPU_R6000 ||
1716 current_cpu_type() == CPU_R6000A) {
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727 }
1728
1729
1730 if (board_nmi_handler_setup)
1731 board_nmi_handler_setup();
1732
1733 if (cpu_has_fpu && !cpu_has_nofpuex)
1734 set_except_vector(15, handle_fpe);
1735
1736 set_except_vector(22, handle_mdmx);
1737
1738 if (cpu_has_mcheck)
1739 set_except_vector(24, handle_mcheck);
1740
1741 if (cpu_has_mipsmt)
1742 set_except_vector(25, handle_mt);
1743
1744 set_except_vector(26, handle_dsp);
1745
1746 if (cpu_has_vce)
1747
1748 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1749 else if (cpu_has_4kex)
1750 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1751 else
1752 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1753
1754 signal_init();
1755#ifdef CONFIG_MIPS32_COMPAT
1756 signal32_init();
1757#endif
1758
1759 local_flush_icache_range(ebase, ebase + 0x400);
1760 flush_tlb_handlers();
1761
1762 sort_extable(__start___dbe_table, __stop___dbe_table);
1763}
1764