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15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18
19#include <asm/inst.h>
20#include <asm/elf.h>
21#include <asm/bugs.h>
22
23#include "uasm.h"
24
25enum fields {
26 RS = 0x001,
27 RT = 0x002,
28 RD = 0x004,
29 RE = 0x008,
30 SIMM = 0x010,
31 UIMM = 0x020,
32 BIMM = 0x040,
33 JIMM = 0x080,
34 FUNC = 0x100,
35 SET = 0x200
36};
37
38#define OP_MASK 0x3f
39#define OP_SH 26
40#define RS_MASK 0x1f
41#define RS_SH 21
42#define RT_MASK 0x1f
43#define RT_SH 16
44#define RD_MASK 0x1f
45#define RD_SH 11
46#define RE_MASK 0x1f
47#define RE_SH 6
48#define IMM_MASK 0xffff
49#define IMM_SH 0
50#define JIMM_MASK 0x3ffffff
51#define JIMM_SH 0
52#define FUNC_MASK 0x3f
53#define FUNC_SH 0
54#define SET_MASK 0x7
55#define SET_SH 0
56
57enum opcode {
58 insn_invalid,
59 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
63 insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
64 insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
68};
69
70struct insn {
71 enum opcode opcode;
72 u32 match;
73 enum fields fields;
74};
75
76
77#define M(a, b, c, d, e, f) \
78 ((a) << OP_SH \
79 | (b) << RS_SH \
80 | (c) << RT_SH \
81 | (d) << RD_SH \
82 | (e) << RE_SH \
83 | (f) << FUNC_SH)
84
85static struct insn insn_table[] __cpuinitdata = {
86 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
87 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
88 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
89 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
90 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
91 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
92 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
93 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
94 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
95 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
96 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
97 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
98 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
99 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
100 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
101 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
102 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
103 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
107 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
108 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
109 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
110 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
111 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
112 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
113 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
114 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
115 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
116 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
117 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
118 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
119 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
120 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
122 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
124 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
125 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
126 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
127 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
128 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
129 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
130 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
131 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
132 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
133 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
134 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
135 { insn_invalid, 0, 0 }
136};
137
138#undef M
139
140static inline __cpuinit u32 build_rs(u32 arg)
141{
142 if (arg & ~RS_MASK)
143 printk(KERN_WARNING "Micro-assembler field overflow\n");
144
145 return (arg & RS_MASK) << RS_SH;
146}
147
148static inline __cpuinit u32 build_rt(u32 arg)
149{
150 if (arg & ~RT_MASK)
151 printk(KERN_WARNING "Micro-assembler field overflow\n");
152
153 return (arg & RT_MASK) << RT_SH;
154}
155
156static inline __cpuinit u32 build_rd(u32 arg)
157{
158 if (arg & ~RD_MASK)
159 printk(KERN_WARNING "Micro-assembler field overflow\n");
160
161 return (arg & RD_MASK) << RD_SH;
162}
163
164static inline __cpuinit u32 build_re(u32 arg)
165{
166 if (arg & ~RE_MASK)
167 printk(KERN_WARNING "Micro-assembler field overflow\n");
168
169 return (arg & RE_MASK) << RE_SH;
170}
171
172static inline __cpuinit u32 build_simm(s32 arg)
173{
174 if (arg > 0x7fff || arg < -0x8000)
175 printk(KERN_WARNING "Micro-assembler field overflow\n");
176
177 return arg & 0xffff;
178}
179
180static inline __cpuinit u32 build_uimm(u32 arg)
181{
182 if (arg & ~IMM_MASK)
183 printk(KERN_WARNING "Micro-assembler field overflow\n");
184
185 return arg & IMM_MASK;
186}
187
188static inline __cpuinit u32 build_bimm(s32 arg)
189{
190 if (arg > 0x1ffff || arg < -0x20000)
191 printk(KERN_WARNING "Micro-assembler field overflow\n");
192
193 if (arg & 0x3)
194 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
195
196 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
197}
198
199static inline __cpuinit u32 build_jimm(u32 arg)
200{
201 if (arg & ~((JIMM_MASK) << 2))
202 printk(KERN_WARNING "Micro-assembler field overflow\n");
203
204 return (arg >> 2) & JIMM_MASK;
205}
206
207static inline __cpuinit u32 build_func(u32 arg)
208{
209 if (arg & ~FUNC_MASK)
210 printk(KERN_WARNING "Micro-assembler field overflow\n");
211
212 return arg & FUNC_MASK;
213}
214
215static inline __cpuinit u32 build_set(u32 arg)
216{
217 if (arg & ~SET_MASK)
218 printk(KERN_WARNING "Micro-assembler field overflow\n");
219
220 return arg & SET_MASK;
221}
222
223
224
225
226
227static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
228{
229 struct insn *ip = NULL;
230 unsigned int i;
231 va_list ap;
232 u32 op;
233
234 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
235 if (insn_table[i].opcode == opc) {
236 ip = &insn_table[i];
237 break;
238 }
239
240 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
241 panic("Unsupported Micro-assembler instruction %d", opc);
242
243 op = ip->match;
244 va_start(ap, opc);
245 if (ip->fields & RS)
246 op |= build_rs(va_arg(ap, u32));
247 if (ip->fields & RT)
248 op |= build_rt(va_arg(ap, u32));
249 if (ip->fields & RD)
250 op |= build_rd(va_arg(ap, u32));
251 if (ip->fields & RE)
252 op |= build_re(va_arg(ap, u32));
253 if (ip->fields & SIMM)
254 op |= build_simm(va_arg(ap, s32));
255 if (ip->fields & UIMM)
256 op |= build_uimm(va_arg(ap, u32));
257 if (ip->fields & BIMM)
258 op |= build_bimm(va_arg(ap, s32));
259 if (ip->fields & JIMM)
260 op |= build_jimm(va_arg(ap, u32));
261 if (ip->fields & FUNC)
262 op |= build_func(va_arg(ap, u32));
263 if (ip->fields & SET)
264 op |= build_set(va_arg(ap, u32));
265 va_end(ap);
266
267 **buf = op;
268 (*buf)++;
269}
270
271#define I_u1u2u3(op) \
272Ip_u1u2u3(op) \
273{ \
274 build_insn(buf, insn##op, a, b, c); \
275}
276
277#define I_u2u1u3(op) \
278Ip_u2u1u3(op) \
279{ \
280 build_insn(buf, insn##op, b, a, c); \
281}
282
283#define I_u3u1u2(op) \
284Ip_u3u1u2(op) \
285{ \
286 build_insn(buf, insn##op, b, c, a); \
287}
288
289#define I_u1u2s3(op) \
290Ip_u1u2s3(op) \
291{ \
292 build_insn(buf, insn##op, a, b, c); \
293}
294
295#define I_u2s3u1(op) \
296Ip_u2s3u1(op) \
297{ \
298 build_insn(buf, insn##op, c, a, b); \
299}
300
301#define I_u2u1s3(op) \
302Ip_u2u1s3(op) \
303{ \
304 build_insn(buf, insn##op, b, a, c); \
305}
306
307#define I_u1u2(op) \
308Ip_u1u2(op) \
309{ \
310 build_insn(buf, insn##op, a, b); \
311}
312
313#define I_u1s2(op) \
314Ip_u1s2(op) \
315{ \
316 build_insn(buf, insn##op, a, b); \
317}
318
319#define I_u1(op) \
320Ip_u1(op) \
321{ \
322 build_insn(buf, insn##op, a); \
323}
324
325#define I_0(op) \
326Ip_0(op) \
327{ \
328 build_insn(buf, insn##op); \
329}
330
331I_u2u1s3(_addiu)
332I_u3u1u2(_addu)
333I_u2u1u3(_andi)
334I_u3u1u2(_and)
335I_u1u2s3(_beq)
336I_u1u2s3(_beql)
337I_u1s2(_bgez)
338I_u1s2(_bgezl)
339I_u1s2(_bltz)
340I_u1s2(_bltzl)
341I_u1u2s3(_bne)
342I_u2s3u1(_cache)
343I_u1u2u3(_dmfc0)
344I_u1u2u3(_dmtc0)
345I_u2u1s3(_daddiu)
346I_u3u1u2(_daddu)
347I_u2u1u3(_dsll)
348I_u2u1u3(_dsll32)
349I_u2u1u3(_dsra)
350I_u2u1u3(_dsrl)
351I_u2u1u3(_dsrl32)
352I_u3u1u2(_dsubu)
353I_0(_eret)
354I_u1(_j)
355I_u1(_jal)
356I_u1(_jr)
357I_u2s3u1(_ld)
358I_u2s3u1(_ll)
359I_u2s3u1(_lld)
360I_u1s2(_lui)
361I_u2s3u1(_lw)
362I_u1u2u3(_mfc0)
363I_u1u2u3(_mtc0)
364I_u2u1u3(_ori)
365I_u2s3u1(_pref)
366I_0(_rfe)
367I_u2s3u1(_sc)
368I_u2s3u1(_scd)
369I_u2s3u1(_sd)
370I_u2u1u3(_sll)
371I_u2u1u3(_sra)
372I_u2u1u3(_srl)
373I_u3u1u2(_subu)
374I_u2s3u1(_sw)
375I_0(_tlbp)
376I_0(_tlbwi)
377I_0(_tlbwr)
378I_u3u1u2(_xor)
379I_u2u1u3(_xori)
380
381
382void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
383{
384 (*lab)->addr = addr;
385 (*lab)->lab = lid;
386 (*lab)++;
387}
388
389int __cpuinit uasm_in_compat_space_p(long addr)
390{
391
392#ifdef CONFIG_64BIT
393 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
394#else
395 return 1;
396#endif
397}
398
399static int __cpuinit uasm_rel_highest(long val)
400{
401#ifdef CONFIG_64BIT
402 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
403#else
404 return 0;
405#endif
406}
407
408static int __cpuinit uasm_rel_higher(long val)
409{
410#ifdef CONFIG_64BIT
411 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
412#else
413 return 0;
414#endif
415}
416
417int __cpuinit uasm_rel_hi(long val)
418{
419 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
420}
421
422int __cpuinit uasm_rel_lo(long val)
423{
424 return ((val & 0xffff) ^ 0x8000) - 0x8000;
425}
426
427void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
428{
429 if (!uasm_in_compat_space_p(addr)) {
430 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
431 if (uasm_rel_higher(addr))
432 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
433 if (uasm_rel_hi(addr)) {
434 uasm_i_dsll(buf, rs, rs, 16);
435 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
436 uasm_i_dsll(buf, rs, rs, 16);
437 } else
438 uasm_i_dsll32(buf, rs, rs, 0);
439 } else
440 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
441}
442
443void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
444{
445 UASM_i_LA_mostly(buf, rs, addr);
446 if (uasm_rel_lo(addr)) {
447 if (!uasm_in_compat_space_p(addr))
448 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
449 else
450 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
451 }
452}
453
454
455void __cpuinit
456uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
457{
458 (*rel)->addr = addr;
459 (*rel)->type = R_MIPS_PC16;
460 (*rel)->lab = lid;
461 (*rel)++;
462}
463
464static inline void __cpuinit
465__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
466{
467 long laddr = (long)lab->addr;
468 long raddr = (long)rel->addr;
469
470 switch (rel->type) {
471 case R_MIPS_PC16:
472 *rel->addr |= build_bimm(laddr - (raddr + 4));
473 break;
474
475 default:
476 panic("Unsupported Micro-assembler relocation %d",
477 rel->type);
478 }
479}
480
481void __cpuinit
482uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
483{
484 struct uasm_label *l;
485
486 for (; rel->lab != UASM_LABEL_INVALID; rel++)
487 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
488 if (rel->lab == l->lab)
489 __resolve_relocs(rel, l);
490}
491
492void __cpuinit
493uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
494{
495 for (; rel->lab != UASM_LABEL_INVALID; rel++)
496 if (rel->addr >= first && rel->addr < end)
497 rel->addr += off;
498}
499
500void __cpuinit
501uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
502{
503 for (; lab->lab != UASM_LABEL_INVALID; lab++)
504 if (lab->addr >= first && lab->addr < end)
505 lab->addr += off;
506}
507
508void __cpuinit
509uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
510 u32 *end, u32 *target)
511{
512 long off = (long)(target - first);
513
514 memcpy(target, first, (end - first) * sizeof(u32));
515
516 uasm_move_relocs(rel, first, end, off);
517 uasm_move_labels(lab, first, end, off);
518}
519
520int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
521{
522 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
523 if (rel->addr == addr
524 && (rel->type == R_MIPS_PC16
525 || rel->type == R_MIPS_26))
526 return 1;
527 }
528
529 return 0;
530}
531
532
533void __cpuinit
534uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
535{
536 uasm_r_mips_pc16(r, *p, lid);
537 uasm_i_bltz(p, reg, 0);
538}
539
540void __cpuinit
541uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
542{
543 uasm_r_mips_pc16(r, *p, lid);
544 uasm_i_b(p, 0);
545}
546
547void __cpuinit
548uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
549{
550 uasm_r_mips_pc16(r, *p, lid);
551 uasm_i_beqz(p, reg, 0);
552}
553
554void __cpuinit
555uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
556{
557 uasm_r_mips_pc16(r, *p, lid);
558 uasm_i_beqzl(p, reg, 0);
559}
560
561void __cpuinit
562uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
563 unsigned int reg2, int lid)
564{
565 uasm_r_mips_pc16(r, *p, lid);
566 uasm_i_bne(p, reg1, reg2, 0);
567}
568
569void __cpuinit
570uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
571{
572 uasm_r_mips_pc16(r, *p, lid);
573 uasm_i_bnez(p, reg, 0);
574}
575
576void __cpuinit
577uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
578{
579 uasm_r_mips_pc16(r, *p, lid);
580 uasm_i_bgezl(p, reg, 0);
581}
582
583void __cpuinit
584uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
585{
586 uasm_r_mips_pc16(r, *p, lid);
587 uasm_i_bgez(p, reg, 0);
588}
589
