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8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/time.h>
16
17#include <asm/octeon/octeon.h>
18#include <asm/octeon/cvmx-npi-defs.h>
19#include <asm/octeon/cvmx-pci-defs.h>
20#include <asm/octeon/pci-octeon.h>
21
22#define USE_OCTEON_INTERNAL_ARBITER
23
24
25
26
27
28
29#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
30#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
31
32
33#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
34
35
36
37
38union octeon_pci_address {
39 uint64_t u64;
40 struct {
41 uint64_t upper:2;
42 uint64_t reserved:13;
43 uint64_t io:1;
44 uint64_t did:5;
45 uint64_t subdid:3;
46 uint64_t reserved2:4;
47 uint64_t endian_swap:2;
48 uint64_t reserved3:10;
49 uint64_t bus:8;
50 uint64_t dev:5;
51 uint64_t func:3;
52 uint64_t reg:8;
53 } s;
54};
55
56int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
57 u8 slot, u8 pin);
58enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
59
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70
71int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
72{
73 if (octeon_pcibios_map_irq)
74 return octeon_pcibios_map_irq(dev, slot, pin);
75 else
76 panic("octeon_pcibios_map_irq not set.");
77}
78
79
80
81
82
83int pcibios_plat_dev_init(struct pci_dev *dev)
84{
85 uint16_t config;
86 uint32_t dconfig;
87 int pos;
88
89
90
91
92
93
94
95 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
96
97 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
98
99
100
101 pci_read_config_word(dev, PCI_COMMAND, &config);
102 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
103 pci_write_config_word(dev, PCI_COMMAND, config);
104
105 if (dev->subordinate) {
106
107 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
108
109 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
110 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
111 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
112 }
113
114
115 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
116 if (pos) {
117
118 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
119
120 config |= PCI_EXP_DEVCTL_CERE;
121
122 config |= PCI_EXP_DEVCTL_NFERE;
123
124 config |= PCI_EXP_DEVCTL_FERE;
125
126 config |= PCI_EXP_DEVCTL_URRE;
127 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
128 }
129
130
131 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
132 if (pos) {
133
134 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
135 &dconfig);
136 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
137 dconfig);
138
139
140 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
141
142
143
144
145
146
147
148 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
149 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
150
151
152 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
153
154 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
155
156 if (config & PCI_ERR_CAP_ECRC_GENC)
157 config |= PCI_ERR_CAP_ECRC_GENE;
158
159 if (config & PCI_ERR_CAP_ECRC_CHKC)
160 config |= PCI_ERR_CAP_ECRC_CHKE;
161 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
162
163
164 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
165 PCI_ERR_ROOT_CMD_COR_EN |
166 PCI_ERR_ROOT_CMD_NONFATAL_EN |
167 PCI_ERR_ROOT_CMD_FATAL_EN);
168
169 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
170 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
171 }
172
173 return 0;
174}
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184
185const char *octeon_get_pci_interrupts(void)
186{
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207
208 switch (octeon_bootinfo->board_type) {
209 case CVMX_BOARD_TYPE_NAO38:
210
211 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
212 case CVMX_BOARD_TYPE_THUNDER:
213 return "";
214 case CVMX_BOARD_TYPE_EBH3000:
215 return "";
216 case CVMX_BOARD_TYPE_EBH3100:
217 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
218 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
219 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
220 case CVMX_BOARD_TYPE_BBGW_REF:
221 return "AABCD";
222 default:
223 return "";
224 }
225}
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237
238int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
239 u8 slot, u8 pin)
240{
241 int irq_num;
242 const char *interrupts;
243 int dev_num;
244
245
246 interrupts = octeon_get_pci_interrupts();
247
248 dev_num = dev->devfn >> 3;
249 if (dev_num < strlen(interrupts))
250 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
251 OCTEON_IRQ_PCI_INT0;
252 else
253 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
254 return irq_num;
255}
256
257
258
259
260
261static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
262 int reg, int size, u32 *val)
263{
264 union octeon_pci_address pci_addr;
265
266 pci_addr.u64 = 0;
267 pci_addr.s.upper = 2;
268 pci_addr.s.io = 1;
269 pci_addr.s.did = 3;
270 pci_addr.s.subdid = 1;
271 pci_addr.s.endian_swap = 1;
272 pci_addr.s.bus = bus->number;
273 pci_addr.s.dev = devfn >> 3;
274 pci_addr.s.func = devfn & 0x7;
275 pci_addr.s.reg = reg;
276
277#if PCI_CONFIG_SPACE_DELAY
278 udelay(PCI_CONFIG_SPACE_DELAY);
279#endif
280 switch (size) {
281 case 4:
282 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
283 return PCIBIOS_SUCCESSFUL;
284 case 2:
285 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
286 return PCIBIOS_SUCCESSFUL;
287 case 1:
288 *val = cvmx_read64_uint8(pci_addr.u64);
289 return PCIBIOS_SUCCESSFUL;
290 }
291 return PCIBIOS_FUNC_NOT_SUPPORTED;
292}
293
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295
296
297
298static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
299 int reg, int size, u32 val)
300{
301 union octeon_pci_address pci_addr;
302
303 pci_addr.u64 = 0;
304 pci_addr.s.upper = 2;
305 pci_addr.s.io = 1;
306 pci_addr.s.did = 3;
307 pci_addr.s.subdid = 1;
308 pci_addr.s.endian_swap = 1;
309 pci_addr.s.bus = bus->number;
310 pci_addr.s.dev = devfn >> 3;
311 pci_addr.s.func = devfn & 0x7;
312 pci_addr.s.reg = reg;
313
314#if PCI_CONFIG_SPACE_DELAY
315 udelay(PCI_CONFIG_SPACE_DELAY);
316#endif
317 switch (size) {
318 case 4:
319 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
320 return PCIBIOS_SUCCESSFUL;
321 case 2:
322 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
323 return PCIBIOS_SUCCESSFUL;
324 case 1:
325 cvmx_write64_uint8(pci_addr.u64, val);
326 return PCIBIOS_SUCCESSFUL;
327 }
328 return PCIBIOS_FUNC_NOT_SUPPORTED;
329}
330
331
332static struct pci_ops octeon_pci_ops = {
333 octeon_read_config,
334 octeon_write_config,
335};
336
337static struct resource octeon_pci_mem_resource = {
338 .start = 0,
339 .end = 0,
340 .name = "Octeon PCI MEM",
341 .flags = IORESOURCE_MEM,
342};
343
344
345
346
347
348static struct resource octeon_pci_io_resource = {
349 .start = 0x4000,
350 .end = OCTEON_PCI_IOSPACE_SIZE - 1,
351 .name = "Octeon PCI IO",
352 .flags = IORESOURCE_IO,
353};
354
355static struct pci_controller octeon_pci_controller = {
356 .pci_ops = &octeon_pci_ops,
357 .mem_resource = &octeon_pci_mem_resource,
358 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
359 .io_resource = &octeon_pci_io_resource,
360 .io_offset = 0,
361 .io_map_base = OCTEON_PCI_IOSPACE_BASE,
362};
363
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365
366
367
368static void octeon_pci_initialize(void)
369{
370 union cvmx_pci_cfg01 cfg01;
371 union cvmx_npi_ctl_status ctl_status;
372 union cvmx_pci_ctl_status_2 ctl_status_2;
373 union cvmx_pci_cfg19 cfg19;
374 union cvmx_pci_cfg16 cfg16;
375 union cvmx_pci_cfg22 cfg22;
376 union cvmx_pci_cfg56 cfg56;
377
378
379 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
380 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
381
382 udelay(2000);
383
384 ctl_status.u64 = 0;
385 ctl_status.s.max_word = 1;
386 ctl_status.s.timer = 1;
387 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
388
389
390
391 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
392 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
393
394 udelay(2000);
395
396 ctl_status_2.u32 = 0;
397 ctl_status_2.s.tsr_hwm = 1;
398
399 ctl_status_2.s.bar2pres = 1;
400 ctl_status_2.s.bar2_enb = 1;
401 ctl_status_2.s.bar2_cax = 1;
402 ctl_status_2.s.bar2_esx = 1;
403 ctl_status_2.s.pmo_amod = 1;
404 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
405
406 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
407 ctl_status_2.s.bb1_siz = 1;
408 ctl_status_2.s.bb_ca = 1;
409 ctl_status_2.s.bb_es = 1;
410 ctl_status_2.s.bb1 = 1;
411 ctl_status_2.s.bb0 = 1;
412 }
413
414 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
415 udelay(2000);
416
417 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
418 pr_notice("PCI Status: %s %s-bit\n",
419 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
420 ctl_status_2.s.ap_64ad ? "64" : "32");
421
422 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
423 union cvmx_pci_cnt_reg cnt_reg_start;
424 union cvmx_pci_cnt_reg cnt_reg_end;
425 unsigned long cycles, pci_clock;
426
427 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
428 cycles = read_c0_cvmcount();
429 udelay(1000);
430 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
431 cycles = read_c0_cvmcount() - cycles;
432 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
433 (cycles / (mips_hpt_frequency / 1000000));
434 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
435 }
436
437
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441
442
443
444
445 if (ctl_status_2.s.ap_pcix) {
446 cfg19.u32 = 0;
447
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458
459 cfg19.s.tdomc = 4;
460
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470
471 cfg19.s.mdrrmc = 2;
472
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482
483 cfg19.s.mrbcm = 1;
484 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
485 }
486
487
488 cfg01.u32 = 0;
489 cfg01.s.msae = 1;
490 cfg01.s.me = 1;
491 cfg01.s.pee = 1;
492 cfg01.s.see = 1;
493 cfg01.s.fbbe = 1;
494
495 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
496
497#ifdef USE_OCTEON_INTERNAL_ARBITER
498
499
500
501
502
503 {
504 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
505
506 pci_int_arb_cfg.u64 = 0;
507 pci_int_arb_cfg.s.en = 1;
508 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
509 }
510#endif
511
512
513
514
515
516
517 cfg16.u32 = 0;
518 cfg16.s.mltd = 1;
519 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
520
521
522
523
524
525 cfg22.u32 = 0;
526
527 cfg22.s.mrv = 0xff;
528
529
530
531
532 cfg22.s.flush = 1;
533 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
534
535
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537
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540
541
542 cfg56.u32 = 0;
543 cfg56.s.pxcid = 7;
544 cfg56.s.ncp = 0xe8;
545 cfg56.s.dpere = 1;
546 cfg56.s.roe = 1;
547 cfg56.s.mmbc = 1;
548
549 cfg56.s.most = 3;
550
551
552 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
553
554
555
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560
561
562
563 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
564 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
565 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
566}
567
568
569
570
571
572static int __init octeon_pci_setup(void)
573{
574 union cvmx_npi_mem_access_subidx mem_access;
575 int index;
576
577
578 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
579 return 0;
580
581
582 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
583
584
585 if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
586 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
587 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
588 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
589 else
590 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
591
592
593 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
594 ioport_resource.start = 0;
595 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
596 if (!octeon_is_pci_host()) {
597 pr_notice("Not in host mode, PCI Controller not initialized\n");
598 return 0;
599 }
600
601 pr_notice("%s Octeon big bar support\n",
602 (octeon_dma_bar_type ==
603 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
604
605 octeon_pci_initialize();
606
607 mem_access.u64 = 0;
608 mem_access.s.esr = 1;
609 mem_access.s.esw = 1;
610 mem_access.s.nsr = 0;
611 mem_access.s.nsw = 0;
612 mem_access.s.ror = 0;
613 mem_access.s.row = 0;
614 mem_access.s.ba = 0;
615 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
616
617
618
619
620
621
622
623 octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
624 octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
625
626
627 for (index = 0; index < 32; index++)
628 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
629
630 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
631
632 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
633 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
634
635
636
637
638
639 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
640 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
641
642
643 octeon_pci_mem_resource.start =
644 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
645 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
646 octeon_pci_mem_resource.end =
647 octeon_pci_mem_resource.start + (1ul << 30);
648 } else {
649
650 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
651 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
652
653
654 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
655 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
656
657
658 octeon_pci_mem_resource.start =
659 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
660 (4ul << 10);
661 octeon_pci_mem_resource.end =
662 octeon_pci_mem_resource.start + (1ul << 30);
663 }
664
665 register_pci_controller(&octeon_pci_controller);
666
667
668
669
670
671 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
672 return 0;
673}
674
675arch_initcall(octeon_pci_setup);
676